JP2003122736A - Matrix arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform an arithmetic operation for calculating a solution of a simultaneous linear equation to be expressed in a form including upper triangular matrix or a lower triangular matrix by forward substitution or backward substitution at extremely high speed by using a small-sized and low power consumption unit. SOLUTION: This matrix arithmetic unit constituted of hardware is provided with product-sum operation parts (101, 102, 103, 105, 106, 107, 108, 109, 110) and a linear operation part for performing a prescribed linear operation for a result of a product-sum operation. In a period when an arithmetic operation for finding out a solution of the n-th linear equation is performed in the linear operation part, a product-sum operation about a partial term without including the solution of the n-th linear equation among product-sum operation terms required for finding out a solution of the next (n+1)th linear operation is precedently executed by the product-sum operation parts and a plurality of multipliers of a multiplication part 107 are used on the time-sharing basis.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix calculation device that can be used to obtain a solution of a simultaneous linear equation expressed in a format including an upper triangular matrix or a lower triangular matrix.

[0002]

2. Description of the Related Art When performing a numerical calculation (matrix operation) using an electronic computer, a symmetric matrix is Cholesky decomposed into a product form of an upper triangular matrix and a lower triangular matrix, and simultaneous linear equations are obtained by forward substitution or backward substitution. In some cases, the method of sequentially obtaining the solution of the equation may be adopted.

Such matrix calculation is performed by a plurality of processors (DSP 1002, 10) as shown in FIG.
04). The matrix operation using a plurality of processors is described in, for example, Japanese Patent Laid-Open No. 2000-339296.

[0004]

In the method of performing a matrix operation using a plurality of processors, it is necessary to transfer information between the processors, so that the processing is delayed, and the operation is basically performed by software. Therefore, there is a limit to the speedup.

In addition, the device tends to be large, small,
It is difficult to mount it on a mobile device such as a mobile phone, which is strictly required to be lightweight or low in power consumption.

It is an object of the present invention to significantly improve the processing capability of a matrix operation device, reduce the device size, and reduce power consumption.

[0007]

A matrix arithmetic unit of the present invention is a cyclic arithmetic processing circuit composed of hardware, which sequentially obtains solutions of simultaneous linear equations by forward substitution or backward substitution. Arrange the circuit elements for performing multiplication, division, addition, and subtraction (substantially performing the operations) necessary to obtain the solution of the linear equation along the operation procedure (operation flow). , Perform processing in a pipeline while creating a reasonable data flow. Since the processing is performed by hardware, the arithmetic processing can be executed with the maximum processing capacity of the hardware implemented as an LSI.
As a result, for example, a speedup 10 times faster than the conventional one is achieved.

Further, in the matrix operation device of the present invention, the number of multipliers is reasonably and effectively reduced by using the multipliers in a time-division manner, thereby promoting miniaturization and low power consumption of the device. .

That is, when n simultaneous linear equations are sequentially solved by forward substitution, for example, in order to solve the n-th linear equation, the first to (n-
1) It is necessary to perform an operation (for example, a product-sum operation) using the solution of the first-order linear equation. Therefore, if the solution of the immediately preceding (n−1) -th order linear equation cannot be determined, the n-th first-order equation Can't find the solution.

If this is strictly considered, it means that while the solution of the immediately preceding linear equation is being obtained, the processing concerning the term including the solution of the immediately preceding linear equation cannot be performed. On the other hand, the first one we've been looking for in the past
This means that the processing for the term including the solution of the (n-2) th linear equation is feasible.

Focusing on this point, in the matrix operation device of the present invention, the operation terms are roughly classified into a group having a term including a solution of the immediately preceding linear equation and a group having only a term not including the solution. Then, while seeking the solution of the immediately preceding linear equation, among the operating terms for solving the next linear equation, the arithmetic expression of a group of only the terms not including the solution of the immediately preceding linear equation is executed in advance. Then, the result is held temporarily.

Then, when the solution of the immediately preceding linear equation is obtained, the term including the solution is operated, and the result is summed with the result of the previously executed operation to solve the n-th linear equation. This completes the operation related to the term including all the solutions of the linear equations from the 1st to (n-1) th, which are necessary for

Even if a large number of multipliers are prepared without using the time division, the processing of the solution of the next linear equation is eventually waited until the solution of the immediately previous linear equation is obtained. The processing time is almost the same as when using time division. That is, according to the present invention, it is possible to reasonably realize miniaturization of a circuit and reduction of power consumption while performing high-speed processing.

The matrix calculation device of the present invention can be applied to the forward substitution calculation when obtaining the solution of the simultaneous linear equations including the lower triangular matrix. Further, it can be applied to backward substitution calculation when obtaining a solution of simultaneous linear equations including an upper triangular matrix. Further, when obtaining the solution of the simultaneous linear equations including the symmetric matrix, the symmetric matrix can be applied to the operation of the simultaneous linear equations modified by the Cholesky decomposition or the modified Cholesky decomposition. Further, it can be applied to a matrix calculator capable of performing an inverse matrix calculation utilizing Cholesky decomposition.

The matrix operation device of the present invention includes a receiving device having a joint detection demodulation function, a receiving device having an AAA (adaptive array) based on the least square error method, a transversal filter, or the like. It can be installed in a receiving device in which the adaptive equalizer provided is installed.

Since the matrix calculation device of the present invention is small in size, low in power consumption, and capable of ultra-high-speed processing, it has sufficient capability as a calculation processing device in a mobile station device such as a mobile phone or a wireless base station device. It can be demonstrated.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION First, a method of solving simultaneous linear equations using Cholesky decomposition (LU decomposition (triangular decomposition)) will be described. Here, a case will be described in which a solution of a large-scale simultaneous linear equation as shown by the following equation (1) is obtained. Fd = r (1) where F is a known matrix of n rows × n columns, and r is n
It is a known matrix of rows x 1 columns, and the matrix that d finds (n rows x 1
Column).

According to the LU decomposition method, the known symmetric matrix F can be expressed by the following equation (2) by the lower triangular matrix L and its transposed matrix L ^T. F = LL ^T ...... (2) but ^{LL T d = r ......... (3} ) Equation (3) is to solve for d, the process is 2
It is roughly divided into stage calculations. Below, the first stage process and the second
The process of steps will be described.

(First stage) When L ^T d = z is set, (3)
The equation is transformed into the equation (4). Lz = r (4) The matrix z is obtained from the equation (4). Since the matrix L is a lower triangular matrix, the calculation formula for obtaining the matrix z can be expressed as the following formula (5).

[0020]

[Equation 1] However, i = 2, 3 ... N.

The matrix z is obtained as follows. First, the element z ₁ in the first row is calculated. Next, using the calculated z ₁ , the element z ₂ in the second row is calculated according to the equation (5). Thereafter, similarly, z _i is calculated using the calculation results of z ₁ to z _i-1 . In this way, the operation of calculating in the order of the first element to the Nth element of the matrix z is called forward substitution.

(Second Step) Using the matrix z calculated in the first step, the solution d is obtained from the expression L ^T d = z replaced in the first step. Here, the matrix L ^T is an upper triangular matrix because it is a transposed matrix of the lower triangular matrix L.

Therefore, the calculation formula for obtaining the solution d of the simultaneous linear equations is the following formula (6).

[0024]

[Equation 2] However, i = N-1, N-2 ... 1. The matrix d is
This is called a backward substitution operation because it calculates the Nth element to the first element in reverse order.

The matrix calculation apparatus of the present invention can be widely used for calculation for obtaining a solution of simultaneous linear equations by such forward substitution and backward substitution.

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) Triangular decomposition n rows × n
A circuit configuration for obtaining a solution of simultaneous linear equations regarding a matrix of columns will be described.

When the lower triangular matrix of n rows × n columns is L and the known matrix of n rows × 1 column is r, the simultaneous linear equations are expressed by the equation (7). Lz = r ... (7) Here, Z is a matrix of n rows × 1 column which is a solution of simultaneous linear equations. In the simultaneous linear equations, since the matrix L is a lower triangular matrix, Z ₁ to Z _N can be sequentially obtained by the following equation. Part of the contents of this calculation is shown in FIG.

Process A in FIG. 1 shows the contents of the matrix operation including the lower triangular matrix, process B shows the simultaneous linear equations from the first to the fourth, and process C shows the first to the fourth. Four
The concrete calculation contents for obtaining the solution of the simultaneous linear equations up to the th are shown. The general formula for obtaining the solution of each linear equation is represented by the above formula (5).

As shown in the process A of FIG. 1, the lower triangular matrix is a matrix in which the upper right half is all "0" and the matrix elements are arranged in the lower left half. Here, the matrix elements located on the boundary line in contact with the "0" part in the upper right half are called "diagonal elements" (indicated by circles in FIG. 1), and the other matrix elements are It is called a "general element" (in FIG. 1, it is shown enclosed by a triangle). The definition of the diagonal element and the general element is the same for the upper triangular matrix.

As is clear from the operation contents for obtaining the solution Z ₄ of the _fourth linear equation shown in the process C of FIG.
The solution is calculated by summing the products of the solutions of the respective linear equations calculated in the past and the corresponding general elements of the lower triangular matrix, and subtracting the sum from the corresponding elements of the known matrix r. It consists of a process and a process of dividing the result by a diagonal element of the corresponding lower triangular matrix.

FIG. 2 is a diagram showing a concrete configuration of a matrix calculation device for executing such matrix calculation at high speed. Further, FIG. 3 is a timing diagram for explaining a characteristic operation of the matrix operation device of FIG.

The matrix operation device of FIG. 2 is a cyclic arithmetic processing circuit composed of hardware that sequentially obtains solutions of simultaneous linear equations by forward substitution or backward substitution, and obtains solutions of linear equations. Therefore, the circuit elements for performing multiplication, division, addition, and subtraction necessary for this are arranged along the operation procedure (operation flow), and the processing is performed in a pipeline while creating a reasonable data flow. To do.

The structure of the matrix calculation device of FIG. 2 can be roughly divided into two parts. That is, a hardware for performing a predetermined product-sum operation for all solutions obtained in the past, including the solution of the immediately preceding linear equation, which is necessary for obtaining the solution of the n-th (n is a natural number of 2 or more) linear equation. Sum-of-products operation unit (101, 102, 103, 105, 1) of wear configuration
06, 107, 108, 109, 110) and a value output from the product-sum operation unit, a linear operation unit (111) having a hardware configuration for performing a predetermined linear operation to obtain a solution of the n-th linear equation. , 112, 113, 114)
Can be divided into

In the matrix computing device, the product-sum computing unit computes the n-th linear equation during the period in which the linear computing unit computes the solution of the (n-1) th linear equation. Among the product-sum operation terms required to obtain the solution, the product-sum operation is performed in advance for a partial term that does not include the solution of the (n-1) th linear equation, and (n-1)
When the solution of the th linear equation is obtained, the product-sum operation is performed on the partial terms including the solution of the (n-1) th linear equation, and the multiplier of the multiplication unit 107 is used in time division. .

The specific structure will be described below. In the matrix operation device of FIG. 2, the register 101 is a register for accumulating the solution of the immediately preceding linear equation. The shift register 102 is a shift register that sequentially accumulates solutions of linear equations obtained in the past.

The reason why the register 101 and the shift register 2 are separated is that the solution of the immediately preceding linear equation is in the register 10.
Latched (set) to 1 and register 1
This is because it is considered that the data of 01 and the data of each tap of the shift register are shifted by one stage.

The timing at which the solution of the immediately preceding linear equation is latched (set) in the register 101 is determined by the register latch clock (RC) as shown in FIG.

The timing of shifting the data of the register 101 and the data of each tap of the shift register by one stage is controlled by the shift clock (SCL). The register latch clock (RC) and shift clock (SCL) are supplied to the register 101 via an OR gate (OR).

Here, it should be noted that the shift register 102 has a shape folded back on the way, and as a result, the delay elements at corresponding positions in the first half and the second half of the shift register 102 are located. The outputs of the (memory elements) form one set, and the signals of each set are provided to the switch SW1 provided in the switch unit 105.
To SW (N / 2).

The multiplication unit 107 adopts such a configuration.
This is because the number of multipliers (MUL (1) to MUL (n / 2)) included in is reduced in a time division manner, that is, the solution of the immediately previous linear equation is still set in the register 101. In the non-operating period, the data of the register 101 and the data of each tap of the shift register are shifted by one stage and the switches SW1 to SW (n
/ 2) is switched to the terminal b side, and the shift register 102
From the delay element (memory element) in the latter half of the above, only the solution already obtained is extracted and the operation is advanced in advance. This point will be specifically described later.

The values of the general elements of the lower triangular matrix are stored in the first memory unit 103 (having memories (1) to (n-1)). The value of the general element of the lower triangular matrix is determined by the multiplier (MUL (1) provided in the multiplication unit 107 via the plurality of switches (PW1 to PW (n / 2)) provided in the switch unit 106. ) ~ MUL (n /
The solution of the linear equation, which has been input to 2)) and has already been obtained, is multiplied by the general element of the lower triangular matrix.

Then, the adder 108 adds the output values from the multipliers, sends the result to the register 109 via the adder 110, and temporarily stores it there. Then, after the solution of the immediately preceding linear equation is latched in the register 101, each switch of the switch unit 105 is switched to the a terminal side, and a similar product-sum operation is executed. The product-sum operation result is added up with the result of the preceding process accumulated in the register 109 in the adder 110.

The second memory 111 stores the matrix elements of the known matrix r. The subtractor 112 performs an operation of subtracting the product-sum operation result from the elements of the known matrix r.
The result is further divided by the value of the diagonal element of the lower triangular matrix in the divider 114. Values of diagonal elements of the lower triangular matrix are stored in the third memory 113.

The solution of the linear equation obtained as a result of the division is stored in the fourth memory (memory for storing the solution) 11
Is stored in 5, and set in the register 101,
Hereinafter, the same process is repeated.

FIG. 3 is a timing chart for explaining the operation of the part of the matrix operation device of FIG. 2 which performs the sum of products operation (operation for taking the sum of the outputs of the multipliers).

Here, for the sake of convenience, eight linear simultaneous equations are used.
Suppose you want to solve. Time t0 to t3 is the first one
Formula solution Z₁Is the period for which
5, time t4 to t7, time t6 to t9, time t8 to t1
1, time t10 to t13, time t12 to time t15, hour
From time t14 to time t17, the solution z₂, Z₃，
z _Four, Z_Five, Z₆, Z₇, Z₈Is the period for which

The switches SW1 to S of the switch unit 105
W (n / 2) is alternately and periodically switched to the a terminal side and the b terminal side.

To obtain a certain z _i , the calculation is started after the switch is switched to the terminal b side. Note that this switching also applies to the switch unit 106. When switched to the a terminal side, the first half delay element (storage element) of the shift register 102 and data from the register 101 are taken out, and when switched to the b terminal side, the latter half delay element of the shift register 102. Data is extracted from the.

The shift clock (SCL) and the register latch clock (RC) are out of phase with each other, and the shift clock (SCL) precedes the phase. This means that the data is shifted and the state of the shift register is updated before the solution of the immediately preceding linear equation is obtained.

FIG. 4 schematically shows the operation for obtaining the solution z ₈ of the _eighth equation. Z as shown
_In order to obtain ₈ , it is necessary to add eight terms including the solution of the equation, but the operation cannot be executed unless the solution z ₇ of the immediately preceding equation is calculated.

Therefore, as shown in the upper part of FIG. 4, the terms to be subjected to the sum-of-products operation are roughly classified into a group A that does not include the solution of the immediately preceding equation and a group B that includes the solution of the immediately preceding equation. . And to find the solution z ₇ of the previous equation,
After the addition operation by the adder 110 is completed (that is,
The contents of the shift register are updated after the calculation in the product-sum calculation unit is completed and during the calculation by the subtractor 112 and the division by the divider 114). The solutions of z ₁ to z ₃ obtained in the past are taken out, and the product-sum calculation of group A is carried out in advance.

At the bottom of FIG. 3, the contents of the calculation executed in each period are described. At the beginning, since the data in the latter half of the shift register remains "0", even if the switch is switched to the b side to take out the data from the latter half and carry out the product-sum operation, the result is "0". It remains.

However, as the calculation progresses, the solution of the linear equation obtained in the past is shifted to the latter half of the shift register, and eventually the switch is switched to the b side (that is, the shift register). In the period when the output from the latter half of is selected, some of the product-sum operations required to solve the following linear equations are performed in advance, and the common multiplier is time-divided. The very efficient processing used will be performed.

The above is the outline of the characteristic portion of the arithmetic unit of FIG. Hereinafter, the matrix calculation device of FIG. 2 will be described in more detail.

In the following description, the register 101 is called the first register, the register 104 is called the second register, and the register 109 is called the third register. Further, the adder 108 is called a first adder, and the adder 110 is called a second adder. Also, the switch 105
Will be referred to as a first switch, and the switch 107 will be referred to as a second switch.

The matrix calculation device of FIG. 2 has a first register 10 for storing the calculation result (z _I ) found at the present time.
1 and the calculation result (z ₁ ~
z _{i -1} ) of the (N-2) stage shift register 1
02, the first memory 103 in which all general elements except the diagonal elements of the known lower triangular matrix (L) are stored, and 0 at all times
Is stored in the second register 104 and the first half of the first register 101 and the shift register 102 (N / 2
-1) are combined to form the first half and the latter half of the shift register (N
/ 2-1) The first switch unit 1 which controls the reading of either the first half or the second half with the second half as the second half.
05 and the first half (N / 2) of the first memory 103 are used as the first half, and the second half (N / 2−) of the first memory 103 is
1) The second switch 106 for controlling the reading of either the first half or the second half of the memory and the second register 104 as the latter half, and the output value of the first switch 105 and the second switch 106. N / 2 multipliers 107 for performing multiplication with the output value of the switch 106 of
A first adder 108 for adding all the operation results output from the N / 2 multipliers 107, and the first adder 108 when the operation result of the first adder 108 is obtained by reading the latter half part. Third register 109 for storing the result of the first adder 108 and the operation result of the first adder 108 when the result of the first adder 108 is obtained by reading the first half part From the second adder 110 for adding the value stored in the third register 109, the second memory 111 for storing the elements of the known matrix of N rows × 1 column, and the second memory 111 From the value read out, the second adder 1
The subtracter 112 for subtracting the operation result of 10, the third memory 113 for storing the diagonal elements of the known lower triangular matrix, and the output value from the subtractor 112 for the third memory 1
Divider 114 for dividing by the value read from 13
And a fourth memory 115 for storing the calculation result output from the divider 114. As described above, z ₁ to z _N are sequentially stored in the fourth memory.

Next, the circuit operation of FIG. 2 will be described.

At the start of calculation, the general elements of the known lower triangular matrix L are stored in the first memory 103, and all elements of the known matrix r of N rows × 1 column are stored in the second memory 111. The diagonal elements (L ₁₁ , L ₂₂ , ..., L _NN ) of the lower triangular matrix L are stored in the third memory 113, and 0 is set in the second register 104 and the third register 109.

The first memory 103 is composed of N-1 memories, and each memory has a lower triangular matrix L.
The general elements of are stored regularly.

The memory (1) has (0, L ₂₁ , L ₃₂ ,
L ₄₃ , ..., L _{N, N−1} ) are stored in the memory (2) as (0, 0,
L ₃₁ , L ₄₂ , L ₅₃ , ..., L _{N, N-2} ) are ... Memory (N-
2) has (0, 0, ..., 0, L _N-1 , ₁ , L _{N, 2} ), and memory (N-1) has (0, 0, ..., 0, L _{N, 1} ). Is stored. Each memory has N addresses.
These operate so that the memory address is incremented and sequentially read according to the timing at which the shift register 102 shifts.

When the calculation is started (when z _{1 is} calculated), the first
The register 101 and the shift register unit 102 of
In this state, the initial value 0 is stored.

First, the first switch section 105 controls so as to read the value from the latter half of the shift register 102,
The second switch 106 controls so as to read the value from the latter half of the first memory 103.

At this time, since all 0s are stored in the shift register 102, the operation results of the N / 2 multipliers 107 are all 0s. Therefore, the result of the first adder 108 is also 0, and 0 is stored in the third register 109.

Next, the first switch 105 is switched to control to read the value from the first half of the first register 101 and the shift register 102, and the value is input to the multiplier 107. At the same time, the first half of the first memory 103 and the second register 104 are controlled so as to be read, and the multiplier 1
Enter in 07. Since the multiplication results of the first half are all 0, the calculation result of the first adder 108 is also 0. The calculation result of the first adder 108 (sum of multiplication results of the first half) and the value stored in the third register 109 (sum of multiplication results of the second half) are input to the second adder 110.

The output of the second adder 110 is also 0. When the operation of the second adder is completed, the first element r ₁ of the known matrix r is read from the second memory 111, and the subtracter 112 subtracts the operation result of the second adder 110 from r ₁ .

Further, the third register 109 is initialized. Since the operation result of the second adder 110 is 0, the output of the subtractor 112 is r ₁ −0 = r ₁ . Subtractor 1
When the calculation of 12 is completed, the diagonal element L ₁₁ of the lower triangular matrix is read from the third memory 113, and the output value of the subtractor 112 is divided by L ₁₁ in the divider 114.

Since the output of the divider 114 is r ₁ / L ₁₁ , the solution z ₁ can be obtained at this point. The obtained solution z ₁ is the fourth
Of the first register 1 at the same time as being stored in the memory 115 of
It is stored in 01.

Next, the operation of obtaining the solution z ₂ will be described. In the calculation process of the solution z _{1, when} the calculation of the second adder 110 is completed, the value of the first register 101 is input to the shift register 102 to shift one stage.

In addition, (N-1) first memories 103
Increment the read address of. Here, the first switch 105 is switched to switch the shift register 102.
The value is controlled to be read from the latter half of the. Second at the same time
The switch 106 is switched to read the value from the latter half of the first memory 103.

The second half and the first of the shift register 102
The latter half of the memory is input to the multiplier 107 and multiplication is performed. Even at this point in time, the values in the shift register 102 are all 0, so the multiplication results are all 0.

The multiplication result is input to the first adder 108 and added. The result of the adder is also 0. The addition result is stored in the third register 109. If the solution z ₁ is not found at this point, the first switch 105 and the second switch 106 are not switched, and the calculation for finding the solution z ₂ enters a standby state.

When the solution z ₁ is obtained and stored in the first register 101, the first switch 105 is switched to control the multiplier 107 to read the value from the first half of the first register 101 and the shift register 102. input.

At the same time, the first half of the first memory 103 and the second register 104 are controlled to be read and input to the multiplier 107. The multiplier 107 multiplies the output of the first switch 105 and the output of the second switch 106.

Since the solution z ₁ is stored in the first register 101 and the read address of the first memory 103 is incremented, L ₂₁ is read from the memory (1). Therefore, the multiplier (MUL (1))
The calculation result of is z ₁ · L ₂₁ . Shift register 102
Since all 0s are stored in 0, the calculation result other than the multiplier MUL (1) is 0.

Therefore, the calculation result of the first adder 108 is z ₁ · L ₂₁ . The second adder 110 adds the value stored in the third register 109 and the calculation result of the first adder 108. Since 0 has been entered in the third register 109, the output of the second adder 110 becomes z ₁ .L ₂₁ .

When the operation of the second adder 110 is completed, the second
The read address of the memory 111 is incremented, the value r ₂ is read, and the value is input to the subtractor 112. The subtractor 112 subtracts the output value z ₁ · L ₂₁ of the second adder 110 from r ₂ read from the second memory 111.

Therefore, the calculation result of the subtracter 112 is (r ₂
-Z ₁ · L ₂₁ ). When the calculation of the subtractor 112 is completed, the read address of the third memory 113 is incremented to read the diagonal element L ₂₂ of the lower triangular matrix L and input to the divider 114. In the divider 114, the calculation result of the subtractor 112 (r ₂ −z ₁ · L ₂₁ ) is stored in the third memory 11
Divide by L ₂₂ read from 3.

The operation result of the divider 114 is (r ₂ −z ₁ ·
The L ₂₁₎ / L _22. From the above equation (5), z ₂ = (r ₂
-Z ₁ · L ₂₁ ) / L ₂₂ . That is, the output of the divider 114 is z ₂ and is input to the fourth memory 115 and the first register 101. Thereafter, z ₃ , ..., Z _N can be similarly obtained.

The effects of the arithmetic unit according to the present embodiment described above will be described.

Since the values are read from the first register 101 and the (N-2) th stage shift register 102 to perform multiplication, if there is one multiplier for each stage, parallel processing can be performed and the processing time can be shortened. When performing parallel processing at the same time, it is necessary to wait until the immediately preceding solution is stored in the first register 101.

Therefore, in the matrix operation device of the present invention, the second half of the shift register 102 in which the solutions already obtained are stored is calculated first, and the first half is calculated when the immediately preceding solution is obtained. Thus, the number of multipliers is reduced to half and the time division processing is performed.

From the above, by using the matrix operation device of the present invention, the forward substitution operation process can be performed with a high-speed and small-scale circuit configuration.

(Embodiment 2) In the above-mentioned embodiment,
Although the calculation using the lower triangular matrix has been described, this embodiment will explain a case where the calculation using the upper triangular matrix is performed.

When the upper triangular matrix of N rows × N columns is L and the known matrix of n rows × 1 column is z, the simultaneous linear equations are
It is expressed by equation (8). Ld = z ... (8) The solution d is a matrix with n rows and 1 column. The upper triangular matrix is
For example, as shown in FIG. 5, the matrix has all 0s in the lower left half and matrix elements in the upper right half.

Since the matrix L is an upper triangular matrix, simultaneous linear equations can be obtained in reverse order from d _N to d ₁ . The arithmetic expression in this case is represented by the above expression (6).

Such calculation is executed by the matrix calculation device of FIG.

As described above, the matrix calculation device of FIG.
Calculation result (d _I) To store the first
Register 101 and the operation result obtained up to the present time
Fruit (d_N~ D_{i + 1}) Is stored in the (N-2) th stage shift register
The star 102 and the diagonal elements of the known upper triangular matrix (L)
First memory 103 for storing all general elements except
And a second register 104 that always stores 0,
First half of the first register 101 and the shift register 102
(N / 2-1) are combined to form the first half of the shift register.
There are the first half of these as the latter half of the latter half (N / 2-1).
Or the first switch that controls the readout of either the latter half.
Switch 105 and the first half (N / 2) of the first memory 103
Memory of the first half of the first memory 103 (N
/ 2-1) memory and second register 104
Read either the first half or the second half as a half.
The second switch 106 for controlling the protrusion and the first switch
Output value of the switch 105 and the output value of the second switch 106
N / 2 multipliers 107 for multiplying
Add all operation results output from the multipliers 107
First adder 108 and the operation result of the first adder 108
Is obtained by reading the latter half of the first half, the first adder 10
A third register 109 for storing the result of 8;
The result of the first adder 108 is obtained by reading the first half
If the calculation result of the first adder 108 and the third register
The second for adding the value stored in register 109
Stores adder 110 and elements of a known matrix of N rows x 1 column
Read from the second memory 111 and the second memory 111
Subtract the operation result of the second adder 110 from the output value
Subtractor 112 and the diagonal elements of the known upper triangular matrix
A third memory 113 for storing the
Output value from the third memory 113 is read.
And a divider 114 for dividing by a value
Fourth memory 115 for storing the output operation result
It consists of and. From the above, d is stored in the fourth memory.
_NTo d₁Are sequentially stored until.

Next, the circuit operation will be described.

At the start of the calculation, the general elements of the known upper triangular matrix L are stored in the first memory 103, and the known matrix z (z ₁ , z ₂ , ... z
_N ) are stored, the diagonal elements (L ₁₁ , L ₂₂ , ..., L _NN ) of the upper triangular matrix L are stored in the third memory 113, and the second register 104 and the third register are stored. 109
Is set to 0. The first memory 103 is composed of N-1 memories, and the general elements of the upper triangular matrix L are regularly stored in the respective memories. The memory (1) in the first memory 103 has (L ₁₂ , L ₂₃ , L
₃₄ , ..., L _{N-1, N} , 0) is stored in the memory (2) as (L ₁₃ ,
L ₂₄ , L ₃₅ , ..., L _{N-2, N} , 0, 0) are ... Memory (N
-2) stores (L _{1, N-1} , L _{2, N} , 0, ..., 0), and memory (N-1) stores (L _{1, N} , 0, ..., 0). .
Each memory has N addresses. These operate such that the memory address is decremented and read sequentially according to the shift timing of the shift register 102.

When the calculation is started (d _{N is} calculated), the first
The initial value 0 is stored in the register 101 and the shift register 102.

First, the first switch 105 controls so that the value is read out from the latter half of the shift register 102,
The second switch 106 controls so as to read the value from the latter half of the memory 103. At this time, shift register 1
Since all 0s are stored in 02, the operation results of the N / 2 multipliers 107 are all 0s.

Therefore, the result of the first adder 108 also becomes 0, and 0 is stored in the third register 109.

Next, the first switch 105 is switched to control to read the value from the first half of the first register 101 and the shift register 102, and the value is input to the multiplier 107. At the same time, the first half of the first memory 103 and the second register 104 are controlled to be read so that the multiplier 1
Enter in 07.

Since the multiplication results of the first half are all 0,
The calculation result of the first adder 108 is also 0. The calculation result of the first adder 108 (the sum of the multiplication results of the first half) and the third
The value stored in the register 109 (total sum of multiplication results in the latter half) is input to the second adder 110. The output of the second adder 110 is also 0. When the operation of the second adder is completed, the Nth element z _N of the known matrix z is read from the second memory 111, and the subtracter 112 subtracts the operation result of the second adder 110 from z _N. Also, the third register 1
09 is initialized.

Since the operation result of the second adder 110 is 0, the output of the subtractor 112 is z _N = 0 = z _N. When the operation of the subtractor 112 is completed, the diagonal element L _NN of the upper triangular matrix is read from the third memory 113, and the divider 114 divides the output value of the subtractor 112 by L _NN . Divider 1
Since the output of 14 is z _N / L _NN , the solution d _N can be obtained at this point. The obtained solution d _N is stored in the fourth memory 115 and simultaneously in the first register 101.

Next, the operation of obtaining the solution d _N-1 will be described. In the calculation process of the solution d _{N, when} the calculation of the second adder 110 is completed, the value of the first register 101 is input to the shift register 102 to perform one-stage shift.

In addition, (N-1) first memories 103
Decrement the read address of. Where the first
The switch 105 is switched to read the value from the latter half of the shift register 102.

At the same time, the second switch 106 is switched to control to read the value from the latter half of the first memory 103. The latter half of the shift register 102 and the latter half of the first memory are input to the multiplier 107 and multiplication is performed. Even at this point in time, the values in the shift register 102 are all 0, so the multiplication results are all 0. The multiplication result is input to the first adder 108 and added. The result of the adder is also 0. The addition result is stored in the third register 109. If the solution d _N is not found at this point, the first switch 105 and the second switch 106 are not switched, and the calculation for finding the solution d _{N- 1} enters the standby state. When the solution d _N is obtained and stored in the first register 101, the first switch 105 is switched to change the first register 1
01 and the shift register 102 are controlled to read values from the first half of the shift register 102 and input to the multiplier 107. At the same time, the first half of the first memory 103 and the second register 104 are controlled to be read and input to the multiplier 107. The multiplier 107 multiplies the output of the first switch 105 and the output of the second switch 106. Since the solution d _N is stored in the first register 101 and the read address of the first memory 103 is decremented, L _{N-1, N} is read from the memory (1).
Therefore, the calculation result of the multiplier (MUL1) of the multiplication unit 107 is d _N · L _{N-1, N.} Since all 0s are stored in the shift register 102, the operation result other than the multiplier (MUL1) is 0. Therefore, the operation result of the first adder 108 is d _N · L _{N−1 , N.} The value stored in the third register 109 by the second adder 110 and the first adder 10
The calculation result of 8 is added. Since 0 has been entered in the third register 109, the output of the second adder 110 is d _N
L _{N-1, N.}

When the operation of the second adder 110 is completed, the second
The read address of the memory 111 is decremented to read the value z _N−1 and input to the subtractor 112. The subtracter 112 reads z _N-1 read from the second memory 111.
Is subtracted from the output value d _N · L _{N-1, N} of the second adder 110. Therefore, the calculation result of the subtractor 112 is (z _N-1 −d _N ·
L _{N-1, N} ). When the subtracter 112 has finished the operation, the third
The read address of the memory 113 is decremented and the diagonal elements L _{N-1, N-1} of the upper triangular matrix L are read and input to the divider 114.

[0102] Divider At 114, a computation result of the subtracter _{112 (z N-1 -d N} · L N-1, N) of the third memory 11
Divide by L _{N-1, N-1} read from 3. Divider 114
The calculation result of is (z _N-1 −d _N · L _{N-1, N} ) / L _{N-1, N-1} . From the formula (6), d _N-1 = (z _N-1 −d _N · L _{N-1, N} )
/ L _{N-1, N-1} . That is, the output of the divider 114 is d
_N−1, which is input to the fourth memory 115 and the first register 101. Thereafter, d _N-2 , ..., D ₁ can be similarly obtained.

The effects of this embodiment will be described.

Since the values are read from the first register 101 and the (N-2) th stage shift register 102 and the multiplication is performed, if there is one multiplier for each stage, parallel processing can be performed and the processing time can be shortened. When performing parallel processing at the same time, it is necessary to wait until the immediately preceding solution is stored in the first register 101.

Therefore, in the matrix operation device of the present invention, the second half of the shift register 102 in which the solutions already obtained are stored is calculated first, and the first half is calculated when the immediately preceding solution is obtained. Thus, the number of multipliers is reduced to half and the time division processing is performed.

As described above, by using the matrix calculation device of the present invention, the backward substitution calculation process can be performed with a high speed and small scale circuit configuration.

(Embodiment 3) The matrix calculation device of the present invention is
It can also be applied to joint detection demodulation, which is a demodulation method of signals received by wireless communication.

Joint detection demodulation (hereinafter J
D demodulation) is a demodulation method suitable for TDD mode communication of W-CDMA, and is different from the method of multiplying a spreading code and detecting autocorrelation to demodulate, and is different from that of a plurality of users superimposed on a received signal. This is a demodulation method that positively utilizes the principle of interference cancellation, in which only the signal of each user is extracted by detecting the cross-correlation of each signal and subtracting the components other than its own signal. Since the interference component that cannot be removed can be removed accurately, more accurate demodulation can be performed. Also,
In JD demodulation, interference can be eliminated even for cross-correlation due to delayed waves.

FIG. 7 shows a propagation model of a signal for JD demodulation.

D (1) to d (k) represent the signals transmitted by the k users, respectively, which are the targets of demodulation. c (1) to c (k) are spreading codes, and h
(1) to h (k) are estimated propagation characteristics (delay profile: estimated impulse response of the line).

B (1) to b (k) are vectors obtained by the convolution operation of the spreading code and the propagation characteristic. The noise n added to this is the received signal e, which is demodulated by the JD demodulation unit 203, and the transmitted signals d (1) to d (k) of each user are distinguished and demodulated.

FIG. 8 is a matrix display of the propagation model of FIG.

From FIG. 8, it is the JD demodulation that calculates the matrix d from the equation Ad + n = e. Multiplying both sides by the conjugate transposed matrix A ^H of the matrix A from the left side, A ^H Ad +
It can be transformed into A ^H n = A ^H e. If the noise n is negligibly small, or is represented by A ^H n = σ ² Id (I is an identity matrix of n rows and n columns), the equation is expressed as Fd = r.

That is, assuming that A ^H n = σ ² Id (I is a unit matrix of N rows and N columns), it can be transformed into (A ^H A + σ ² I) d = A ^H e. Here, A ^H e represents the symbol data after RAKE combining, denoted as r. Also, A ^H A
Let + σ ² I = F. Then, it can be expressed as Fd = r.

Here, the matrix F is a cross-correlation matrix, and when the noise n is small enough to be ignored, the vector B1 (= B2 = Bn) obtained by convolving the spreading code and the estimated impulse response of the line is used. It is a matrix generated by multiplying the matrix A generated by regularly arranging it and its conjugate transposed matrix A ^H, and is a symmetric matrix.

In order to obtain the matrix d from such an equation, the inverse matrix of the matrix F may be generated and multiplied.
In reality, the calculation of the inverse matrix is not easy. Therefore, the JD demodulation unit of the present embodiment obtains the elements of the matrix d by performing Cholesky decomposition of the matrix F and solving the simultaneous linear equations.

FIG. 6A shows a CDMA including a JD demodulation section.
It is a block diagram which shows the structure of a receiver, (b) is a figure which shows the format of transmission data.

The signal received by antenna 2 is amplified by radio receiving section 10 and channel estimating section 201 and despreading section 20 are amplified.
Input to 7.

Channel estimation section 201 estimates the channel of each user's signal from the impulse response of the known signal (midamble code) contained in the received signal.

The midamble code is. As shown in FIG. 6 (b), it is inserted in the center of one slot,
This is a known code for line estimation.

Channel estimating section 201 has a midamble correlation processing section 20, a midamble code generating section 24, and a path selecting section 22.

The signal passed through the radio receiving section 10 is despreading section 20.
Despread at 7. The channel estimation value obtained by the channel estimation section 201 is used as the RAKE combining section 202 and the JD demodulation section 20.
Input to 3. Regarding the symbol data after despreading,
Phase compensation is performed based on the channel estimation value, RAKE combining section 202 performs RAKE combining, and RAKE combining result r is input to JD demodulating section 203.

The JD demodulation section 203 has a spreading code generating section 3
A cross-correlation matrix (F) generation unit 204 that obtains a cross-correlation matrix (F) from the spread code given from 0 and the impulse response of the estimated channel, and a cross-correlation matrix or a modified Cholesky decomposition to obtain a lower triangle. A Cholesky decomposition unit 205 in the form of a product of a matrix and an upper triangular matrix,
It has a simultaneous equation calculation unit 206 for calculating a solution for simultaneous linear equations expressed in a format including a lower triangular matrix or an upper triangular matrix by using forward substitution or backward substitution.
The simultaneous equation calculation unit 206 includes the matrix calculation device of FIG.

FIG. 9 shows the cross-correlation matrix (F) generator 204.
3 is a diagram for explaining the function of FIG. In the convolution operation processing X1 shown on the upper side of FIG. 9, the spreading code (C _{1 to} C _Q ) output from the portion 900 that stores the spreading code.
And the parameter (h _{1 to} h _w ) of the line estimation value output from the portion 902 storing the line estimation value, the adder 90
3 (903a to 903c, etc.) and the adder 904 are used for convolution to obtain vectors b _{1 to} b _{Q + W-1} .

Then, in process Y1 shown on the lower side of FIG. 9, the vector b is regularly arranged to generate the matrix A. Further, in the process Y2, the matrix A and the matrix A ^H that is the conjugate transposed matrix of the matrix A are multiplied to obtain the matrix F (= A ^H
A) is generated.

Here, assuming that the estimated signal of the transmission signal obtained as a result of JD demodulation is d, the following expression (9) is established. Fd = r (9) This equation is solved for d by the simultaneous equation calculation unit 206.

Since the matrix F is a symmetric matrix, Cholesky factorization (including modified Cholesky factorization) can be performed, and the matrix F can be factored into F = LL ^H using the lower triangular matrix L. However, L ^H is a conjugate transposed matrix of L. The Cholesky decomposition section 205 performs Cholesky decomposition (or modified Cholesky decomposition).

From the above, LL ^H d = r and L ^H d = z
First, the simultaneous equations regarding the lower triangular matrix are solved for z with Lz = r. Now that the matrix z is known, a system of equations for the upper triangular matrix of L ^H d = z can be solved for d.

By solving these simultaneous linear equations for the lower triangular matrix and simultaneous linear equations for the upper triangular matrix using the matrix operation device of the present invention shown in FIG. 2, the solution can be obtained very quickly. .

(Embodiment 4) The matrix operation device of the present invention can also be used in a communication device in which an adaptive array based on the least square error method (MMSE) is mounted.

FIG. 10 shows a communication device in which an adaptive array based on the least square error method (MMSE) is mounted.

As an example, a case where there are three antennas will be described.

Received signals are input from the antennas 301, 302 and 303. The weight generator 30 is provided so that the demodulator 304 of the received signal can perform optimum demodulation.
Optimal weighting is performed by multiplying the signal received from each antenna by the weight generated in 5.

Let R be the autocorrelation matrix of the received signals input from antenna 301, antenna 302, and antenna 303.
When the cross-correlation matrix between the received signal and the known signal is P, the weight w can be calculated from the equation (10). Rw = P
(10) Here, since R is a symmetric matrix, Cholesky decomposition can be performed. Therefore, simultaneous linear equations regarding the upper triangular matrix and simultaneous linear equations regarding the lower triangular matrix are solved.

Therefore, by using the matrix operation device of the present invention, the optimum weight can be obtained at high speed.

(Embodiment 5) The matrix operation device of the present invention can be used also in a communication device in which an adaptive equalizer is mounted. The adaptive equalizer is a filter that precisely controls the time response of the transmission line to smooth the amplitude and delay characteristics of the transmission line. FIG. 1 shows a communication device in which an adaptive equalizer is mounted.
Shown in 1.

The received signal is a transversal filter (F
(IR) 401 and weight calculation section 402.

The weight calculator 402 calculates the optimum tap coefficient of the transversal filter 401. The number of taps of the transversal filter 401 is M.
The optimum tap coefficient is calculated as follows. The optimum tap coefficient is M row × 1 column matrix w, the received signal autocorrelation matrix is R (M row × M column matrix), and the cross-correlation matrix between the received signal and the desired response corresponding to the known signal. To P
(M rows × 1 column matrix), the following expression (11) is established. RW = p (11) Here, assuming that the received signal r (i) at the time point i, the autocorrelation matrix of the received signal is given as follows.

[0138]

[Equation 3] Further, the cross-correlation matrix P between the desired response d (n) and the received signal is given as follows.

[0139]

[Equation 4]

The equation (11) is solved for w, the optimum tap coefficient is obtained, and the optimum filter is generated. Where R
Since is a symmetric matrix, Cholesky decomposition and modified Cholesky decomposition can be performed. By using the matrix calculator of the present invention, the subsequent forward substitution and backward substitution calculations can be performed at high speed with a small circuit configuration.

(Embodiment 6) The matrix calculation device of the present invention is a type of arrival estimation algorithm, Capo, in a communication device in which an adaptive array is mounted.
It is also effective for the n-method calculation.

When the correlation matrix of the received signal is Rxx and the response vector of the array is a (θ), the Capon method angle spectrum P _cp (θ) can be obtained by the equation (12).

[0143]

[Equation 5] Here, since the correlation matrix R _xx of the received signal is a symmetric matrix, Cholesky decomposition can be performed. If the lower triangular matrix is L, then R
_It can be decomposed as _xx = LL ^H. Therefore, R _xx ^-1 = (LL ^H ) ^-1
Can be transformed. When the inverse matrix of LL ^H is obtained, it can be easily obtained by using the equation (13). When the inverse matrix of LL ^H is x and the identity matrix is E, it can be expressed by equation (13). LL ^H x = E (13) By using the matrix calculator of the present invention to solve Expression 11 for x, a small-scale circuit can perform high-speed calculations. As shown above, the matrix calculator of the present invention can obtain an inverse matrix at high speed.

[0144]

As described above, according to the present invention, a super-high-speed matrix operation can be executed by a cyclic arithmetic processing circuit composed of hardware. As a result, for example, a speedup 10 times faster than the conventional one is achieved.

Further, according to the present invention, by using the multipliers in a time division manner, it is possible to effectively and effectively reduce the number of the multipliers, thereby promoting miniaturization of the device and reduction of power consumption.
That is, when the solution of the previous linear equation is still being calculated,
The product-sum calculation of the solution calculation of the following linear equation is started. However, the sum-of-products calculation cannot perform all the sum-of-products calculation because it includes the element immediately before being calculated at this point. So the first half and the second half (the one that includes the previous element)
Therefore, a plurality of multipliers are arranged so that the multiplication can be performed all at once, and the multiplication is started from the latter half. After the previous element is found, the first half multiplication is started. For example, half the number of multipliers is sufficient as compared with the case where the immediately preceding element is obtained and multiplication is performed all at once, and the product sum operation is performed. The processing time is almost unchanged.

As described above, according to the present invention, a high-speed matrix operation can be efficiently realized with a small-sized and low power consumption hardware. The matrix calculation device of the present invention is
It is suitable for I-mode and is therefore applicable to mobile communication devices such as mobile phones.

[Brief description of drawings]

FIG. 1 is a diagram showing the processing contents of a matrix operation including a lower triangular matrix.

FIG. 2 is a circuit diagram showing a configuration of an example of a matrix calculation device of the present invention.

FIG. 3 is a timing diagram for explaining a characteristic operation of the matrix operation device of FIG.

FIG. 4 is a diagram for explaining an example of processing contents when a solution of a linear equation is obtained by the matrix operation device of FIG.

FIG. 5 is a diagram showing the processing contents of a matrix operation including an upper triangular matrix.

FIG. 6A is a block diagram showing a configuration of a CDMA receiving device including a JD demodulation unit, and FIG. 6B is a diagram showing a format of transmission data.

FIG. 7 is a diagram showing a propagation model of a multi-user transmission signal.

8 is a diagram showing the propagation model of FIG. 7 in a matrix format.

FIG. 9 is a diagram for explaining generation of a cross correlation matrix (F).

FIG. 10 is a diagram showing the configuration of an adaptive array device to which the matrix calculation device of the present invention is applied.

FIG. 11 is a diagram showing the configuration of an adaptive equalizer to which the matrix calculation device of the present invention is applied.

FIG. 12 is a diagram for explaining a matrix calculation method using a conventional multiprocessor.

[Explanation of symbols]

101, 104, 109 registers 102 shift register 103,111,113,115 memory 105,106 switch part 108,110 adder 112 subtractor 114 divider 206 matrix computing device

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B056 AA05 BB01 BB31 BB71                 5J021 AA05 AA09 CA06 DB02 DB03                       EA04 FA13 FA14 FA15 FA16                       FA17 FA20 FA26 FA29 FA30                       FA32 GA02 HA04 HA05 JA10                 5K046 AA05 BA01 BA07 EE05 EE06                       EE32 EE47 EF15                 5K059 AA08 AA12 CC01 CC04 DD31

Claims (9)

[Claims] 1. When a known lower triangular matrix is "L" and a known upper triangular matrix is "U", L (or U) .X = Y
A matrix operation device for calculating a solution of a simultaneous linear equation represented by (X is a matrix to be obtained and Y is a known matrix) by using forward substitution or backward substitution to obtain values of all the elements of the matrix X to be obtained. , N-th (n is a natural number greater than or equal to 2) hardware required to find the solution of the linear equation immediately before, including all solutions obtained in the past, including the solution of the previous linear equation And a linear operation unit having a hardware configuration for performing a predetermined linear operation on a value output from the product-sum operation unit to obtain a solution of the n-th linear equation, During the period in which the operation for obtaining the solution of the (n-1) th linear equation is performed in the linear operation unit, the product-sum operation required for obtaining the solution of the nth linear equation in the product-sum operation unit (N-1) of the item Matrix operation and wherein the preceding practiced product-sum operation for the partial terms the solution does not contain a linear equation of. 2. The matrix operation device according to claim 1, wherein the multiplier forming the product-sum operation unit is used in a time division manner. 3. When a known lower triangular matrix is "L" and a known upper triangular matrix is "U", L (or U) .X = Y
A matrix operation device for calculating a solution of a simultaneous linear equation represented by (X is a matrix to be obtained and Y is a known matrix) by using forward substitution or backward substitution to obtain values of all the elements of the matrix X to be obtained. , A first register for temporarily accumulating the solution of the immediately preceding linear equation necessary for finding the solution of the n-th (n is a natural number of 2 or more) linear equation, and the solution of the n-th linear equation A shift register having a configuration that temporarily accumulates each solution of a linear equation prior to the immediately preceding linear equation necessary for obtaining, and is divided into a first half portion and a second half portion by folding back in the middle. Of the folded back shift registers, the taps of the first half and the second half of the corresponding shifts are set as a set, or the register and the second half of the shift register are paired. And the position of the tap as one set, in each set, for switching whether to output either,
A plurality of switches provided for each set, and a general element of the lower triangular matrix L or the upper triangular matrix U,
As a coefficient for multiplying each of the values output from the plurality of switches, a coefficient generator that is generated in a predetermined order, a value that is output from each of the plurality of switches, and a coefficient that is generated from the coefficient generator A plurality of multipliers for multiplying the coefficient corresponding to each switch, an adder for adding the values output from each of the plurality of multipliers, and the n-th output from this adder. The value forming a part of the product-sum operation result required to obtain the solution of the linear equation is temporarily stored, and the stored value is stored when the next addition process is performed in the adder. A second register to be returned to the adder, and a necessary linear operation are performed on a value output from the adder, the value indicating a complete product-sum operation result necessary for obtaining a solution of the n-th linear equation. , The n-th primary A linear operation circuit for calculating the solution of the equation, and returning the solution of the obtained n-th linear equation to the first register, and the solution of the n-th linear equation to the first register. Shows a complete sum of products operation result required to shift the first register and the shift register by one stage and obtain the solution of the nth linear equation from the adder before being set. After the value is output and during the period when the operation is performed in the linear operation circuit, the plurality of switches are switched so that the value of the tap in the latter half portion of the shift register is output,
A part of the multiply-accumulate operation necessary for obtaining the solution of the next (n + 1) th linear equation is executed in advance, and then the obtained solution is returned to the first register to continue the operation. A matrix calculation device characterized by specifying all the elements of a matrix X to be obtained. 4. The coefficient generator outputs the value of a general element of a lower triangular matrix or an upper triangular matrix as a coefficient, and the linear arithmetic circuit outputs the lower triangular matrix or the upper triangular matrix. A matrix operation device comprising a circuit for performing a division operation using a diagonal element of the above as a divisor or a multiplication operation equivalent to this division operation. 5. A matrix in which a convolution of a spreading code and an estimated impulse response of the line is regularly arranged,
A cross-correlation matrix generator that multiplies the conjugate transposed matrix of the matrix to generate a cross-correlation matrix; and a cross-correlation matrix or a modified Cholesky decomposition of the cross-correlation matrix to form a product of a lower triangular matrix and an upper triangular matrix. Cholesky factorization section to be, and for a simultaneous linear equation represented in a format including the lower triangular matrix or the upper triangular matrix, the operation of calculating a solution using forward substitution or backward substitution, 4. A joint detection demodulation device, comprising: a simultaneous equation calculation unit that uses the matrix calculation device according to any one of items 4 to 4; 6. An adaptive array device, characterized in that a weight for multiplying a received signal of each antenna in the adaptive array is obtained by using the matrix operation device according to any one of claims 1 to 4. 7. The tap coefficient of the transversal filter in an adaptive equalizer including a traversal filter is obtained by using the matrix operation device according to claim 1. Adaptive equalizer. 8. An inverse matrix calculation device, wherein the matrix calculation device according to any one of claims 1 to 4 is used to perform an inverse matrix calculation using Cholesky decomposition. 9. The joint detection demodulator according to claim 5, the adaptive array device according to claim 6,
A wireless communication device equipped with either the adaptive equalizer according to claim 7 or the inverse matrix operation device according to claim 8.