CN1665009A - Semiconductor wafer device having multilayer wiring structure and packaging method thereof - Google Patents
Semiconductor wafer device having multilayer wiring structure and packaging method thereof Download PDFInfo
- Publication number
- CN1665009A CN1665009A CN2004100074834A CN200410007483A CN1665009A CN 1665009 A CN1665009 A CN 1665009A CN 2004100074834 A CN2004100074834 A CN 2004100074834A CN 200410007483 A CN200410007483 A CN 200410007483A CN 1665009 A CN1665009 A CN 1665009A
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- electric conductor
- insulating barrier
- wiring structure
- semiconductor chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The invention discloses a semiconductor wafer device with a multilayer wiring structure and its packaging method, and the method includes the steps as follows: providing a semiconductor wafer, forming a first insulating layer on the pad installation surface of the wafer, where the first insulating layer is provided with pad exposing through hole; forming a first conductor on the pad, where the first conductor is provided with a first end connected with the pad and a second end extending upwards from the pad onto the first insulating layer; forming a second insulating layer on the first insulating layer, where the second insulating layer is provided with a through hole exposing the second end of the first conductor; forming a second conductor on the second end of the first conductor; forming a third insulating layer on the second insulating layer and forming a conductive ball on the second conductor. The invention can make the pad easy to connect with external circuit and then raise production efficiency and product yield.
Description
[technical field]
The invention relates to a kind of semiconductor chip device and method for packing thereof, particularly relevant for a kind of semiconductor chip device and method for packing thereof with Miltilayer wiring structure.
[background technology]
Sustainable development along with semi-conductor industry, the surface area and the weld pad on the wafer surface of semiconductor wafer become more and more littler, and the distance between weld pad also can be dwindled because of the weld pad number more and more increases more and more, so that it is very difficult to become when being electrically connected with external circuit, and then influence production efficiency and acceptance rate, even influence the development that semi-conductor industry continues.
[summary of the invention]
In view of this, the purpose of this invention is to provide a kind of semiconductor chip device and method for packing thereof with Miltilayer wiring structure, make weld pad be easy to be electrically connected under can be at the distance between the chip bonding pads more and more littler situation, and then enhance productivity and acceptance rate with external circuit.
According to a kind of method for packing of the present invention, it is characterized in that: comprise following step with semiconductor chip device of Miltilayer wiring structure:
(1) provide semiconductor wafer, this semiconductor wafer has a pad installation surface and several and is installed on weld pad on this pad installation surface;
(2) form one first insulating barrier on the pad installation surface of this wafer, this first insulating barrier is that the weld pad corresponding to this wafer is formed with the through hole that several are used to expose corresponding pad;
(3) form one first electric conductor at least one described weld pad, this first electric conductor has a first end that is electrically connected with this weld pad and and extends upwardly to the second end on the top surface of this first insulating barrier from this weld pad;
(4) form one second insulating barrier on this first insulating barrier, this second insulating barrier is formed with the through hole that several are used to expose the second end of the first corresponding electric conductor corresponding to the second end of this first electric conductor;
(5) on the second end of each first electric conductor, form another electric conductor;
(6) form one the 3rd insulating barrier on this second insulating barrier, the 3rd insulating barrier forms the through hole that several are used to expose another corresponding electric conductor corresponding to described another electric conductor;
(7) on each described another electric conductor, form a conductor ball.
Preferably, in the step (3) that forms first electric conductor before, more comprise a step that forms a metallic conduction piece on each weld pad of wafer, the first end of each this first electric conductor is to be electrically connected with corresponding metallic conduction piece.
Preferably, in the step (3) that forms first electric conductor, more comprise the step that forms one second electric conductor at least one weld pad in this weld pad, this second electric conductor be with corresponding pad on the metallic conduction piece be electrically connected, and, in the step (4) that forms this second insulating barrier, this second insulating barrier is to be formed with the through hole that several are used to expose the second corresponding electric conductor corresponding to this second electric conductor.
Preferably, in the step (5) that forms another electric conductor, this another electric conductor is the 3rd electric conductor, and form in the step (5) of another electric conductor at this, more comprise a step that forms one the 4th electric conductor on each second electric conductor, the 4th electric conductor has a first end that is electrically connected with corresponding second electric conductor and and extends up to the second end on the top surface of this second insulating barrier from this second corresponding electric conductor.
Preferably, in forming the step (6) of the 3rd insulating barrier, the 3rd insulating barrier more forms the through hole that several are used to expose the second end of the 4th corresponding electric conductor corresponding to the second end of the 4th electric conductor.
Preferably, in the step (7) that forms conductor ball, more comprise a step that on the second end of each the 4th electric conductor, forms a conductor ball.
Preferably, in the step (4) that forms this second insulating barrier before, more comprise a step that the second end of this first electric conductor is polished by milled processed.
Preferably, in the step (4) that forms this second insulating barrier before, more comprise a step that forms a conductive layer in each on this first electric conductor.
Preferably, in the step that forms described conductive layer, each this conductive layer is to be made of a nickel coating and a Gold plated Layer.
Preferably, in the step (4) that forms this second insulating barrier before, more comprise following step:
By milled processed the second end of this first electric conductor is polished; And
Form a conductive layer on this first electric conductor in each.
Preferably, in the step that forms this conductive layer, each this conductive layer is to be made of a nickel coating and a Gold plated Layer.
Preferably, in the step (6) that forms the 3rd insulating barrier before, more comprise a step that the second end of the 3rd electric conductor and the 4th electric conductor is polished by milled processed.
Preferably, after the step that the second end of the 3rd electric conductor and the 4th electric conductor is polished, more comprise a step that on the second end of each the 3rd electric conductor and each the 4th electric conductor, forms a metal contiguous block.
According to a kind of semiconductor chip device with Miltilayer wiring structure of the present invention, it is characterized in that: comprise: semiconductor wafer, this semiconductor wafer have a pad installation surface and several and are installed on weld pad on this pad installation surface;
One is formed at first insulating barrier on the pad installation surface of this wafer, and this first insulating barrier is formed with the through hole that several are used to expose corresponding pad corresponding to the weld pad of this wafer;
First electric conductor that forms at least one this weld pad, this first electric conductor have a first end that is electrically connected with corresponding pad and and extend upwardly to the second end on the top surface of this first insulating barrier from this corresponding pad;
One is formed at second insulating barrier on this first insulating barrier, and this second insulating barrier is formed with the through hole that several are used to expose the second end of the first corresponding electric conductor corresponding to the second end of this first electric conductor;
Another electric conductor of at least one that forms on the first end of at least one first electric conductor in this;
One is formed at the 3rd insulating barrier on this second insulating barrier, and the 3rd insulating barrier is formed with the through hole that several are used to expose another corresponding electric conductor corresponding to these another electric conductors; And
One is formed at the conductor ball on this at least one another electric conductor.
Preferably, more comprise a metallic conduction piece on each weld pad that is formed at wafer, the first end of each this first electric conductor is to be electrically connected with corresponding metallic conduction piece.
Preferably, more comprise at least one and be formed at second electric conductor on another weld pad in the described weld pad, this second electric conductor be with corresponding pad on the metallic conduction piece be electrically connected, this second insulating barrier more is formed with the through hole that several are used to expose the second corresponding electric conductor corresponding to this second electric conductor.
Preferably, this another electric conductor is the 3rd electric conductor, more be formed with the 4th electric conductor on each second electric conductor, the 4th electric conductor has a first end that is electrically connected with corresponding second electric conductor and and extends up to the second end on the top surface of this second insulating barrier from this second corresponding electric conductor.
Preferably, the 3rd insulating barrier forms the through hole that several are used to expose the second end of the 4th corresponding electric conductor corresponding to the second end of the 4th electric conductor.
Preferably, on the second end of each the 4th electric conductor, be formed with a conductor ball.
Preferably, the second end of this first electric conductor is polished by milled processed.
Preferably, more comprise the conductive layer that is formed on each this first electric conductor.
Preferably, each this conductive layer is to be made of a nickel coating and a Gold plated Layer.
Preferably, the second end of this first electric conductor is polished by milled processed, and forms a conductive layer on this first electric conductor in each.
Preferably, each this conductive layer is to be made of a nickel coating and a Gold plated Layer.
Preferably, the second end of the 3rd electric conductor and the 4th electric conductor is polished by milled processed.
Preferably, more comprise metal contiguous block on the second end that is formed at each the 3rd electric conductor and each the 4th electric conductor.
[description of drawings]
Fig. 1-2 is the semiconductor chip device method for packing with Miltilayer wiring structure of describing preferred embodiment of the present invention forms first insulating barrier on the pad installation surface of wafer a flow process schematic sectional view.
Fig. 3 is the flow process schematic sectional view of semiconductor chip device method for packing of the present invention in the subsequent step of Fig. 2.
Fig. 4 is the vertical view of Fig. 3.
Fig. 5-9 is for describing the flow process schematic sectional view of semiconductor chip device method for packing of the present invention in the subsequent step of Fig. 3.
Main element conventional letter table in the accompanying drawing
1 semiconductor wafer, 10 pad installation surface
11 weld pads, 12 metallic conduction pieces
13 through holes, 2 first insulating barriers
30 first electric conductors, 31 second electric conductors
300 first ends, 301 the second ends
4 conductive layers, 5 second insulating barriers
50 through holes 60 the 3rd electric conductor
61 the 4th electric conductors, 610 first ends
611 the second ends 7 the 3rd insulating barrier
70 through holes, 8 metal contiguous blocks
9 conductor balls
[embodiment]
Before the present invention is described in detail, should be noted that in the middle of whole explanation components identical is to be indicated by identical label.
See also shown in Fig. 1～9, the flow process of the method for packing of the semiconductor chip device with Miltilayer wiring structure of preferred embodiment of the present invention is to be shown.
As shown in FIG. 1, at first, semiconductor wafer 1 is to be provided.This semiconductor wafer 1 has a pad installation surface 10 and several and is installed on weld pad 11 (only showing a weld pad in graphic) on this pad installation surface 10.
Should be noted that this semiconductor wafer 1 can be the wafer that cuts out from a wafer (Wafer), also can be the wafer that does not cut out from a wafer as yet.
Then, one first insulating barrier 2 be can, for example, liquid photoresist (Photo Liquid Film Ink) is printed on the pad installation surface 10 of this wafer 1 by printing means, be heated again to solidify and form.Then, as shown in Figure 2, by known exposure-processed and chemical irrigating medium, this first insulating barrier 2 is that the weld pad 11 corresponding to this wafer 1 is formed with the through hole 13 that several are used to expose corresponding pad 11.Then, utilizing any suitable plating means, is to be formed with a metallic conduction piece 12 on each weld pad 11.
Now, see also shown in Fig. 3,4, Fig. 4 is the vertical view of Fig. 3.Several first electric conductors 30 and several second electric conductors 31 are to be formed at respectively on the corresponding metallic conduction piece 12.In these first electric conductors 30 each has a first end 300 that is electrically connected with corresponding metallic conduction piece 12 and and extends upwardly to the second end 301 on the top surface of this first insulating barrier 2 from this corresponding metallic conduction piece 12.
Then, see also shown in Figure 5ly, the second end of these first electric conductors 30 is to be polished by milled processed.Then, be to form a conductive layer 4 on each first electric conductor 30 by any suitable plating means.This conductive layer 4 is to be made of a nickel coating and a Gold plated Layer.Certainly, this conductive layer 4 can also be made of any other electroplated metal layer, perhaps only comprises an electroplated metal layer.
See also shown in Figure 6ly now, one second insulating barrier 5 is being formed on this first insulating barrier 2 with first insulating barrier, 2 similar modes, and covers these first and second electric conductors 30 and 31.This second insulating barrier 5 also is to be formed with several by known exposure-processed and the next the second end corresponding to these first electric conductors 30 of chemical irrigating medium with these second electric conductors 31 to be used to expose the second end of the first corresponding electric conductor 30 and the through hole 50 of these second electric conductors 31.Should be noted that the structure that shows present embodiment for clear, Fig. 6 is not the cutaway view under same tangent plane.
Then, see also shown in Figure 7ly, several the 3rd electric conductors 60 are formed on the second end that is exposed of the first corresponding electric conductor 30, and several the 4th electric conductors 61 are to be formed on the second corresponding electric conductor 31.In these grade in an imperial examination four electric conductors 61 each has a first end 610 that is electrically connected with corresponding second electric conductor 31 and and extends upwardly to the second end 611 on the top surface of this second insulating barrier 5 from this second corresponding electric conductor 31.
See also now shown in Figure 8, the top of these grade in an imperial examination three electric conductors 60 partly and the second end 611 of these grade in an imperial examination four electric conductors 61 polished by milled processed.Then, one the 3rd insulating barrier 7 is to cover these third and fourth electric conductors 60 and 61 on this second insulating barrier 5 to be formed at first and second insulating barriers 2 and 5 similar modes.
Then, the 3rd insulating barrier 7 also is to be formed with the through hole 70 that several are used to expose the 3rd corresponding electric conductor 60 and the second end of corresponding the 4th electric conductor 61 corresponding to the 3rd electric conductor 60 and the second end 611 of the 4th electric conductor 61 by known exposure-processed and chemical irrigating medium.
Then, on the second end of each the 3rd electric conductor 60 and each the 4th electric conductor 61, be to be formed with a metal contiguous block 8.
At last, see also shown in Figure 9ly, on each metal contiguous block 8, be formed with a conductor ball 9.
Therefore, by application of the present invention,, be still to have enough spaces to form the electric conductor that is connected with external circuit on the one hand, and also can keep high acceptance rate on the other hand even distance is more and more littler between between weld pad.
Should be noted that in above disclosed embodiment, be that first to the 3rd insulating barrier is only arranged, yet the number of insulating barrier is optionally to increase or to reduce.
In sum, semiconductor chip device and the method for packing thereof with Miltilayer wiring structure of the present invention really can pass through above-mentioned disclosed structure, device, reaches its intended purposes and effect.
But above-mentioned graphic and explanation of taking off only is embodiments of the invention, and is non-for limiting protection scope of the present invention; Generally be familiar with the personage of this skill, its other equivalences changed or modify according to the present invention does, all should be encompassed in protection scope of the present invention.
Claims (26)
1. method for packing with semiconductor chip device of Miltilayer wiring structure is characterized in that: comprise following step:
(1) provide semiconductor wafer, this semiconductor wafer has a pad installation surface and several and is installed on weld pad on this pad installation surface;
(2) form one first insulating barrier on the pad installation surface of this wafer, this first insulating barrier is that the weld pad corresponding to this wafer is formed with the through hole that several are used to expose corresponding pad;
(3) form one first electric conductor at least one described weld pad, this first electric conductor has a first end that is electrically connected with this weld pad and and extends upwardly to the second end on the top surface of this first insulating barrier from this weld pad;
(4) form one second insulating barrier on this first insulating barrier, this second insulating barrier is formed with the through hole that several are used to expose the second end of the first corresponding electric conductor corresponding to the second end of this first electric conductor;
(5) on the second end of each first electric conductor, form another electric conductor;
(6) form one the 3rd insulating barrier on this second insulating barrier, the 3rd insulating barrier forms the through hole that several are used to expose another corresponding electric conductor corresponding to described another electric conductor;
(7) on each described another electric conductor, form a conductor ball.
2. the method for packing with semiconductor chip device of Miltilayer wiring structure as claimed in claim 1, it is characterized in that: before in the step (3) that forms first electric conductor, more comprise a step that forms a metallic conduction piece on each weld pad of wafer, the first end of each this first electric conductor is to be electrically connected with corresponding metallic conduction piece.
3. the method for packing with semiconductor chip device of Miltilayer wiring structure as claimed in claim 2, it is characterized in that: in the step (3) that forms first electric conductor, more comprise the step that forms one second electric conductor at least one weld pad in this weld pad, this second electric conductor be with corresponding pad on the metallic conduction piece be electrically connected, and, in the step (4) that forms this second insulating barrier, this second insulating barrier is to be formed with the through hole that several are used to expose the second corresponding electric conductor corresponding to this second electric conductor.
4. the method for packing with semiconductor chip device of Miltilayer wiring structure as claimed in claim 3, it is characterized in that: in the step (5) that forms another electric conductor, this another electric conductor is the 3rd electric conductor, and form in the step (5) of another electric conductor at this, more comprise a step that forms one the 4th electric conductor on each second electric conductor, the 4th electric conductor has a first end that is electrically connected with corresponding second electric conductor and and extends up to the second end on the top surface of this second insulating barrier from this second corresponding electric conductor.
5. the method for packing with semiconductor chip device of Miltilayer wiring structure as claimed in claim 4, it is characterized in that: in forming the step (6) of the 3rd insulating barrier, the 3rd insulating barrier more forms the through hole that several are used to expose the second end of the 4th corresponding electric conductor corresponding to the second end of the 4th electric conductor.
6. the method for packing with semiconductor chip device of Miltilayer wiring structure as claimed in claim 5, it is characterized in that: in the step (7) that forms conductor ball, more comprise a step that on the second end of each the 4th electric conductor, forms a conductor ball.
7. the method for packing with semiconductor chip device of Miltilayer wiring structure as claimed in claim 1, it is characterized in that: in the step (4) that forms this second insulating barrier before, more comprise a step that the second end of this first electric conductor is polished by milled processed.
8. the method for packing with semiconductor chip device of Miltilayer wiring structure as claimed in claim 1, it is characterized in that: in the step (4) that forms this second insulating barrier before, more comprise a step that forms a conductive layer in each on this first electric conductor.
9. the method for packing with semiconductor chip device of Miltilayer wiring structure as claimed in claim 8 is characterized in that: in the step that forms described conductive layer, each this conductive layer is to be made of a nickel coating and a Gold plated Layer.
10. the method for packing with semiconductor chip device of Miltilayer wiring structure as claimed in claim 1 is characterized in that: in the step (4) that forms this second insulating barrier before, more comprise following step:
By milled processed the second end of this first electric conductor is polished; Reach in each and form a conductive layer on this first electric conductor.
11. the method for packing with semiconductor chip device of Miltilayer wiring structure as claimed in claim 10 is characterized in that: in the step that forms this conductive layer, each this conductive layer is to be made of a nickel coating and a Gold plated Layer.
12. the method for packing with semiconductor chip device of Miltilayer wiring structure as claimed in claim 5, it is characterized in that: in the step (6) that forms the 3rd insulating barrier before, more comprise a step that the second end of the 3rd electric conductor and the 4th electric conductor is polished by milled processed.
13. the method for packing with semiconductor chip device of Miltilayer wiring structure as claimed in claim 12, it is characterized in that: after the step that the second end of the 3rd electric conductor and the 4th electric conductor is polished, more comprise a step that on the second end of each the 3rd electric conductor and each the 4th electric conductor, forms a metal contiguous block.
14. the semiconductor chip device with Miltilayer wiring structure is characterized in that: comprise:
Semiconductor wafer, this semiconductor wafer have a pad installation surface and several and are installed on weld pad on this pad installation surface;
One is formed at first insulating barrier on the pad installation surface of this wafer, and this first insulating barrier is formed with the through hole that several are used to expose corresponding pad corresponding to the weld pad of this wafer;
First electric conductor that forms at least one this weld pad, this first electric conductor have a first end that is electrically connected with corresponding pad and and extend upwardly to the second end on the top surface of this first insulating barrier from this corresponding pad;
One is formed at second insulating barrier on this first insulating barrier, and this second insulating barrier is formed with the through hole that several are used to expose the second end of the first corresponding electric conductor corresponding to the second end of this first electric conductor;
Another electric conductor of at least one that forms on the first end of at least one first electric conductor in this;
One is formed at the 3rd insulating barrier on this second insulating barrier, and the 3rd insulating barrier is formed with the through hole that several are used to expose another corresponding electric conductor corresponding to these another electric conductors; An and conductor ball that is formed on this at least one another electric conductor.
15. the semiconductor chip device with Miltilayer wiring structure as claimed in claim 14, it is characterized in that: more comprise a metallic conduction piece on each weld pad that is formed at wafer, the first end of each this first electric conductor is to be electrically connected with corresponding metallic conduction piece.
16. the semiconductor chip device with Miltilayer wiring structure as claimed in claim 15, it is characterized in that: more comprise at least one and be formed at second electric conductor on another weld pad in the described weld pad, this second electric conductor be with corresponding pad on the metallic conduction piece be electrically connected, this second insulating barrier more is formed with the through hole that several are used to expose the second corresponding electric conductor corresponding to this second electric conductor.
17. the semiconductor chip device with Miltilayer wiring structure as claimed in claim 16, it is characterized in that: this another electric conductor is the 3rd electric conductor, more be formed with the 4th electric conductor on each second electric conductor, the 4th electric conductor has a first end that is electrically connected with corresponding second electric conductor and and extends up to the second end on the top surface of this second insulating barrier from this second corresponding electric conductor.
18. the semiconductor chip device with Miltilayer wiring structure as claimed in claim 17 is characterized in that: the 3rd insulating barrier forms the through hole that several are used to expose the second end of the 4th corresponding electric conductor corresponding to the second end of the 4th electric conductor.
19. the semiconductor chip device with Miltilayer wiring structure as claimed in claim 18 is characterized in that: on the second end of each the 4th electric conductor, be formed with a conductor ball.
20. the semiconductor chip device with Miltilayer wiring structure as claimed in claim 14 is characterized in that: the second end of this first electric conductor is polished by milled processed.
21. the semiconductor chip device with Miltilayer wiring structure as claimed in claim 14 is characterized in that: more comprise the conductive layer that is formed on each this first electric conductor.
22. the semiconductor chip device with Miltilayer wiring structure as claimed in claim 21 is characterized in that: each this conductive layer is to be made of a nickel coating and a Gold plated Layer.
23. the semiconductor chip device with Miltilayer wiring structure as claimed in claim 14 is characterized in that: the second end of this first electric conductor is polished by milled processed, and forms a conductive layer on this first electric conductor in each.
24. the semiconductor chip device with Miltilayer wiring structure as claimed in claim 23 is characterized in that: each this conductive layer is to be made of a nickel coating and a Gold plated Layer.
25. the semiconductor chip device with Miltilayer wiring structure as claimed in claim 18 is characterized in that: the second end of the 3rd electric conductor and the 4th electric conductor is polished by milled processed.
26. the semiconductor chip device with Miltilayer wiring structure as claimed in claim 25 is characterized in that: more comprise the metal contiguous block on the second end that is formed at each the 3rd electric conductor and each the 4th electric conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100074834A CN100382263C (en) | 2004-03-05 | 2004-03-05 | Semiconductor wafer device having multilayer wiring structure and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100074834A CN100382263C (en) | 2004-03-05 | 2004-03-05 | Semiconductor wafer device having multilayer wiring structure and packaging method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1665009A true CN1665009A (en) | 2005-09-07 |
| CN100382263C CN100382263C (en) | 2008-04-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100074834A Expired - Fee Related CN100382263C (en) | 2004-03-05 | 2004-03-05 | Semiconductor wafer device having multilayer wiring structure and packaging method thereof |
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| Country | Link |
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| CN (1) | CN100382263C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719488B (en) * | 2008-10-09 | 2011-12-21 | 台湾积体电路制造股份有限公司 | Bond pad connection to redistribution lines having tapered profiles |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3128324B2 (en) * | 1992-05-20 | 2001-01-29 | 株式会社東芝 | Ceramic multilayer package for semiconductor |
| KR100192180B1 (en) * | 1996-03-06 | 1999-06-15 | 김영환 | Buttom lead package of multi layer |
| JPH11186434A (en) * | 1997-12-18 | 1999-07-09 | Kyocera Corp | Multi-layer wiring substrate |
| JP4037561B2 (en) * | 1999-06-28 | 2008-01-23 | 株式会社東芝 | Manufacturing method of semiconductor device |
| CN1225791C (en) * | 2002-02-09 | 2005-11-02 | 旺宏电子股份有限公司 | Semiconductor configuration and making process |
| JP3612310B2 (en) * | 2002-06-18 | 2005-01-19 | 株式会社東芝 | Semiconductor device |
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2004
- 2004-03-05 CN CNB2004100074834A patent/CN100382263C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719488B (en) * | 2008-10-09 | 2011-12-21 | 台湾积体电路制造股份有限公司 | Bond pad connection to redistribution lines having tapered profiles |
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| CN100382263C (en) | 2008-04-16 |
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Granted publication date: 20080416 Termination date: 20130305 |