CN1664959A - Memory device for pre-burning test and method therefor - Google Patents
Memory device for pre-burning test and method therefor Download PDFInfo
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- CN1664959A CN1664959A CN 200410028640 CN200410028640A CN1664959A CN 1664959 A CN1664959 A CN 1664959A CN 200410028640 CN200410028640 CN 200410028640 CN 200410028640 A CN200410028640 A CN 200410028640A CN 1664959 A CN1664959 A CN 1664959A
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Abstract
This invention relates to a prefire testing memory device and its method, which comprises multiple sub-array character, drain current limit units and multiple single character drain current limit units. The device uses an intended character line current rating to limit every current through every character line. In the prefire test, character line drive output is in high-impedance state. Bit line forcing voltage is pressurized in a line of memory via normal read-write path. In prefire testing mode, even number and odd number character lines are sub-grouped and character line forcing voltage added on the even and odd character line in alternatively switching way.
Description
[technical field]
The invention relates to a kind of storage arrangement, and, in dynamic RAM (DRAM), detect the method for defect memory particularly relevant for a kind of storage arrangement that is used for burn-in testing and a kind of in wafer stage.
[background technology]
Generally speaking, burn-in testing system tests to prevent reliability issues the semiconductor storer.Or rather, be assemble (assembled) or encapsulation at storer (packaged) finish after.If the element that is detected words defective can't or re-assembly with laser repairing (re-assembled).Therefore, a large amount of production can be very expensive.Burn-in testing is carried out under high pressure and high temperature usually, semiconductor memory component is operated under the state that reads or writes, to detect the problematic flaw of possibility, for example transistorized grid layer, storage node, the p/n of memory component connect the flaw of insulation course, adjacent character line, adjacent bit line, character line and the bit line of face, electric capacity.But the character linear system of opening determines in regular turn that according to the row address particularly for DRAM, and the character line of opening also will be according to the number of update cycle.For instance, a specific character line is an example with 4M DRAM, can select once in 1024 cycles; With 16M DRAM is example, can select once in 2048 or 4096 cycles; With 64MDRAM is example, can select once in 4096 or 8192 cycles.In addition, when estimating the efficient of a storer that is subjected to the voltage pressurization, the work period of character line and complementary burn-in testing data (1 and 0) are very important.If the burn-in testing time can't increase, the efficient of pressurization can be very low, particularly for the memory component of new generation of high density.For a capable address, take the data of storage or write new data and also can suffer similar difficulty.If all character lines start simultaneously, and all storeies upgrade synchronously, and burn-in testing time and expense can reduce significantly, particularly for wafer stage.
Consider above-mentioned problem, the mode that some are traditional comprises circuit and method, can increase burn-in testing efficient at wafer stage or encapsulated phase.Below do brief narration.
In U.S. Patent No. 5265057, all character lines start simultaneously, or the startup of hiving off, so that adjacent character line is pressurizeed.Operating voltage does not act on the element, makes pressurization voltage to import, and the lock (pass gate) that passes through that perhaps will be connected to intensifier circuit cuts out, and wherein is connected between intensifier circuit and the novel word-line driver design for pseudo two-port by lock system.Like this, pressurization voltage can be imported by outside pin position.The burn-in testing data are via bit line precharge element input, and add and be pressed on the paratope unit line.So, burn-in testing data are write store.
In U.S. Patent No. 5293340, pressurization voltage provides via a predetermined external testing pin position.Simultaneously character line is pressurizeed via a PMOS.Two extra nmos pass transistors are connected respectively to the bit line to (bit line pair), and input pre-burning data.
In U.S. Patent No. 5381373, when element in burn-in testing, intensifier circuit does not start and word line voltages source and the short circuit of element operation voltage source.Also from the input of bit line precharge element, in addition, bit line precharge generator separates with the capacitor board voltage generator burn-in testing data.
In U.S. Patent No. 5590079 and No.5790465, two NMOS elements are moved low (low) current potential to through the NMOS that connects a novel word-line driver design for pseudo two-port, and have only a NMOS among two NMOS to start in normal mode or burn-in testing pattern.In normal operation, the NMOS of a ground connection opens to be used to lower the character line noise signal.Other NMOS open in the burn-in testing pattern so that character line pressurization voltage to be provided.
In U.S. Patent No. 5638331, a test circuit is used for the novel word-line driver design for pseudo two-port of nmos type is located at high impedance status.Before the burn-in testing mode initialization, pre-burning background data write store, operating voltage is added on the character line so that grid oxic horizon is pressurizeed via PMOS then.
In U.S. Patent No. 5926423, capacitor board voltage separates with a bit line pre-charge voltage by lock (pass gate) via CMOS, and wherein CMOS ties up to the output terminal of voltage generator by lock.Bit line pressurization voltage is sent to the bit line by external voltage or complementary interior voltage via pressurization conversion PMOS and bit line precharge NMOS.
In U.S. Patent No. 6055199, a bit line pre-charge circuit is connected to an external testing pin position in order to supply with bit line pressurization voltage and a bit line precharge element and a storer.Character line is divided into the address of even number and odd number, and bit line pressurization voltage is supplied to storer via bit line precharge element.So, a memory test type sample (pattern) has just produced.
In U.S. Patent No. 6169694, wafer stage presintering test circuit in the complete wafer is proposed.Comprising three main circuit.A high voltage generator unit produces character line pressurization voltage in order to detect the grid oxic horizon flaw.Bit line pre-charge voltage and capacitor board voltage are provided by bit line pre-charge voltage generation unit and capacitor board voltage generation unit respectively.The burn-in testing data are by the input of bit line precharge element, and capacitor board voltage is used for storer is pressurizeed.
In above-mentioned traditional approach, grid oxic horizon pressurization voltage is from an external power source, via a predetermined external testing pin position or internal high voltages generator input.No matter which type of voltage source is wafer designer select for use, the maximum current that voltage source can be supplied exists forever.For example, in burn-in testing, the burning of a character line flaw success goes out, and the inner relevant flaw of character line is perhaps arranged.The both causes the drain current path at this bit line.In extreme situation, these flaws cause character line direct short-circuit to ground, to such an extent as to make the too big voltage source of leakage current be unable to supply.Because voltage source can't be supported leakage current, so character line pressurization voltage reduces significantly.When pressurization voltage reduces, the electric field deficiency of crossing over grid oxic horizon.Therefore, the flaw that other grid oxic horizons are relevant just can't detect.
Further, in conventional wafer stage burn-in test method, the pre-burning background data writes via a bit line preliminary filling source element or an element that additionally is connected to the bit line, and in this method, capacitor board voltage need separate with bit line pre-charge voltage.The former pressurizes to insulating layer of capacitor, and the latter writes the burn-in testing data.The bit line has identical voltage level usually with complementary bit line, does not therefore have electric field between the two.This method can't detect flaw relevant between adjacent bit line.Another shortcoming is that voltage level separately has different reactions to the ground connection noise signal, and in normal operation, this can have bad effect to bit line input.
[summary of the invention]
Therefore purpose of the present invention is providing an a kind of storage arrangement and a presintering test circuit with exactlying, can keep the pressurization situation in burn-in testing and when seriously flaw exists.
Another object of the present invention is that a kind of storage arrangement, a presintering test circuit and a method are being provided, and the method can make the character line driving circuit be in high impedance status, makes character line pressurization voltage to be imported by a leakage current limiting unit.
Another purpose of the present invention is that an a kind of storage arrangement and a presintering test circuit are being provided, and can write the burn-in testing background data via normal data read-write path.
A further object of the present invention is that a kind of storage arrangement, a presintering test circuit and a method are being provided, and the method can increase burn-in testing efficient and reduce the burn-in testing time.
According to above-mentioned purpose of the present invention, a kind of storage arrangement that is used for burn-in testing is proposed.This storage arrangement comprises a memory array, a plurality of character line, a plurality of bit line and a leakage current limiting unit.The leakage current limiting unit connects memory array so far through a plurality of character lines thus.
When burn-in testing, the leakage current limiting unit limits the electric current of each character line of flowing through with a book character line current value, and character line pressurization voltage provides each line storage that gives in the memory array via the leakage current limiting unit, and with this character line pressurization voltage each line storage is pressurizeed.Wherein each line storage is connected in a character line.
The leakage current limiting unit more comprises a plurality of array character line leakage current limiting units and a plurality of single character line leakage current limiting unit.Wherein array character line leakage current limiting unit is connected to the character line of a number each time.Inferior array character line leakage current limiting unit limits the total current value of the character line of this number of flowing through with a predetermined inferior array current value.
Predetermined time array current value is relevant with the number of preparation character line.Each single character line leakage current limiting unit is connected to a character line, and limits the electric current of this character line of flowing through with the book character line current value.The current limited system of a character line because flow through is so voltage source can be supplied enough voltage with all character lines that pressurizes.So, this storage arrangement can be kept the pressurization situation when burn-in testing and serious flaw exist.
According to purpose of the present invention, the output terminal that proposes a kind of maintenance one novel word-line driver design for pseudo two-port is in the method for high impedance status.The method is used for the burn-in testing of a storer.This novel word-line driver design for pseudo two-port has a mutual load that connects.
The method comprises the following step.At first, make each MOS transistor be in high impedance status.Then, a predetermined high voltage is added on this mutual load that connects.Then, provide a predetermined low voltage to give the output terminal of this novel word-line driver design for pseudo two-port via a character line.The method can place high impedance status with novel word-line driver design for pseudo two-port, makes character line pressurization voltage to be imported by a leakage current limiting unit.
According to purpose of the present invention, a kind of commutation circuit is proposed, between a normal data access path and a burn-in testing path, switch.When normal mode, the read-write motion of row storer system carries out via the normal data access path, and wherein this row storer is connected in a bit line.
When the burn-in testing pattern, via the burn-in testing path, bit line pressurization voltage is imported this row storer to carry out burn-in testing.Therefore, this commutation circuit can write the burn-in testing background data via normal data read-write path.
According to purpose of the present invention, a kind of method of storage arrangement being carried out burn-in testing is proposed.The method comprises the following steps.At first, the load with the mutual connection of novel word-line driver design for pseudo two-port adds a predetermined high voltage.Then, notify this storage arrangement with a burn-in testing mode signal.
Then, a plurality of character lines are added character line pressurization voltage.Then, the reservior capacitor with memory array adds a capacitor board voltage.Then, a plurality of bit lines are added bit line pressurization voltage.The method comprises sensing amplifier control signal anergy, and all inferior array character lines and bit switch is opened.The method can increase burn-in testing efficient and reduce the burn-in testing time.
It must be appreciated that aforesaid general description and ensuing embodiment are all for example, in order to provide further explanation to claim of the present invention.
[description of drawings]
State with other purposes, feature and advantage and can become apparent on the present invention for allowing, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Figure 1A illustrates the calcspar of a preferred embodiment of the present invention;
Figure 1B illustrates the thin portion structure calcspar of preferred embodiment of the present invention;
Fig. 1 C illustrates the circuit diagram of an example of preferred embodiment of the present invention;
Fig. 2 A illustrates a part of circuit diagram of a novel word-line driver design for pseudo two-port;
Fig. 2 B illustrates the sample circuit diagram of intensifier circuit, inferior array decoder, novel word-line driver design for pseudo two-port, single character line leakage current limiting unit and inferior array character line leakage current limiting unit;
Fig. 3 A illustrates the calcspar of commutation circuit of the present invention;
Fig. 3 B illustrates the circuit diagram of an explanation pre-burning data write paths; And
Fig. 4 is the example of the time sequential routine mode chart of burn-in testing pattern.
[embodiment]
The present invention describes in detail with the real by way of example of doing, and the example among the embodiment is to describe with reference to graphic mode.The identical identical or similar part of label representative in the graphic and instructions.
Figure 1A illustrates the calcspar of a preferred embodiment of the present invention.Figure 1B illustrates the thin portion structure calcspar of preferred embodiment of the present invention.Please refer to Figure 1A and Figure 1B, storage arrangement 102 comprises a memory array 112, a plurality of character line 106, a plurality of bit line 110 and a leakage current limiting unit 108.
Each character line 106 is connected in the delegation in the memory array 112.Each bit line 110 is connected in the row in the memory array 112.Leakage current limiting unit 108 is connected in memory array 112 via a plurality of character lines 106.
Please refer to Figure 1B, for instance, leakage current limiting unit 108 comprises a plurality of single character line leakage current limiting units 124 and a plurality of array character line leakage current limiting units 126.Each single character line leakage current limiting unit 124 is connected in a character line and limits the electric current of this character line of flowing through with a book character line current value.
Array character line leakage current limiting unit 126 is connected in the character line of a number each time, and limits the total current value of the character line of this number of flowing through with a predetermined inferior array current value.Inferior array character line leakage current limiting unit 126 connects the character line of number so far via single character line leakage current limiting unit 124.
Fig. 1 C illustrates the circuit diagram of an example of preferred embodiment of the present invention.Single character line leakage current limiting unit 124 is a MOS transistor for example.Fig. 2 B illustrates the sample circuit diagram of intensifier circuit (boost circuit) 138, inferior array decoder 262, novel word-line driver design for pseudo two-port 208, single character line leakage current limiting unit 124 and inferior array character line leakage current limiting unit 126.For example, inferior array character line leakage current limiting unit 126 comprises a level translator at least, and each level translator is in order to the restriction electric current.
Please refer to Fig. 1 C and Fig. 2 B, at normal mode, burn-in testing mode signal WBI 142 is in low-potential state.Pin position 125 and 128 can be used for monitoring under normal mode.Pin position 125 and 128 can be used for forcing making alive under the burn-in testing pattern.Voltage generator 130 produces a predetermined high voltage 127 (being VW) and offers the n type well (n well) of all PMOS.In Fig. 2 B, PMOS transistor 204 and 206 source electrode or drain electrode are connected to character line 106 via single character line leakage current limiting unit 124.
At normal mode, according to the decision of WBI 142, single character line leakage current limiting unit 124 and inferior array character line leakage current limiting unit 126 are anergy, so node WBG 144, ODD 146 and EVEN 148 all maintain low-potential state.Bit switch 150,152 or 154,156 is by the decision of row address.In the middle of a cycle that writes, the input data are by pin position 151 and 153 inputs.Simultaneously, switch S1 158 and S3 160 open.The input data then input to IO line (IO0 162, and IO0N 164).Then, amplifier 172 will be imported data and be sent to data line (DL Φ 166, DL Φ N 168).The input data write a sensing amplifier 170 via bit switch 150 and 152.At last, storer 112 is via sensing amplifier 170 charge or discharge.
In burn-in testing, the burn-in testing mode signal, WBI 142, are set to high potential state.When WBI 142 was high potential state, all input buffers 180,181,182,183,184 and 185 were anergy; Intensifier circuit 138 activations maintain high impedance status to assist novel word-line driver design for pseudo two-port 208; All inferior array novel word-line driver design for pseudo two-port 140 are opening; All bit switchs are opening; And utilize the mode of closing the sensing amplifier control signal, making all sensing amplifiers is closed condition.
Predetermined high voltage 127 (VW) is by 125 inputs of pin position.At this moment, predetermined high voltage 127 (VW) forces input with the magnitude of voltage that is higher than voltage generator 130 original design.For preventing voltage competition (contention) between voltage generator 130 and the predetermined high voltage 127 (VW), voltage generator 130 automatic anergies.Pin position 107,109 and 111 is used to set up character line burn-in testing kenel, and this kenel is for carrying out character line synchronously or alternately burn-in testing.This expression is if signal ODD 146 and EVEN 148 are all high potential state, and then start signal WBG 144 makes it to be in high potential state.So, character line 106 pressurizes simultaneously.Another example is that signal ODD 146 and EVEN 148 alternately switch between high potential state and low-potential state, and so, 106 of character lines hive off and alternately pressurize.
Bit line pressurization voltage is by 115 inputs of pin position.Switch 117 and 119 open make bit line pressurization voltage via normal read-write path to data line (DL Φ 166, DL Φ N 168 and DL1 121, DL1N123)., all bit switchs and all sensing amplifiers open and closed condition the easy write store 112 of bit line pressurization voltage because being respectively.In the burn-in testing pattern, according to WBI 142, voltage generator circuit 132 anergies.Therefore, force by pin position 128 and add that capacitor board voltage VEQ 136 is with to the pressurization of the insulation course (insulator film) of reservior capacitor 116 (shown in Figure 1B), with the input data.
Fig. 2 A illustrates a part of circuit diagram of a novel word-line driver design for pseudo two-port.Please refer to Fig. 2 A and Fig. 2 B, novel word-line driver design for pseudo two-port 208 has a mutual load 210 that connects.This mutual load 210 that connects has one the one PMOS transistor 212 and one the 2nd PMOS transistor 214.
The source electrode 216 of the one PMOS transistor 212 is connected in the source electrode 218 of the 2nd PMOS transistor 214.The grid 220 of the one PMOS transistor 212 is connected in the drain electrode 222 of the 2nd PMOS transistor 214.The grid 224 of the 2nd PMOS transistor 214 is connected in the drain electrode 226 of a PMOS transistor 212.The output terminal 228 of novel word-line driver design for pseudo two-port 208 be positioned at a PMOS transistor 212 drain electrode 226.Character line 230 is connected in the output terminal 228 of storer 112 and novel word-line driver design for pseudo two-port 208.
Fig. 2 B illustrates the sample circuit diagram of intensifier circuit 138, inferior array decoder 262, novel word-line driver design for pseudo two-port 208, single character line leakage current limiting unit 124 and inferior array character line leakage current limiting unit 126.At normal mode, PRECH 232 is in high potential state; LKSPN 234 is in high potential state; And BOOST 134 is in low-potential state.Before sending RAS order, MOS transistor 236 is used for node VH 240 is done precharge, and is precharged to the potential level of VCC 238.Send when RAS order, PRECH 232 is in low-potential state; LKSPN 234 is in low-potential state; And BOOST 134 is in high potential state.The electric charge that is stored in capacitor C 242 pours into to node VH 240, and in a long RAS sampling action, PMOS transistor 244 is used to keep the leakage current of the character line of a startup.
In normal mode, one or more time array novel word-line driver design for pseudo two-port 140 is selected, so the voltage level that signal SUB ARRAY 246 becomes high-voltage state and node VH Φ 248 becomes VH 240 by VCC 238.One group of row address decision signal ROW_1 251 is in high potential state, and ROW_2N 250 is in low-potential state, and ROW_3N 252 is in low-potential state, makes a character line be in opening.Strengthen electric charge (boot charge) and be sent to the grid that captures transistor 114, open storer 112 for read-write motion via MOS transistor 254 and PMOS transistor 212.Because WBI 142 is in low-potential state, the output terminal of inferior array character line leakage current limiting unit 126, comprise three level translators 203,205 and 207, all be in low-potential state, meaning is that WBG 144, ODD 146 and EVEN 148 all are in low-potential state, and the NMOS in single character line leakage current limiting unit 124 all is in closed condition.
In the burn-in testing pattern, please refer to Fig. 2 A, following a kind of output terminal 228 of novel word-line driver design for pseudo two-port 208 that keeps of example narration is in the method for high impedance status.At first, except a PMOS transistor 212 and the 2nd PMOS transistor 214, make each MOS transistor (264 and 266) be in high impedance status.Wherein MOS transistor 264 and 266 is positioned at novel word-line driver design for pseudo two-port 208 and output terminal 228 that be connected in novel word-line driver design for pseudo two-port 208.
Then, will be scheduled to make the source electrode of win PMOS transistor 212 and the 2nd PMOS transistor 214 all maintain predetermined high voltage 127 (VW) on the source electrode 216 that high voltage 127 (VW) is added in a PMOS transistor 212.Then, the output terminal 228 that provides a predetermined low voltage to give novel word-line driver design for pseudo two-port 208 via character line 230.
Fig. 2 B provides a kind of details circuit diagram that keeps the output terminal 228 of novel word-line driver design for pseudo two-port 208 in the high impedance status method.Please refer to Fig. 2 B, in the burn-in testing pattern, WBI 142 is in high potential state; Intensifier circuit 138 is in enabled status; PRECH 232 is in low-potential state; LKSPN 234 is in low-potential state; BOOST 134 is in high potential state; All inferior array novel word-line driver design for pseudo two-port 140 all are selected; All inferior array decoders 262 all are in starting state; Because PMOS transistor 244 and MOS transistor 254 are all opening, the voltage of node VH Φ 248 is equal to predetermined high voltage 127 (VW).WBI 142 is located at low-voltage state with ROW_1 251, and ROW_2N 250 is located at low-voltage state and ROW_3N 252 is located at low-voltage state, and meaning is that MOS transistor 263, MOS transistor 264 and MOS transistor 266 all are in closed condition.
When the burn-in testing state model was early stage, pin position 107 and 109 all was in low-potential state.Pin position 111 is set in high potential state earlier, therefore WBG 144 is in high potential state, ODD 146 and EVEN 148 are in low-potential state (being predetermined low voltage), so the PMOS transistor 214 of novel word-line driver design for pseudo two-port 208 is opened and the grid 220 of PMOS transistor 212 is increased to predetermined high voltage 127 (VW) to close PMOS transistor 212.Therefore, the MOS transistor 264,266 and the PMOS transistor 212 of novel word-line driver design for pseudo two-port 208 are all closed condition, and wherein MOS transistor 264,266 and PMOS transistor 212 all are connected to character line 230.Therefore, novel word-line driver design for pseudo two-port 208 is in high impedance status.
In the burn-in testing pattern, alternately switch between high potential state and low-potential state test pin position 109 and 107, so the output terminal of level translator 205 and 207 is equal to VW 127 or VSS, and wherein VSS is the minimum voltage in the burn-in testing pattern.This narration is decided according to test duration type sample (testtiming pattern).For example, pin position 111 and 107 is in high potential state, and pin position 109 is in low-potential state.Then, it is accurate that WBG 144 and EVEN 148 are in the position of VW 127, and ODD146 is in low-potential state.Therefore, even number character line WL0 230 ... WL_ (2n) 211 is promoted to VW-Vthn, and this is character line pressurization voltage.Vthn is the threshold voltage (threshold voltage) of MOS transistor in the single character line leakage current limiting unit 124.Even under this test mode, PMOS transistor 214 can be closed, or has some drain current paths (leakage) to exist in the grid 220 of PMOS transistor 212.It is accurate to keep the closed condition of PMOS transistor 212 that the grid 220 of PMOS transistor 212 can't maintain the position of VW 127, and character line pressurization this moment voltage still maintains VW-Vthn or VW 127.
MOS transistor in the single character line leakage current limiting unit 124 is used as current-limiting apparatus use, and this current-limiting apparatus will support leakage current (sustain leakage current) limit by the maximum current of a single character line or the maximum of single flaw (defected) character line.Wherein maximum support leakage current is the book character line current value.Character line pressurization voltage (being VW-Vthn) is that wherein the row of each in the memory array 112 system is connected in a character line via leakage current limiting unit 108 (shown in Figure 1A) making alive each row in memory array 112.Level translator 203,205 and 207 is used as the another one current-limiting apparatus, and this current-limiting apparatus limits the maximum character line pump current of time array 103 (shown in Figure 1B) of flowing through.Wherein maximum character line pump current is predetermined time array current value.Predetermined time array current value in the inferior array character line leakage current limiting unit 126 is decided according to the number of standby character line.
Predetermined time array current value is between one first current value and an electric current and value.The lowest high-current value that this first current value can provide for standby character line, this electric current and value be first current value and one second current value sum for this reason.The lowest high-current value that this second current value can provide for an extra standby character line.
For example, in one array, there are two standby character lines can be used for replacing the flaw character line.If the book character line current value is set at 300uA, then the maximum current of the PMOS transistor 206 of the PMOS transistor 204 of level translator 205 or level translator 207 then is located between 600uA ~ 900uA.In this example, first current value (600uA) is the lowest high-current value that these standby character lines can provide.Second current value (300uA) is the lowest high-current value that an extra standby character line can provide.Electric current and value (900uA) are first current value (600uA) and second current value (300uA) sum.Therefore, predetermined time array current value is between first current value (600uA) and electric current and value (900uA).Wafer (die) with the leakage current (leakage) above 900uA must be abandoned, because there are not enough standby character lines to use.
Say that further it is accurate to pressurize other wafer (die), particularly when the wafer stage parallel testing (wafer level parallel test) that character line pressurization voltage must maintain sufficiently high position.In fact,, then do not have enough electric currents can supply other character line, cause invalid pre-burning (ineffective burn-in) if the too many electric current of voltage generator 130 supplies is given minority flaw character line.In extreme situation, leakage current has surpassed the electric current that voltage source can provide, so character line pressurization voltage descends too many.
Shown in Figure 1A, the total current that flows to storage arrangement 102 is limited to a predetermined total current.This predetermined total current is less than the maximum current that a voltage source can provide.Wherein this voltage source provides character line pressurization voltage to give storage arrangement 102.
In Fig. 2 B, MOS transistor 280,282 and 284 is used as the load of level translator 203,205 and 207 respectively, in order to the transmission that slows down level translator 203,205 and 207 and reduce peak value (peak value) electric current in the burn-in testing pattern to minimum value.
Fig. 3 A illustrates the calcspar of commutation circuit of the present invention.Please refer to Fig. 3 A, commutation circuit 300 is used for switching between a normal data access path 304 and a burn-in testing path 306.Commutation circuit 300 is used for the row in burn-in testing testing memory array 112.Commutation circuit 300 comprises that data enter a unit 308 and a switch 302.Data enter unit 308 and are used for transmitting this row storer that the input data are given memory array 112 via a bit line 309, and wherein bit line 309 is to be connected in this row storer 112.Switch 302 is connected in data and enters unit 308, and switch 302 is used for switching between normal data access path 304 and burn-in testing path 306.Switch 302 transmits the input data, and wherein this input data system selects input data by normal data access path 304 or burn-in testing path 306 and enters unit 308.
At normal mode, the read-write motion of this row storer is that wherein this row storer is connected in bit line 309 via normal data access path 304.When the burn-in testing pattern, bit line pressurization voltage is the input data, and via burn-in testing path 306, this bit line pressurization voltage is imported this row storer to carry out burn-in testing.
Fig. 3 B illustrates the circuit diagram of an explanation pre-burning data write paths, and this pre-burning data write paths system passes through burn-in testing path 306 and normally reads and writes path 311 and enters a storer 112.In the burn-in testing pattern, all bit switchs are for opening.BS Φ 310 and VCCSA 312 all are equal to VCC.The sensing amplifier control signal is made as closed condition.SP1 314 and SP2 316 all are in high potential state.SN1 318 and SN2 320 all are in low-potential state.PMOS transistor 322,324 and nmos pass transistor 326,328 all are in closed condition.EQD 330 is in low-potential state.Bit line pre-charging device 332 is a closed condition.MOS transistor 334,336 and 338 is a closed condition.The pre-burning background data is used as the input data and is entered DL Φ 166 and complementary DL Φ N 168 by pin position 115 via burn-in testing path 306 and amplifier 172.
For instance, DL Φ 166 equals VCC; DL Φ N 168 equals VSS; BL Φ 340 equals VCC-Vthn; BL Φ N 342 equals VSS; Vthn is the threshold voltage (threshold voltage) of bit switch 150 and 152.For a pressurized character line, be to be connected to bit line 346 or complementary bit line 348 and to decide according to storer 112, storer 112 writes with the voltage of VCC-Vthn or VSS.Capacitor board voltage (VEQ 136) forces input by pin position 128, and therefore, the insulation course of reservior capacitor 350 is subjected to the voltage pressurization between VEQ 136 and the VCC-Vthn or the voltage between VEQ 136 and the VSS pressurizes.
Fig. 4 is the example of the time sequential routine mode chart of burn-in testing pattern.This time sequential routine mode chart is the method (shown in Figure 1A) of storer 102 being carried out burn-in testing.Please refer to Fig. 4, Figure 1B, 1C figure, 2B figure and Fig. 3 B, the method comprises the following steps: at first, a predetermined high voltage 127 (VW) is added on the source electrode 216 of a PMOS transistor 212 of novel word-line driver design for pseudo two-port 208.Then, with a burn-in testing mode signal WBI 142 notice storage arrangements 102.Then, utilize WBG 144, ODD 146 and EVEN 148 that a plurality of character lines 106 are added character line pressurization voltage.Then, the reservior capacitor with memory array 112 adds a capacitor board voltage (VEQ 136) on 116.Then, via pin position 115 a plurality of bit lines are added bit line pressurization voltage.
When a plurality of bit lines 110 (shown in Figure 1B) add bit line pressurization voltage, this capacitor board voltage (VEQ 136) alternately switches between a high potential state and a low-potential state, make cross-pressure on the storer 112 and the cross-pressure on the reference memory 344 pressurize fully with different magnitudes of voltage, wherein storer 112 is connected in a bit line 346 (shown in Fig. 3 B), and reference memory 344 (storer that promptly faces mutually) is connected in the bit line 348 of a complementation.
Keep data enter the time of setting (set up time) (Tds 402) and data (holdtime) (Tdh 404) that enter the retention time at the rising edge 407 of the capacitor board voltage (VEQ 136) that alternately switches and falling edge 408 places.As shown in Figure 4, hive off, and the character line voltage that pressurizes is added on even number character line and the odd number character line with switching mode alternately with ODD 146 and 148 pairs of odd number character lines of EVEN and even number character line.
In Fig. 2 B, the even number character line is with WL_ (2n) 211 expressions, and the odd number character line is with WL_ (2n-1) 215 expressions.The character line propagation delay time (word line transition delay) (Td 406) places between the character line pressurization voltage that alternately switches, and wherein character line pressurization voltage is added on even number character line 211 and the odd number character line 215 to replace switching mode.
Definition time parameter Td 406, Tds 402 and Tdh404 are to prevent voltage competition (contention) and the electric current surging (peak current) that reduces operation.With VCC 410 or the operating voltage of VCCSA 412 decision storeies 102 (shown in Figure 1A) and the voltage (shown in Figure 1B) that is stored in reservior capacitor 116.
The cross-pressure of storer 112 is equal to VCC-Vthn or VSS.For instance, shown in Fig. 1 C, WBI 142, pin position 111,109,107 and 115 noble potential are equal to VCC, and are used to carry out burn-in testing.Shown in Figure 1B, the grid 118 of the acquisition transistor 114 of the noble potential of VW 127 decision storer 112, this grid 118 is with the voltage pressurization of VW-Vthn.The electric field of the insulation course of the noble potential of test pin position 128 (being capacitor board voltage VEQ 136) and low-potential state decision reservior capacitor 116 is shown in Figure 1B.The burn-in testing mode signal, WBI 142, activation after VW 127 rising 2Tds.Early stage in the burn-in testing pattern, ODD 146 and EVEN 148 must be held in low-potential state and be in high impedance status to keep novel word-line driver design for pseudo two-port 208.Except that this, VEQ 136 does not force pressurization as yet, to keep that voltage generator circuit 132 is not had voltage competition (contention).
In the example of Fig. 4, minimum frequency is test pin position 115.The frequency of VEQ 136 is double, and EVEN 148 and ODD 146 are four times.EVEN 148 and ODD 146 alternately switch so that the grid 118 of acquisition transistor 114 and adjacent character line are pressurizeed.Be connected to bit line 346 or complementary bit line 348 according to storer 112 and decide, the voltage of write store 112 can be 1 or 0, shown in Fig. 3 B.Therefore, capacitor board voltage (VEQ 136) need be transformed into another standard and alternately open odd number and the even number character line, so that all storeies 112 pressurize fully with different voltage.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so the scope of claims that protection scope of the present invention should basis defines and is as the criterion.
Claims (21)
1. storage arrangement that is used for burn-in testing comprises at least:
One memory array;
A plurality of character lines, wherein each character line is connected to the delegation in this memory array; And
One leakage current limiting unit is connected to this memory array via these a plurality of character lines;
Wherein when burn-in testing, this leakage current limiting unit limits the electric current of each character line of flowing through with a book character line current value, and character line pressurization voltage provides each line storage that gives in this memory array via this leakage current limiting unit, and with this character line pressurization voltage this each line storage is pressurizeed, wherein this each line storage is connected in a character line.
2. storage arrangement according to claim 1, it is characterized in that, comprise a plurality of bit lines, wherein each bit line is connected to the delegation in this memory array, each storer comprises an acquisition transistor and a storage capacitors at least, this captures transistorized grid and is connected to a character line, and this acquisition transistor drain is connected to a bit line, and this captures transistorized source electrode and is connected to this storage capacitors.
3. storage arrangement according to claim 1 is characterized in that, this leakage current limiting unit more comprises:
A plurality of single character line leakage current limiting units, wherein each single character line leakage current limiting unit is connected to a character line, and limits the electric current of this character line of flowing through with this book character line current value.
4. storage arrangement according to claim 3 is characterized in that, this single character line leakage current limiting unit comprises a metal oxide semiconductor transistor.
5. storage arrangement according to claim 1 is characterized in that, this leakage current limiting unit further comprises:
A plurality of array character line leakage current limiting units, wherein array character line leakage current limiting unit is connected to the character line of a number each time, and limits the total current value of the character line of this number of flowing through with a predetermined inferior array current value.
6. storage arrangement according to claim 5 is characterized in that, this time array character line leakage current limiting unit comprises at least one level translator, and each level translator is in order to the restriction electric current.
7. storage arrangement according to claim 5, it is characterized in that, this leakage current limiting unit more comprises a plurality of single character line leakage current limiting units, these a plurality of array character line leakage current limiting units are connected in this a plurality of character lines via these a plurality of single character line leakage current limiting units, the electric current that each single character line leakage current limiting unit is connected in a character line and limits this this character line of flowing through with this book character line current value.
8. storage arrangement according to claim 7, it is characterized in that, should be scheduled to time array current value scope between one first current value and an electric current and value, the lowest high-current value that this first current value can provide for standby character line, this electric current and value are this first current value and one second current value sum, the lowest high-current value that this second current value can provide for an extra standby character line.
9. storage arrangement according to claim 1, it is characterized in that, the total current that flows to this storage arrangement is limited to a predetermined total current, and this predetermined total current is less than the maximum current that a voltage source can provide, and wherein this voltage source provides this character line pressurization voltage to give this storage arrangement.
10. an output terminal that keeps a novel word-line driver design for pseudo two-port is in the method for high impedance status, this method is used for a burn-in testing of a storer, wherein this novel word-line driver design for pseudo two-port has a mutual load that connects, should the mutual load that connects have one the one PMOS transistor and one the 2nd PMOS transistor, the transistorized source electrode of the one PMOS is connected in the transistorized source electrode of the 2nd PMOS, the transistorized grid of the one PMOS is connected in the 2nd PMOS transistor drain, the transistorized grid of the 2nd PMOS is connected in a PMOS transistor drain, the output terminal of this novel word-line driver design for pseudo two-port is positioned at a PMOS transistor drain, and this method comprises at least:
This storer is connected via a character line with the output terminal of this novel word-line driver design for pseudo two-port;
Except a PMOS transistor AND gate the 2nd PMOS is transistorized, make each MOS transistor be in high impedance status, wherein this each MOS transistor is positioned at this novel word-line driver design for pseudo two-port and output terminal that be connected in this novel word-line driver design for pseudo two-port;
The transistorized source electrode of the one PMOS is added a predetermined high voltage, make the transistorized source electrode of a PMOS transistor AND gate the 2nd PMOS all be in this predetermined high voltage; And
Provide a predetermined low voltage to give the output terminal of this novel word-line driver design for pseudo two-port via a character line.
11. method according to claim 10, it is characterized in that, this storer comprises an acquisition transistor and a reservior capacitor at least, this captures transistorized grid and is connected in a character line, this acquisition transistor drain is connected in a bit line, and this captures transistorized source electrode and is connected in this reservior capacitor.
12. a commutation circuit is switched between a normal data access path and a burn-in testing path, this commutation circuit is used for the row in burn-in testing testing memory array, and this commutation circuit comprises at least:
One data enter the unit, are used for transmitting the input data via a bit line and give this row storer, and wherein this bit line is connected in this row storer; And
One switch, be connected in these data and enter the unit, this switch is used for switching between this normal data access path and this burn-in testing path, and this switch transmits this input data, and wherein an input is selected by this normal data access path or this burn-in testing path by this input data system;
Wherein this commutation circuit has a normal mode and a burn-in testing pattern;
When normal mode, the read-write motion of this row storer system carries out via this normal data access path, and wherein this row storer is connected in this bit line; And
When the burn-in testing pattern, bit line pressurization voltage is the input data, and via this burn-in testing path, this bit line pressurization voltage is imported this row storer to carry out burn-in testing.
13. commutation circuit according to claim 12, it is characterized in that, each storer comprises an acquisition transistor and a reservior capacitor at least, this captures transistorized grid and is connected to a character line, this acquisition transistor drain is connected to a bit line, and this captures transistorized source electrode and is connected to a storage capacitors.
14. a storage arrangement is used for a burn-in testing, this storage arrangement comprises at least:
One memory circuitry comprises:
One memory array;
A plurality of character lines, each character line is connected in the delegation in this memory array; And
A plurality of bit lines, each bit line is connected in the row in this memory array;
Wherein each storer is fixed by a character line and a bit line selection;
A plurality of commutation circuits, wherein each commutation circuit is used for row of this memory array are done burn-in testing, and each commutation circuit is connected in a bit line and switches between a normal data access path and a burn-in testing path; And
A plurality of novel word-line driver design for pseudo two-port, wherein each novel word-line driver design for pseudo two-port comprises a mutual load that connects at least, should the mutual load that connects have one the one PMOS transistor and one the 2nd PMOS transistor, the transistorized source electrode of the one PMOS is connected in the transistorized source electrode of the 2nd PMOS, the transistorized grid of the one PMOS is connected in the 2nd PMOS transistor drain, the transistorized grid of the 2nd PMOS is connected in a PMOS transistor drain, the output terminal of this novel word-line driver design for pseudo two-port is positioned at a PMOS transistor drain, and each novel word-line driver design for pseudo two-port is connected in a character line via the output of this novel word-line driver design for pseudo two-port.
15. storage arrangement according to claim 14, it is characterized in that, each storer comprises an acquisition transistor and a reservior capacitor at least, this captures transistorized grid and is connected in a character line, this acquisition transistor drain is connected in a bit line, and this captures transistorized source electrode and is connected in this reservior capacitor.
16. storage arrangement according to claim 14 is characterized in that, more comprises:
One leakage current limiting unit, be connected in this memory array via these a plurality of character lines, wherein when burn-in testing, this leakage current limiting unit limits the electric current of each character line of flowing through with a book character line current value, and character line pressurization voltage provides each line storage that gives in this memory array via this leakage current limiting unit, and with this character line pressurization voltage this each line storage is pressurizeed, wherein this each line storage is connected in a character line.
17. the method that claim the 14th described storage arrangement is carried out burn-in testing, this method comprises at least:
The transistorized source electrode of the one PMOS of this novel word-line driver design for pseudo two-port is added a predetermined high voltage;
Notify this storage arrangement with a burn-in testing mode signal;
Should add character line pressurization voltage by a plurality of character lines;
The reservior capacitor of this memory array is added a capacitor board voltage; And
Should add bit line pressurization voltage by a plurality of bit lines.
18. method according to claim 17, it is characterized in that, when these a plurality of bit lines add bit line pressurization voltage, this capacitor board voltage alternately switches between a high potential state and a low-potential state, make cross-pressure and the cross-pressure on the reference memory on the storer pressurize fully with different magnitudes of voltage, wherein this storer is connected in a bit line, and this reference memory is connected in a complementary bit line.
19. method according to claim 18 is characterized in that, at the rising edge of this capacitor board voltage that alternately switches and the falling edge place keeps data to enter the time of setting and data enter the retention time.
20. method according to claim 17 is characterized in that, dual numbers character line and odd number character line hive off, and this character line pressurization voltage is added on even number character line and the odd number character line to replace switching mode.
21. method according to claim 20, it is characterized in that, the character line propagation delay time places between this character line that alternately switches pressurization voltage, and wherein this character line pressurization voltage is added on even number character line and the odd number character line to replace switching mode.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106531225A (en) * | 2015-09-09 | 2017-03-22 | 力晶科技股份有限公司 | Wafer level dynamic burn-in test method |
| US11609705B2 (en) | 2021-03-23 | 2023-03-21 | Changxin Memory Technologies, Inc. | Memory detection method and detection apparatus |
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| JP3237127B2 (en) * | 1991-04-19 | 2001-12-10 | 日本電気株式会社 | Dynamic random access memory device |
| US5499211A (en) * | 1995-03-13 | 1996-03-12 | International Business Machines Corporation | Bit-line precharge current limiter for CMOS dynamic memories |
| KR100278926B1 (en) * | 1998-05-25 | 2001-01-15 | 김영환 | Pulley on-chip wafer level burn-in test circuit and its method |
| US6078538A (en) * | 1998-08-20 | 2000-06-20 | Micron Technology, Inc. | Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts |
| US6414889B1 (en) * | 2001-07-03 | 2002-07-02 | United Microelectronics Corp. | Method and apparatus thereof for burn-in testing of a static random access memory |
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| CN106531225A (en) * | 2015-09-09 | 2017-03-22 | 力晶科技股份有限公司 | Wafer level dynamic burn-in test method |
| CN106531225B (en) * | 2015-09-09 | 2019-10-11 | 力晶积成电子制造股份有限公司 | Wafer level dynamic burn-in test method |
| US11609705B2 (en) | 2021-03-23 | 2023-03-21 | Changxin Memory Technologies, Inc. | Memory detection method and detection apparatus |
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