CN106531225A - Wafer level dynamic burn-in test method - Google Patents
Wafer level dynamic burn-in test method Download PDFInfo
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- CN106531225A CN106531225A CN201510606228.XA CN201510606228A CN106531225A CN 106531225 A CN106531225 A CN 106531225A CN 201510606228 A CN201510606228 A CN 201510606228A CN 106531225 A CN106531225 A CN 106531225A
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- 238000010998 test method Methods 0.000 title claims abstract description 27
- 238000012360 testing method Methods 0.000 claims abstract description 84
- 238000005538 encapsulation Methods 0.000 description 8
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- 238000010586 diagram Methods 0.000 description 5
- 239000011469 building brick Substances 0.000 description 4
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- 238000004806 packaging method and process Methods 0.000 description 2
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Abstract
A wafer level dynamic burn-in test method. The enabling state of each word line group is repeatedly switched during the burn-in test period, and the voltage applied to the bit lines is changed when the word line groups are enabled again according to the test pattern data.
Description
Technical field
The present invention relates to a kind of method of testing, more particularly to a kind of wafer scale dynamic burn-in test method.
Background technology
With flourishing for semiconductor technology, the volume of electronic building brick also day by day towards it is light, thin, short,
Little direction is developed.After electronic building brick completes, electronic building brick would generally first receive burn-in testing
(burn-in test), with test out in the environment of a high temperature, high voltage, high current life cycle compared with
Short electronic building brick.Thus, you can improve the reliability (reliability) of product.
General burn-in testing is to complete it in memory assembled (assembled) or encapsulation (packaged)
After carry out, if therefore the component words defective that are detected, it is impossible to laser repairing or group again
Dress (re-assembled), test mode so needs to spend sizable encapsulation and testing cost, and makes
Production capacity is reduced.
In order to further reduce production cost, also it has been proposed that performing the defects detection of correlation before packaging,
Such as wafer scale pre-burning (Wafer Level Burn-In, WLBI) test, the product On-Wafer Measurement stage is made i.e.
Reliability checking can be carried out, so as the test of part still must be performed after packaging, for example dynamic operation is pre-
Burn (dynamic operation burn-in) test, therefore and cannot really be effectively reduced production cost,
That is, burn-in testing of the prior art still has the space of improvement.
The content of the invention
The present invention provides a kind of wafer scale dynamic burn-in test method, encapsulation can be effectively greatly reduced and surveys
Examination cost.
The present invention provides a kind of wafer scale dynamic burn-in test method, and wherein wafer includes multiple storage cores
Piece, each memory chip include multiple word line groups and multiple bit lines, and wherein each word line group includes a plurality of word
Line, the burn-in test method of wafer comprise the following steps.Switch repeatedly each word line group during burn-in testing
Enabled status.It is enabled again time-varying in word line group according to test pattern data during the burn-in testing
Change the voltage applied to bit line.
In one embodiment of this invention, above-mentioned wafer scale dynamic burn-in test method includes, pre- at this
Enable word line group in turn during burning test, wherein when the one of word line group is enabled, remaining word line group quilt
Forbidden energy.
In one embodiment of this invention, above-mentioned bit line is divided into multiple set of bit lines, and the pre-burning of wafer is surveyed
Method for testing includes, during the burn-in testing when word line group is enabled again, it is electric that switching is applied in first
The set of bit lines of pressure, wherein when the one of set of bit lines is applied in first voltage, applies second voltage to remaining
Set of bit lines, wherein first voltage are more than second voltage.
In one embodiment of this invention, above-mentioned set of bit lines is alternately applied in first voltage.
In one embodiment of this invention, above-mentioned storage circuit include positions of odd wordlines group, even wordline group,
Odd bit lines group and even bitlines group, the burn-in test method of wafer include, during the burn-in testing
Enable positions of odd wordlines group and even wordline group in turn, wherein when in enable positions of odd wordlines group with even wordline group
Its for the moment, it is another in forbidden energy positions of odd wordlines group and even wordline group, when word line group is enabled again,
The voltage that switching set of bit lines is applied in.
In one embodiment of this invention, above-mentioned odd bit lines group is alternately applied in even bitlines group
First voltage, wherein when the one in odd bit lines group with the even bitlines group is applied in first voltage,
Apply another in second voltage to odd bit lines group and even bitlines group, wherein first voltage is more than second
Voltage.
In one embodiment of this invention, above-mentioned odd bit lines group is applied in identical with even bitlines group
Voltage.
In one embodiment of this invention, above-mentioned memory chip is for while carry out burn-in testing.
Based on above-mentioned, embodiments of the invention switch the enable shape of each word line group during burn-in testing repeatedly
State, and the voltage that contraposition line applies is converted when each word line group is enabled again according to test pattern data,
The component shorter rapidly to test out life cycle, is effectively greatly reduced encapsulation and testing cost.
It is that the features described above and advantage of the present invention can be become apparent, special embodiment below, and coordinate
Accompanying drawing describes in detail as follows.
Description of the drawings
Fig. 1 is a kind of schematic diagram of the memory chip of the wafer according to one embodiment of the invention.
Fig. 2 is that a kind of flow process of the wafer scale dynamic burn-in test method according to one embodiment of the invention is shown
It is intended to.
Fig. 3 is a kind of flow process of the wafer scale dynamic burn-in test method according to another embodiment of the present invention
Schematic diagram.
Fig. 4 is a kind of flow process of the wafer scale dynamic burn-in test method according to another embodiment of the present invention
Schematic diagram.
Fig. 5 is a kind of flow process of the wafer scale dynamic burn-in test method according to another embodiment of the present invention
Schematic diagram.
Specific embodiment
Fig. 1 is a kind of schematic diagram of the memory chip of the wafer according to one embodiment of the invention, and Fig. 2 is
According to a kind of schematic flow sheet of wafer scale dynamic burn-in test method of one embodiment of the invention, refer to
Fig. 1 and Fig. 2.Wafer (not illustrating) may include multiple memory chips, be ease of explanation, the present embodiment
Only illustrate a memory chip 100 to be illustrated, actually the memory chip in wafer can be same
Shi Jinhang burn-in testings.Memory chip 100 may include presintering test circuit 102 and memory array
104, wherein memory array 104 includes a plurality of wordline WL and multiple bit lines BL, wordline WL with
And the memory cell (not illustrating) that the infall configuration of bit line BL is connected with wordline WL and bit line BL.
Wherein, wordline WL can be divided into multiple word line groups, and presintering test circuit 102 can receive burn-in testing and refer to
Order, and burn-in testing is carried out to memory chip 100 according to burn-in testing instruction.
As shown in Fig. 2 presintering test circuit 102 can switch each word line group during burn-in testing repeatedly
Enabled status (step S202), and be enabled again time-varying in each word line group according to test pattern data
The voltage (step S204) applied to bit line is changed, wherein, the length during burn-in testing may be, for example, 1 point
Clock, 5 minutes or 10 minutes, are so not limited, and test pattern data may be included in burn-in testing and refer to
In order, test pattern data are to the word line group that indicates to be enabled and apply to the electricity of each bar bit line BL
Pressure, to test reliability of the memory cell under different bias conditions.Carrying out static wafer scale in the past
During burn-in testing, it is to carry out by constantly enable word line group and in the way of applying fixed voltage to bit line,
Compared to the burn-in testing mode of prior art, the present embodiment by burn-in testing during switch repeatedly it is each
The enabled status of word line group, and contraposition is converted when each word line group is enabled again according to test pattern data
The mode of the voltage that line applies, interior during identical burn-in testing can repeatedly change write storage unit
Data, to give memory chip 100 different bias conditions, and then test out wafer more quickly
Last function can be carried out after the completion of the shorter memory chip of upper life cycle, and follow-up encapsulation to survey
Examination, dynamic operation pre-burning (the dynamic operation burn-in) test after being not necessary to be packaged again,
Therefore encapsulation and testing cost can be effectively greatly reduced.
For example, Fig. 3 is a kind of wafer scale dynamic burn-in testing side according to another embodiment of the present invention
The schematic flow sheet of method, refer to Fig. 3.In the present embodiment, wordline WL is divided into the 0th wordline
The N+1 word line groups such as group～n-th word line group, bit line BL are then divided into the 0th set of bit lines～the M
The M+1 set of bit lines such as individual set of bit lines, wherein N, M are positive integer.Presintering test circuit 102 can be taken turns
Stream opens this little word line group (that is, this little word line group of enable in turn), wherein when the one of word line group is unlocked
When, remaining word line group is closed (that is, being disabled), and such as in the present embodiment, word line group is from the 0th
Word line group starts alternately to be unlocked, and the word line group being not gated on then is closed.In this enforcement
In example, when word line group is unlocked again, presintering test circuit 102 can alternately be converted and be applied in first
The set of bit lines (that is, converting the set of bit lines being unlocked) of voltage, to convert the bias strip between consecutive storage unit
Part.As shown in figure 3, when each word line group is unlocked for the first time, presintering test circuit 102 applies first
When voltage to the 0th set of bit lines, and each word line group is unlocked for the second time, presintering test circuit 102 changes
For applying first voltage to the 1st set of bit lines, the rest may be inferred, and alternately conversion is applied in first voltage
Set of bit lines.Wherein when its a period of time for applying first voltage to set of bit lines, presintering test circuit 102 is applied simultaneously
Plus second voltage, to remaining set of bit lines (that is, closing remaining set of bit lines), wherein first voltage is electric more than second
Pressure.It should be noted that in during burn-in testing, after all set of bit lines are all opened (also
After being all applied in first voltage), can continue to switch again unlatching, the closing of word line group and set of bit lines
State, to shorten the time of burn-in testing as much as possible, and then is effectively greatly reduced encapsulation and tests into
This.Additionally, the unlatching of word line group and set of bit lines, closing sequence are not limited with the present embodiment, at other
Order that can also be different in embodiment is implementing.
For example, Fig. 4 is a kind of wafer scale dynamic burn-in testing side according to another embodiment of the present invention
The schematic flow sheet of method, refer to Fig. 4.In the present embodiment, wordline WL is divided into positions of odd wordlines group
With even wordline group, bit line BL is also divided into odd bit lines group and even bitlines group.As shown in figure 4,
Presintering test circuit 102 can open positions of odd wordlines group and even wordline group (that is, enable odd number in turn in turn
Word line group and even wordline group), wherein when the one in positions of odd wordlines group with even wordline group is unlocked,
Another in positions of odd wordlines group and even wordline group is closed (that is, being disabled), and word line group again by
During unlatching, the voltage that 102 changeable set of bit lines of presintering test circuit is applied in, wherein each word line group are every
It may be, for example, 50 milliseconds that the secondary time being unlocked and each set of bit lines are applied in the time of voltage every time
(ms), so it is not limited.Specifically, in the present embodiment, presintering test circuit 102 is first opened
Even wordline group simultaneously closes positions of odd wordlines group, while applying first voltage respectively with second voltage to even bit
Line group and odd bit lines group, to open even bitlines group and close odd bit lines group, wherein first voltage is big
In second voltage.Then it is changed to again open positions of odd wordlines group close even wordline group, and by first voltage
Even bitlines group and odd bit lines group are respectively applied to second voltage (that is, to open even bitlines group and close
Close odd bit lines group).Then, presintering test circuit 102 is changed to open even wordline group and close once again
Positions of odd wordlines group, now for being enabled for the second time, presintering test circuit 102 will can switch even wordline group
It is applied in the set of bit lines of first voltage, that is, is changed to apply first voltage to odd bit lines group, and by second
Voltage applies to even bitlines group.Afterwards, presintering test circuit 102 is changed to open positions of odd wordlines group simultaneously again
Even wordline group is closed, now positions of odd wordlines group is to be enabled for the second time, therefore presintering test circuit 102
Switching also can be applied in the set of bit lines of first voltage, that is, be changed to apply first voltage to odd bit lines
Group, and second voltage is applied to even bitlines group.
Similarly, during burn-in testing in, after all set of bit lines are all opened (that is, all by
After applying first voltage), can continue to switch again unlatching, the closed mode of word line group and set of bit lines.
As shown in figure 4, presintering test circuit 102 can be changed to open even wordline group and close positions of odd wordlines group again,
Its follow-up embodiment can be analogized by the above and be learnt, therefore will not be described here.It is noted that
Now presintering test circuit 102 can according to test pattern data determine again apply to even bitlines group with
The voltage of odd bit lines group.In the present embodiment, after all set of bit lines are all opened once, in advance
Burn test circuit 102 when the operation of subsequent cycle is carried out, for applying being made to even bitlines group and odd bits
The voltage of line group is identical when being unlocked with previous even wordline group.Additionally, the present embodiment does not also limit applying
Must be different to even bitlines group and the voltage of odd bit lines group, as shown in figure 4, even bitlines group with it is strange
The state of digit line group simultaneously for being turned on and off, that is, can apply to even bitlines group and odd bit lines group
Voltage can be also first voltage or second voltage simultaneously.
Again for example, Fig. 5 is a kind of wafer scale dynamic burn-in test method according to another embodiment of the present invention
Schematic flow sheet, refer to Fig. 5.In the present embodiment, wordline is divided into into word line group WL00, word
Line group WL01, word line group WL10 and word line group WL11, and bit line is divided into into even bitlines group
VBLPE00, even bitlines group VBLPE01, even bitlines group VBLPE10, odd bit lines group
VBLPO00, odd bit lines group VBLPO01 and odd bit lines group VBLPO10.Wherein word line group
WL00 includes that the 4K article wordline, word line group WL01 include the 4K+1 article wordline, word line group WL10
Include the 4K+3 article wordline including the 4K+2 article wordline, word line group 11.In the present embodiment, even number
Set of bit lines VBLPE00 is divided into the first set of bit lines with odd bit lines group VBLPO01 and is applied in identical
Voltage, even bitlines group VBLPE01, even bitlines group VBLPE10, odd bit lines group VBLPO00
And odd bit lines group VBLPO10 is divided into the second set of bit lines and is applied in identical voltage.
Similarly, in the present embodiment, presintering test circuit 102 can switch word line group in order in turn
The enabled status of WL00～word line group WL11, and to above-mentioned first, second set of bit lines applied voltage,
Wherein, it is enabled (as shading is indicated) in word line group WL00～word line group WL11 for the first time and is opened
When, together with the first set of bit lines (that is, even bitlines group VBLPE00 and odd bit lines group VBLPO01) by
Presintering test circuit 102 applies first voltage (as shading is indicated) and is unlocked, and the second set of bit lines is (also
I.e. even bitlines group VBLPE01, even bitlines group VBLPE10, odd bit lines group VBLPO00 with
And odd bit lines group VBLPO10) second voltage is applied by presintering test circuit 102 together and is closed,
Wherein first voltage is more than second voltage.When being enabled in word line group WL00～word line group WL11 again
When (unlatching), presintering test circuit 102 will apply to the first set of bit lines (that is, even bitlines group VBLPE00
With odd bit lines group VBLPO01) voltage be changed to second voltage (that is, close even bitlines group
VBLPE00 and odd bit lines group VBLPO01), and will apply to the voltage of the second set of bit lines to be changed to the
One voltage (that is, opening the second set of bit lines).Similarly, in during burn-in testing, in all set of bit lines
After being all opened, can continue to switch again unlatching, the closing shape of word line group and above-mentioned two set of bit lines
State.
In sum, embodiments of the invention switch the enable shape of each word line group during burn-in testing repeatedly
State, and the voltage that contraposition line applies is converted when each word line group is enabled again according to test pattern data,
The component shorter rapidly to test out life cycle, is effectively greatly reduced encapsulation and testing cost.
Although the present invention is disclosed as above with embodiment, so which is not limited to the present invention, any ability
Domain those of ordinary skill, without departing from the spirit and scope of the present invention, when can make a little change and repair
Decorations, therefore protection scope of the present invention is defined by claim.
Claims (8)
1. a kind of wafer scale dynamic burn-in test method, the wafer include multiple memory chips, respectively should
Memory chip includes multiple word line groups and multiple bit lines, and wherein respectively the word line group includes a plurality of wordline,
The burn-in test method of the wafer includes：
Switch repeatedly the enabled status of the respectively word line group during a burn-in testing；And
It is right to convert when word line group is enabled again according to test pattern data during the burn-in testing
The voltage that those bit lines apply.
2. wafer scale as claimed in claim 1 dynamic burn-in test method, including：
Those word line groups of enable in turn during the burn-in testing, wherein when the one of those word line groups is caused
During energy, remaining word line group is disabled.
3. wafer scale as claimed in claim 2 dynamic burn-in test method, wherein those bit lines are divided
For multiple set of bit lines, the burn-in test method of the wafer includes：
During the burn-in testing when word line group is enabled again, switching is applied in being somebody's turn to do for a first voltage
A little set of bit lines, wherein when the one of those set of bit lines is applied in the first voltage, apply a second voltage
To remaining set of bit lines, the wherein first voltage is more than the second voltage.
4. wafer scale as claimed in claim 3 dynamic burn-in test method, wherein those set of bit lines wheels
It is applied in the first voltage stream.
5. wafer scale as claimed in claim 1 dynamic burn-in test method, wherein the storage circuit bag
Include a positions of odd wordlines group, an even wordline group, an odd bit lines group and an even bitlines group, the wafer
Burn-in test method include：
The enable positions of odd wordlines group and the even wordline group in turn during the burn-in testing, wherein work as enable
Its a period of time in the positions of odd wordlines group and the even wordline group, the forbidden energy positions of odd wordlines group and the even wordline
It is another in group, when word line group is enabled again, switch the voltage that set of bit lines is applied in.
6. wafer scale as claimed in claim 5 dynamic burn-in test method, wherein the odd bit lines group
The first voltage is applied in alternately with the even bitlines group, wherein when the odd bit lines group and the even bit
When one in line group is applied in the first voltage, apply a second voltage to the odd bit lines group and the idol
Another in digit line group, wherein the first voltage is more than the second voltage.
7. wafer scale as claimed in claim 5 dynamic burn-in test method, wherein the odd bit lines group
Identical voltage is applied in the even bitlines group.
8. wafer scale dynamic burn-in test method as claimed in claim 1, wherein those storage cores
Piece is for while carry out burn-in testing.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104129726 | 2015-09-09 | ||
| TW104129726A TWI550293B (en) | 2015-09-09 | 2015-09-09 | Wafer level dynamic burn-in test method |
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| CN106531225B CN106531225B (en) | 2019-10-11 |
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| KR100223674B1 (en) * | 1996-03-12 | 1999-10-15 | 윤종용 | Apparatus for reducing burn-in testing time and method thereof |
| US6055199A (en) * | 1998-10-21 | 2000-04-25 | Mitsubishi Denki Kabushiki Kaisha | Test circuit for a semiconductor memory device and method for burn-in test |
| TW476068B (en) * | 2000-02-02 | 2002-02-11 | United Microelectronics Corp | Device and method for inspecting the dynamic random access memory during wafer level burn-in process |
| TW200527443A (en) * | 2004-02-09 | 2005-08-16 | Elite Semiconductor Esmt | Memory device and method for burn-in test |
| CN1664959A (en) * | 2004-03-03 | 2005-09-07 | 晶豪科技股份有限公司 | Memory device for pre-burning test and method therefor |
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| KR0127680B1 (en) * | 1987-08-07 | 1998-04-03 | 미다 가쓰시게 | Semiconductor memory device |
| KR100575882B1 (en) * | 2003-11-26 | 2006-05-03 | 주식회사 하이닉스반도체 | A device for generating internal voltages in a burn-in test mode |
| KR100610015B1 (en) * | 2004-09-10 | 2006-08-09 | 삼성전자주식회사 | Circuits for burn-in test in memory device having open bit-line cell structure and method thereof |
| TWI382425B (en) * | 2008-06-24 | 2013-01-11 | United Microelectronics Corp | Test system for identifying defects and method of operating the same |
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2015
- 2015-09-09 TW TW104129726A patent/TWI550293B/en active
- 2015-09-22 CN CN201510606228.XA patent/CN106531225B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100223674B1 (en) * | 1996-03-12 | 1999-10-15 | 윤종용 | Apparatus for reducing burn-in testing time and method thereof |
| US6055199A (en) * | 1998-10-21 | 2000-04-25 | Mitsubishi Denki Kabushiki Kaisha | Test circuit for a semiconductor memory device and method for burn-in test |
| TW476068B (en) * | 2000-02-02 | 2002-02-11 | United Microelectronics Corp | Device and method for inspecting the dynamic random access memory during wafer level burn-in process |
| TW200527443A (en) * | 2004-02-09 | 2005-08-16 | Elite Semiconductor Esmt | Memory device and method for burn-in test |
| CN1664959A (en) * | 2004-03-03 | 2005-09-07 | 晶豪科技股份有限公司 | Memory device for pre-burning test and method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI550293B (en) | 2016-09-21 |
| CN106531225B (en) | 2019-10-11 |
| TW201710695A (en) | 2017-03-16 |
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