CN1664823A - Pseudo ring-free aperture passing method - Google Patents
Pseudo ring-free aperture passing method Download PDFInfo
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- CN1664823A CN1664823A CN 200510031396 CN200510031396A CN1664823A CN 1664823 A CN1664823 A CN 1664823A CN 200510031396 CN200510031396 CN 200510031396 CN 200510031396 A CN200510031396 A CN 200510031396A CN 1664823 A CN1664823 A CN 1664823A
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Abstract
This invention discloses a pseudo-acyclic passing hole method in means of EDA tool to design passing hole, characterized in using spliced definition tie disk namely size of soldering disk function to design the PCB and MCM passing hole in different slice tie disks, if there being wire linked out in some layer, adopting ring tie disk in passing hole definition stage, if not, adopting micro-ring tie disk with the size of tie disk more or less same with that of passing hole. The invention can keep the wiring space away from tie disk area, realize using mature product technology to get high-density PCB and MCM wiring with high-accuracy and narrow-pitch device.
Description
Technical field:
The present invention relates to the method for designing of printed board (PCB) and multi-chip module (MCM), especially have high precision, the high density PCB of thin space (Pitch) chip and the design implementation method of MCM.
Background technology:
Along with the continuous development of integrated circuit technique, chip volume is more and more littler, and chip pin is more and more, and (Pitch) is more and more littler for the pin-pitch of chip and encapsulation, has brought the difficult problem of high density PCB and high density MCM wiring thus.In the face of often running into the high-density wiring problem of high precision, thin space (Pitch) device in the hyundai electronics design, common solution be adopt dwindle live width or spacing, reduce via hole, buried via hole, blind hole and little ring via hole high density such as (also claiming ring-free aperture passing) interconnection (HDI) technology design.These technology and method have not only increased production cost, have increased producting process difficulty simultaneously, have also reduced the rate of manufacturing a finished product.
In PCB and MCM design, utilize the conventional method of electric design automation (EDA) instrument design via hole to be, set the size of wiring layer (the comprising superficial layer) terminal pad of via hole, the size of the disconnected dish in power supply stratum (anti-pad) and the size of surperficial welding resistance dish at first respectively, and then set the boring size of via hole.So just finished the definition of via hole, defined via hole can call in subsequently PCB and MCM wiring (craft or self routing) design at any time.Generally the wiring layer terminal pad of via hole all is the same on each layer as can be seen, and its size does not change.The problem of bringing thus is, more and more littler along with chip and packaging pin spacing (Pitch) utilizes present conventional via hole technology can not finish the high-density wiring design.
Such as, in the printed board design, when containing the ball grid array that solder pad space length is 1mm or littler encapsulation (BGA) device on the plate, via hole adopts via hole aperture and the 0.6mm via hole terminal pad of 0.3mm usually under common process.Under this condition, wiring fan-out (Pin-escape) space below ball grid array (BGA) device between two via holes only stays 0.4mm (solder pad space length 1mm deducts terminal pad size 0.6mm).Therefore, when wire pitch and conductor width all are the horizontal 0.127mm of common process in the printed board design, any one deck all can only pass through a lead between per two adjacent vias in its BGA the inside, can't pass through two-conductor line (0.127mm*5=0.635mm＞0.4mm).When if the pin of BGA device adopts differential signal transmission, the wiring fan-out (Pin-escape) of BGA device need be carried out the parallel routing design in paired mode, and this just causes can't realizing the wires design of differential signal under the common process condition.Often run into the high-density wiring problem of high precision, thin space (Pitch) device in the modern printed board design that Here it is.
The common method that solves the above-specified high density wiring problem at present has three kinds, a kind of method is, employing dwindle PCB routing live width and spacing (as: wire pitch and conductor width all become 0.1mm), reduce the method for via hole (as: the via hole aperture adopts 0.2mm and terminal pad to adopt 0.5mm), like this, wiring space is 0.5mm (solder pad space length 1mm deducts terminal pad size 0.5mm), can be from just in time designing two leads (0.1mm*5=0.5mm) of drawing 0.1mm live width and spacing between per two adjacent vias of BGA.But therefore this method, has increased the production difficulty owing to adopted very little lead live width, wire pitch and lead via hole, has improved cost.
Second method is, adopts the printed board designing technique of buried via hole and blind hole, and this technology realizes the wiring fan-out of BGA device by utilizing buried via hole and blind hole technology, thereby realizes the printed board high-density wiring.But this method is owing to adopted buried via hole and blind hole to carry out BGA wiring fan-out, and the wire interconnects in the printed board needs the process via hole repeatedly to transfer and just can finish.The repeatedly switching of via hole has not only reduced the reliability that the printed board upper conductor interconnects, and also the transmission quality to high speed signal on the lead produces baneful influence.In addition, burying/blind hole production technology and machining production line of printed board needs higher technology and cost to realize.
The third method is, adopts little ring via hole printed board designing technique of (also claiming ring-free aperture passing), and promptly 0.3mm is adopted in the via hole aperture, and its terminal pad also adopts and equals or little pad greater than 0.3mm.Like this, under the situation of not dwindling live width and spacing (as: wire pitch and conductor width still are 0.127mm), also have the wiring space (solder pad space length 1mm deducts terminal pad size 0.3mm) about 0.7mm, can be from just in time designing two leads (0.127mm*5=0.635mm＜0.7mm) between per two adjacent vias of BGA.The problem of bringing when adopting little ring via hole or ring-free aperture passing technology to carry out high density PCB or MCM wiring is: since the size of each layer terminal pad of PCB or MCM also with the big or small basic identical (disk ring of terminal pad＜0.1mm) of via hole, like this, each of PCB or MCM layer terminal pad drill bit (laser) of the manufactured via hole of possibility in process of production destroyed, thereby the terminal pad with connection effect may be removed, therefore, when the terminal pad of via hole has lead to link to each other, to have a strong impact on the connection reliability that terminal pad links to each other with lead, its production cost also can improve greatly simultaneously.
The via hole implementation method of above-mentioned three kinds of methods is, every layer of terminal pad of via hole all is once to design to finish, and has same size, and promptly each layer terminal pad of PCB or MCM is big or small identical.Simultaneously, the size of the size of solder mask pad, the anti-pad in power supply stratum and the size of boring aperture also are once to define to finish, and design suitable mutually size according to the requirement of production technology.The implementation method of little ring via hole or ring-free aperture passing is identical with the implementation method of general via hole, what be that little ring via hole or ring-free aperture passing adopt is the terminal pad that has only little connection disk ring or do not connect disk ring, each layer terminal pad size that is PCB or MCM is identical, and the big or small basically identical of the size of terminal pad and via hole or more bigger.
Above-mentioned three kinds of methods belong to printed board HDI (high density interconnect) technology category, and they are at technology difficulty that has increased PCB Production in varying degrees and production cost.How under the situation that does not increase production cost and technology difficulty, utilize conventional production process, realize having the high density PCB routing of high precision, thin space (Pitch) device, the manufacturability and the reliability that improve printed board become problem demanding prompt solution.
Summary of the invention:
Technical matters to be solved by this invention is that under the situation that does not increase production cost and technology difficulty, the production technology that utilization is ripe realizes having the high density PCB and the MCM wires design of high precision, thin space (Pitch) chip.
Technical scheme of the present invention is: the function of utilizing sub-definition terminal pad (pad) size that the printed board eda software provides, PCB and MCM via hole are defined design respectively at the terminal pad of different layers, finish dodging of wiring space and terminal pad zone, thereby realize having high precision, the high density PCB of thin space (Pitch) chip and the wires design of MCM.
Implementation method of the present invention is: in the via hole definition phase, when certain layer had lead to connect, its corresponding terminal pad definition is adopted the ring terminal pad; And certain layer is not when having lead to connect, and little ring terminal pad is adopted in its corresponding terminal pad definition, the size of this terminal pad and via hole big or small basic identical; In addition, also all designing to adopt for two superficial layer terminal pads of via hole has the ring terminal pad, can guarantee that like this via hole connects the reliability of promptly electroplating, and guarantees the reliability that BGA terminal pad fan-out line is connected with via hole simultaneously.By such flexibility and changeability with because of the different terminal pad designing technique of layer, promptly, the principle of " wired (connecting lead) be big (the ring terminal pad is arranged), wireless (connecting lead) then little (little ring terminal pad) then " is adopted in the design of via hole terminal pad, reach effectively dodging of wiring space and terminal pad zone, thereby be implemented under the situation that does not increase production cost and technology difficulty, utilize ripe production technology, realize having the high density PCB and the MCM wiring of high precision, thin space (Pitch) device.In addition, be the reliability of assurance printed board design and the productibility of printed board, and the present invention's operating and realizability in the printed board eda software, general, under the situation of PCB routing space permission, the size of little ring terminal pad should be slightly larger than the aperture of via hole.
Performing step of the present invention is: at first, according to the pin and the line situation of high-density device, route planning of being correlated with and stack-design, the differential conductor that promptly designs the high-density device pin is to can be from which layer so that how mode connects up; Secondly, in eda software, open the Via Design definition module, and determine the size of via hole aperture and terminal pad (pad) according to the virtual rating of production technology with sub-definition terminal pad (pad) size function; The 3rd, lamination situation according to PCB or MCM wires design, according to the various combination mode that ring line dish and little ring terminal pad are arranged, define the array mode of all possible pseudo ring-free aperture passing, like this, when PCB or MCM wires design, just can be according to the various via holes that ring line dish and the combination of little ring terminal pad are arranged of the demand random call of wiring, make that the wiring space of wiring layer of the little ring terminal pad of via hole correspondence is effectively abdicated, so that this layer can many cloth lead.In addition, because the present invention does not change the method for designing of solder mask pad, the anti-pad in power supply stratum and the boring aperture of via hole, therefore, design for solder mask pad, the anti-pad in power supply stratum and the boring aperture of via hole, still carry out according to original or general design and step, be after each via hole has ring line dish and little ring terminal pad combination definition to finish, design size, the size of the anti-pad in power supply stratum and the size of boring aperture of solder mask pad again according to the requirements definition of production technology.At last, finish in PCB or the MCM wires design design of the pseudo ring-free aperture passing that will use, i.e. one group of via hole that has difference that ring terminal pad and the combination of little ring terminal pad are arranged, and can call at any time according to the demand of wiring.
Adopt the present invention to carry out high density PCB and MCM wires design, and, can reach following technique effect the exploitation of EDA wiring software:
1), can realize the multi-thread fan-out (Pin-escape) under the common process live width condition for high precision device with tiny leg spacing (Pitch).As the BGA device of 1.0mm Pitch, 1517Pin, can realize the two-wire fan-out of 5mil live width/spacing under the conventional production process condition;
2), realize the high-density wiring of PCB or MCM wires design by simple and practical Via Design technology;
3) realize high density PCB and MCM with low production technology (or conventional production process) design, thereby guarantee the quality of production of high density PCB and MCM, improve the rate that manufactures a finished product of high density PCB and MCM;
4) for the EDA producer of exploitation PCB or MCM wiring software, can increase " the line dish is pushed function " in wiring software, the realization of this function will greatly improve the high-density wiring performance of wiring software.The principle of this function is: lead can be pushed the line dish according to the line situation of terminal pad in wiring process, promptly, when certain certain line dish of layer does not connect outlet, this layer wiring lead can be pushed (pad diminishes) to this line dish, when certain certain line dish of layer had the outlet of company, this layer wiring lead can not be pushed (pad immobilizes) to this line dish;
5) also has directive function for low technology, low-density PCB or MCM wires design and via hole definition.
Description of drawings:
The embodiment that Fig. 1 designs for pseudo ring-free aperture passing;
Fig. 2 goes out the synoptic diagram of two-conductor line for 1mm pin-pitch (Pitch);
Fig. 3 is certain layer of local wiring figure of pseudo ring-free aperture passing wires design example.
Embodiment is:
Among Fig. 1, the pin-pitch (Pitch) of the last BGA device of PCB is 1mm, the terminal pad 2 of each layer (comprising that two superficial layers are top coat and bottom surface layer) of PCB via hole, 6,8,9 are defined as 0.6mm (24mil), it is the terminal pad 2 of PCB superficial layer, 9 all are defined as 0.6mm, the terminal pad 6 that needs the outlet layer in the internal signal layer, 8 are defined as 0.6mm (terminal pad that connects disk ring is arranged), and do not need the terminal pad 4 of outlet, 7 are defined as the 0.3302mm (terminal pad 4 that has only small ring, 7), little ring terminal pad 4,7 size should be slightly larger than the aperture 3 of via hole, it is little ring terminal pad 4,7 disk ring 5 is generally less than 0.1mm, and (0.3302mm-0.3mm＜0.1mm), the aperture 3 of via hole is defined as 0.3mm.When the terminal pad of adjacent vias in certain wiring layer of printed board all is the terminal pad of nothing connection disk ring, in wire pitch and conductor width all is under 0.127mm (common process level) situation, just can pass through two-conductor line between two adjacent acyclic terminal pads below the BGA of 1mm encapsulation, thereby realize the high density difference distributing line.The present invention does not increase the technology difficulty and the production cost of production, still adopts conventional production process and production technology, as long as adopt technology definition via hole of the present invention just can finish in printed board EDA process.
Among Fig. 2, the shallow bid of solid black circle representative adjacent vias in certain interior layer, solid box representation signal lead, frame of broken lines is represented spacing, and A represents two spaces between the shallow bid, then A=1mm-0.3302mm=0.6698mm; The space that needs by 2 signal conductors is 0.127mm*5=0.635mm (25mil)＜0.6698mm, so under this condition, differential pair can pass through between two adjacent vias.
Among Fig. 3, little white filled circles represents not have the terminal pad that connects disk ring, and big white filled circles represents that the terminal pad that connects disk ring is arranged, and the white wire segment table shows interconnecting lead.
All provide the function of sub-definition terminal pad (pad) size in present most of PCB and the MCM design software, as the Boardstation of Mentor company, Allegro of Cadence company or the like.The Boardstation that University of Science and Technology for National Defence selects Mentor company for use has successfully used the present invention in the PCB of the milky way high-performance computer of design voluntarily and MCM design, obtained very good effect.
Claims (3)
1. pseudo ring-free aperture passing method, utilize printed board electric design automation eda tool design via hole, it is characterized in that the sub-definition terminal pad that utilizes eda software to provide is the function of pad size size, PCB and MCM via hole are defined design respectively at the terminal pad of different layers, concrete grammar is in the via hole definition phase, when certain layer had lead to connect, its corresponding terminal pad definition is adopted the ring terminal pad; And certain layer is not when having lead to connect, and little ring terminal pad is adopted in its corresponding terminal pad definition, the size of this terminal pad and via hole big or small basic identical; In addition, also all designing to adopt for two superficial layer terminal pads of via hole has the ring terminal pad, connects the reliability of promptly electroplating to guarantee via hole, guarantees the reliability that BGA terminal pad fan-out line is connected with via hole simultaneously; Promptly, the principle of " having that to connect lead then big; i.e. design has the ring terminal pad, do not have that to connect lead then little; promptly design little ring terminal pad " is adopted in the design of via hole terminal pad, reach effectively dodging of wiring space and terminal pad zone, be implemented under the situation that does not increase production cost and technology difficulty, utilize ripe production technology, realize having the high density PCB and the MCM wiring of high precision, thin space (Pitch) device.
2. pseudo ring-free aperture passing method as claimed in claim 1, it is characterized in that being the reliability of assurance printed board design and the productibility of printed board, and the present invention's operating and realizability in the printed board eda software, under the situation of PCB routing space permission, the size of little ring terminal pad should be slightly larger than the aperture of via hole.
3. pseudo ring-free aperture passing method as claimed in claim 1 is characterized in that performing step of the present invention is:
3.1 according to the pin and the line situation of high-density device, route planning of being correlated with and stack-design, the differential conductor that promptly designs the high-density device pin is to can be from which layer so that how mode connects up;
3.2 in having the eda software that the sub-definition terminal pad is the pad size magnitude function, open the Via Design definition module, and determine that according to the virtual rating of production technology via hole aperture and terminal pad are the size of pad;
3.3 lamination situation according to PCB or MCM wires design, according to the various combination mode that ring line dish and little ring terminal pad are arranged, define the array mode of all possible pseudo ring-free aperture passing, like this, when PCB or MCM wires design, just can be according to the various via holes that the combination of ring line dish and little ring terminal pad is arranged of the demand random call of wiring, make that the wiring space of wiring layer of the little ring terminal pad of via hole correspondence is effectively abdicated, so that this layer can many cloth lead;
3.4 because the present invention does not change the method for designing of solder mask pad, the anti-pad in power supply stratum and the boring aperture of via hole, therefore, design for solder mask pad, the anti-pad in power supply stratum and the boring aperture of via hole, still carry out according to original or general design and step, be after each via hole has ring line dish and little ring terminal pad combination definition to finish, design size, the size of the anti-pad in power supply stratum and the size of boring aperture of solder mask pad again according to the requirements definition of production technology;
3.5 finish in PCB or the MCM wires design design of the pseudo ring-free aperture passing that will use, i.e. one group of via hole that has difference that ring terminal pad and the combination of little ring terminal pad are arranged, and can call at any time according to the demand of wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100313967A CN100397402C (en) | 2005-03-30 | 2005-03-30 | Pseudo ring-free aperture passing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100313967A CN100397402C (en) | 2005-03-30 | 2005-03-30 | Pseudo ring-free aperture passing method |
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| CN1664823A true CN1664823A (en) | 2005-09-07 |
| CN100397402C CN100397402C (en) | 2008-06-25 |
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| CNB2005100313967A Expired - Fee Related CN100397402C (en) | 2005-03-30 | 2005-03-30 | Pseudo ring-free aperture passing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103717012A (en) * | 2012-09-28 | 2014-04-09 | 杭州华三通信技术有限公司 | PCB board via impedance control method and structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6728944B2 (en) * | 2001-11-29 | 2004-04-27 | Intenational Business Machines Corporation | Method, system, and computer program product for improving wireability near dense clock nets |
| CN1304996C (en) * | 2004-07-06 | 2007-03-14 | 清华大学 | Rectangular steiner tree method of super large size integrated circuit avoiding barrier |
| CN100347709C (en) * | 2004-07-09 | 2007-11-07 | 清华大学 | Non-linear planning layout method based minimum degree of freedom priority principle |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103717012A (en) * | 2012-09-28 | 2014-04-09 | 杭州华三通信技术有限公司 | PCB board via impedance control method and structure |
| CN103717012B (en) * | 2012-09-28 | 2018-05-18 | 新华三技术有限公司 | A kind of method and structure of PCB board via impedance control |
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| Publication number | Publication date |
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| CN100397402C (en) | 2008-06-25 |
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Granted publication date: 20080625 Termination date: 20140330 |