CN1654420A - Dielectric ceramic materials for chip capacitor and method for preparing same - Google Patents
Dielectric ceramic materials for chip capacitor and method for preparing same Download PDFInfo
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- CN1654420A CN1654420A CN 200510032658 CN200510032658A CN1654420A CN 1654420 A CN1654420 A CN 1654420A CN 200510032658 CN200510032658 CN 200510032658 CN 200510032658 A CN200510032658 A CN 200510032658A CN 1654420 A CN1654420 A CN 1654420A
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Abstract
The present invention provides the preparation process of dielectric ceramic material for low voltage non-linear chip capacitor. The preparation process includes the following steps: 1) preparing glass state material as the third auxiliary component with SrO, CaO, BaO, B2O3 and SiO2 in the molar ratio of 0.5 to 0.5 to 0.2-0.5 to 1.0-2.0 to 0.5-1.0; 2) preparing the main component in the chemical expression of (Ca1-x-ySrxBay)(Ti1-zZrz)O3, where, x is 0.15-0.19, y is 0.14-0.18 and z is 0-0.04; 3) mixing homogeneously the main component, the first auxiliary component (MgO in 0.8-1.5 mol% and MnO2 in 0.1-0.2 mol%), the second auxiliary component (RE oxide Re2O3 in 0.4-1.5 mol%) and the third auxiliary component to obtain the dielectric ceramic material of the present invention. The dielectric ceramic material may be used in producing inner nickel electrode type ceramic capacitor with very low voltage non-linearity of capacitance.
Description
Technical field
The present invention relates to the chip capacitor technology, specifically be a kind of can with base-metal inner-electrode material dielectric ceramic materials for chip capacitor co-sintered, that the electrical capacity non-linear to voltage is very little under reducing atmosphere.
The invention still further relates to the preparation method of described medium ceramic material.
Background technology
For the developing direction of the high-performance, low cost and the miniaturization that adapt to electronic system product, the electrical condenser that requires to be adopted constantly develops to microminiaturization, high capacity, high-performance, high reliability and cost degradation direction.Along with the travelling speed of central processing unit (CPU) (CPU) improves constantly and voltage of supply reduces in succession, the CPU peripheral circuit requires corresponding thereupon raising with the degree of distortion of electrical condenser; In addition, mobile communication equipment, high-fidelity E-consumer series products also need the low distortion electrical condenser of (or being called low distortion factor lowdistortion factor).
The low distortion electrical condenser of Cai Yonging mostly was organic film condenser in the past.Because the dielectric coefficient very low (less than 10) of the nonpolar organic medium that such electrical condenser adopts, so its volume is bigger.The organic film condenser installation volume that realizes chip type reduces to some extent, but because organic film material at high temperature is easy to generate irrecoverable viscous deformation, the Reflow Soldering operation in the electronics packaging technology process is easy to make the chip organic film condenser to destroy, lost efficacy.And, along with popularizing of electronic product environmental requirement, the tin-lead alloy scolder of Cai Yonging progressively was eliminated in the past, replace pure tin or tin-silver solder, because these scolder use temperatures are than tin-lead alloy scolder height, therefore the corresponding raising of Reflow Soldering operation processing temperature, the chip organic film condenser is difficult to adapt to this processing requirement.
Multiple-layer sheet ceramic capacitor (MLCC) has high reliability, big specific volume electric capacity (dielectric coefficient is big), and can adapt to the reflow soldering process of comparatively high temps, so MLCC obtains more and more widely to use.But the MLCC degree of distortion character factor of comparatively large capacity is more much bigger than organic dielectric capacitor usually.The ceramic medium material that comparatively large capacity MLCC adopts mostly is ferroelectric ceramic material, and the ferroelectric ceramic(s) dielectric material has non-linear than the forceful electric power pressure, and promptly the dielectric material coefficient changes along with the variation of strength of electric field.The non-linear to voltage of dielectric coefficient is the major cause that ceramic condenser produces distortion.And along with MLCC develops to the miniaturization high capacity, its deielectric-coating is more and more thinner, and this makes dielectric material applied electric field strength range be in especially than the strong nonlinearity district.The MLCC distortion factor is significantly reduced, must adopt non-ferroelectric media stupalith.
Regular History Frequency thermally stable ceramic media material is non-ferroelectric substance (the NPO characteristic of EIA standard, or the I class C group dielectric material of GB GB/T5596 regulation), the MLCC electrical condenser that adopts such material to make has the low distortion characteristic, but because such dielectric material coefficient lower (10--100) is used for making the frequency applications MLCC of electrical capacity less than 1000pf (1nf) more.And be used for the main scope of condenser capacity that matching circuit requires low nonlinearity, the low distortion factor is 10nf～100nf (0.1 μ f), when adopting Regular History Frequency thermally stable ceramic media material to make the chip capacitor of the low nonlinearity of above containment, the low distortion factor, the effective medium number of plies that needs is a lot, and will adopt expensive precious metal inner electrode usually, so cost of goods manifactured is very high.
Another kind of non-ferroelectricity high-frequency dielectric material at present commonly used--temperature profile be SL (Chinese national standard GB/T5596-1996 stipulate its dielectric coefficient temperature factor be+140～-1000ppm/ degree centigrade), its room temperature dielectric coefficient can reach about 300, adopt the ceramic capacitor of this material manufacturing to have the low distortion factor, but because this material system contains Pb and Bi usually, adopt such material not only bad for environmental protection, and must adopt electrode in the precious metal when making MLCC.
Summary of the invention
The objective of the invention is to overcome the shortcoming that prior art exists, providing a kind of is fit to and the base-metal inner-electrode one reducing atmosphere agglomerating multilayer chip capacitor medium ceramic material that coexists, its dielectric coefficient non-linear to voltage is very little, is fit to make low nonlinearity (low distortion) base-metal inner-electrode chip capacitor.
The present invention also aims to provide the preparation method of described low nonlinearity dielectric ceramic materials for chip capacitor.
The preparation method of dielectric ceramic materials for chip capacitor of the present invention comprises the steps:
The first step: each component of the 3rd minor component is mixed, be heated to fusion after, it is broken and be crushed to particle diameter D50 in the particle≤1.0 μ m with ball milled and promptly make the vitreous state material to adopt the cold quenching method to make glass;
Second step: make principal constituent.Can take two kinds of methods, first method is synthetic respectively earlier CaTiO3, SrTiO
3, BaTiO
3, Ca (Ti
0.8Zr
0.2) O
3. its synthetic method can adopt high temperature solid phase synthesis, liquid phase chemical co-precipitation postheat treatment synthesis method or hydrothermal synthesis method, will synthesize good CaTiO3, SrTiO again
3, BaTiO
3, Ca (Ti
0.8Zr
0.2) O
3Add water for ball milling by principal constituent stoichiometric ratio batching, after mixing or stir, dry back 1100～1300 ℃ of calcinings in air be incubateds 0.5～5 hour, add water for ball milling particle diameter D50≤1.0 μ m to the particle, dry back acquisition principal constituent.Second method is directly to adopt CaCO
3, SrCO
3, BaCO
3, TiO2, ZrO
2, adding water for ball milling by principal constituent stoichiometric ratio batching, after mixing or stir, dry back 1100～1300 ℃ of calcinings in air be incubateds 0.5～5 hour, add water for ball milling particle diameter D50≤1.0 μ m to the particle, dry back acquisition principal constituent.
The 3rd step: the vitreous state mixing of materials that above-mentioned principal constituent, first minor component, second minor component, the first step are obtained evenly promptly obtains the low nonlinearity dielectric ceramic materials for chip capacitor.
The 3rd step, described blending means can adopt dry type to mix method, but also wet mixing after drying method.
To account for total amount ratio minor component seldom and be uniformly dispersed in major ingredient in order to make, above-mentioned first minor component and the second minor component granularity preferably guarantee particle diameter D50 in the particle≤0.6 μ m.
Described principal constituent expression formula: (Ca
1-x-ySr
xBa
y) (Ti
1-zZr
z) O
3, wherein, x=0.15～0.19, y=0.14～0.18, z=0～0.04;
First minor component is MgO, MnO
2Or its presoma;
Second minor component is rare earth oxide Re
2O
3Or its presoma;
The 3rd minor component is by SrCO
3, CaCO
3, BaCO
3, B
2O
3, SiO
2The vitreous state material of making.
Each composition consumption is as follows:
Principal constituent 100mol
The first minor component MgO is 0.8～1.5mol
MnO
2Be 0.1～0.2mol
The second minor component Re
2O
3Be 0.4～1.5mol
The 3rd minor component 1.0～2.0wt% (is 100wt% in main composition), wherein
SrO, CaO, BaO, B
2O
3, SiO
2Mol ratio be:
0.5∶0.5∶0.2～0.5∶1.0～2.0∶0.5～1.0
Described drying means can adopt spray-drying process or other drying meanss, homodisperse, not stratified in each composition drying process in the assurance powder;
Described rare earth oxide Re
2O
3Be to comprise Y
2O
3, Sc
2O
3, Dy
2O
3, Ho
2O
3, Er
2O
3, Tm
2O
3, Yb
2O
3, Lu
2O
3In one or more mixtures.
The presoma of described metal oxide is meant nitrate, carbonate, oxalate or the acetate of this metal.
The low nonlinearity dielectric ceramic materials for chip capacitor that adopts the inventive method to make is suitable for making electrodes in base metal low nonlinearity chip multilayer ceramic capacitor.The process of making chip multilayer ceramic capacitor is as follows:
(1) the low nonlinearity dielectric ceramic materials for chip capacitor and the organic carrier mixing and ball milling that aforesaid method are made are made slurry.
Described organic carrier comprises organic binder bond and solvent, organic binder bond and solvent types are not done qualification, organic binder bond can be selected from polyvinyl butyral acetal, ethyl cellulose or other common adhesive, and solvent can be selected one or more of organic solvents such as toluene, diethylene glycol monobutyl ether, terpinol for use.Described organic carrier also can comprise dispersion agent, softening agent, defoamer etc. as required, and one or more add material.
(2) the above-mentioned slurry of making curtain coating on the film casting machine is made into medium green compact film.
(3) electrode pattern in employing nickel electrode slurry and method for printing screen print on above-mentioned green compact film.
(4) the green compact film lamination behind the electrode in the above-mentioned printing is made laminate blank, institute's lamination number is decided by required electrical capacity requirement, and the most beneath and the most surperficial should each folded on the aforementioned medium green compact film that do not print electrode of one deck at least.
(5) adopt hot pressing and the method that waits static pressure that above-mentioned laminate blank is compressed, discharges interlayer air.
(6) cut apart base substrate.
(7) get rid of tackiness agent.Can be at binder removal under the air atmosphere, also can be under nitrogen atmosphere or hydrogen-nitrogen reducing atmosphere binder removal.The binder removal top temperature can not surpass 300 ℃ in air, otherwise can make the inner electrode oxidation, and in nitrogen or hydrogen nitrogen reducing atmosphere during binder removal top temperature can rise to 500 ℃ or higher.
(8) sintering.Sintering carries out in reducing atmosphere, and sintering temperature is decided on prescription composition and powder granularity, and suitable sintering temperature can be in 1250～1320 scopes.Oxygen partial pressure is 10 in the control sintering atmosphere
-9～10
-12Mpa, reducing atmosphere adopts the hydrogen-nitrogen mixture gas of humidification, and the hydrogen ratio can be controlled in 1～5% scope, can adopt the method for regulating hydrogen ratio and humidifier water temperature to regulate oxygen partial pressure in the sintering atmosphere under guaranteeing the bubble-tight condition of body of heater.
(9) thermal treatment.The porcelain spare that sintering obtains places weak oxide atmosphere oxidizing thermal treatment to improve the dielectric voltage withstand ability of dielectric material.Thermal treatment can be carried out by temperature-fall period in sintering oven, also can carry out behind sintering again.Oxygen partial pressure is controlled at 10 in the heat-treating atmosphere
-7～10
-8Mpa, treatment temp is 1100 ± 30 ℃, soaking time 1～3 hour.Heat treatment step can improve product voltage load aging life-span.
(10) make the first layer end electrode.Adopt dip-coating or the printing way porcelain spare two electrode leads to client coating upper end electrode slurry after sintering and thermal treatment.Terminal electrode paste can adopt copper slurry or silver slurry.Be placed in the nitrogen atmosphere proper temperature after end slurry coating is good and handle, treatment temp decide on the end electrode material behavior, and treatment temp is 750～850 ℃ during the employing copper termination, and treatment temp is 550～850 ℃ when adopting silver-colored end electrode.End electrode is communicated with nickel inner electrode by over-over mode, make each monolithic capacitor parallel connection in the sample.
(11) adopt electro-plating method to make the second layer and the 3rd layer of end electrode.
So far promptly produce nickel inner electrode low nonlinearity multiple-layer sheet ceramic capacitor sample, this sample can be for test, analysis.
The present invention has following advantage with respect to prior art:
The medium ceramic material of the fabrication techniques that the present invention is open is fit to burn altogether with the nickel inner electrode material, makes deielectric-coating thickness less than 10 microns low nonlinearity multi-layer ceramic chip capacitor.
Medium ceramic material dielectric coefficient of the present invention is greater than 250.The condenser capacity non-linear to voltage that adopts this material to make is little, when direct-current biasing is 2.5kV/mm, rate of change of capacitance is less than 0.05%, with dielectric coefficient less than 100, adopt the non-linear to voltage characteristic of the NP0 characteristic laminated ceramic capacitor of electrode in the precious metal approaching.Make the low nonlinearity chip capacitor of a constant volume, its volume can reduce greatly.
Can cooperate when medium ceramic material of the present invention is used to make chip capacitor and adopt nickel inner electrode and copper termination, chip low nonlinearity ceramic condenser production cost is reduced greatly.
The chip capacitor that adopts low nonlinearity dielectric ceramic materials for chip capacitor of the present invention to make is fit to various electronic product field weld technologies, particularly be fit to the leadless environment-friendly weldprocedure, overcome the shortcoming of organic film low nonlinearity chip capacitor aspect welding and thermal distortion.
Description of drawings
Fig. 1: condenser capacity non-linear to voltage test principle figure.
Direct supply is the constant pressure source of Adjustable Output Voltage among the figure; R
1And R
2Be isolation resistance, nominal resistance is chosen as 1～10M Ω; C
1And C
2Be isolation capacitance, optional with non-linear to voltage very little non-polar organic-dielectric capacitor or comparatively large capacity NP0 property slice type ceramic condenser (can adopt a plurality of parallel connections inadequately) as capacity.
Fig. 2: sample of the present invention (sample 101 among the embodiment 1) and contrast sample 1 (commercially available X7R property slice type multilayer ceramic capacitor), and the electrical capacity non-linear to voltage characteristic test correlation curve figure as a result of contrast sample 2 (commercially available NP0 property slice type multilayer ceramic capacitor).
Embodiment
Below by embodiment the present invention is done further concrete description, but embodiments of the present invention are not limited thereto.
Embodiment 1
Principal constituent expression formula (Ca
1-x-ySr
xBa
y) (Ti
1-zZr
z) O
3In, x=0.17, y=0.16, z=0.025.
In first minor component, the MgO addition is 1.0mol (is 100mol in the principal constituent); MnO
2With MnCO
3Form adds, and addition is 0.15mol.
Adopt the synthetic respectively CaTiO of high temperature solid phase synthesis
3, SrTiO
3, BaTiO
3, Ca (Ti
0.8Zr
0.2) O
3. after this according to principal constituent expression formula (Ca
0.67Sr
0.17Ba
0.16) (Ti
0.975Zr
0.025) O
3Add water for ball milling after stoichiometric ratio batching, the mixing, dry back 1250 ℃ of calcinings in air are incubated 3 hours, add water high-speed stirring ball milling 5 hours, dry back acquisition major ingredient.Detect the particle diameter D50 in the major ingredient particle that obtains≤1.0 μ m through laser particle size analyzer.
The making of the 3rd minor component: with SrCO
3, CaCO
3, BaCO
3, B
2O
3, SiO
2Be in molar ratio: 0.5: 0.5: 0.3: weighing in 1.5: 0.8 mixes, place crucible to be heated to 1350 ℃ of fusions after, it is broken to adopt the cold quenching method to make glass, and adopts high speed ball mill to pulverize 5 hours, promptly makes the 3rd added ingredients (vitreous state material).The 3rd minor component add-on in each prescription of present embodiment is 1.5wt%.
In the present embodiment, select Y for use as the rare earth oxide of second minor component
2O
3, Dy
2O
3, Ho
2O
3, Er
2O
3And adjust the addition (seeing Table 1) of these four kinds of oxide compounds.
Above-mentioned major ingredient, first minor component, second minor component and 5 hours after drying of the 3rd minor component mixing and water adding ball milling promptly are made into the media ceramic powder.
Adopt above-mentioned resulting media ceramic powder, and adopt the aforementioned techniques method produce dimensions be 0805 (2 * 1.25mm) low nonlinearity chip capacitor sample, the effective medium number of plies of sample is 20 layers, every layer thickness is about 10 microns.Sintering temperature is 1280 ℃ in the technological process, and oxygen partial pressure is controlled to be 10
-11Mpa is incubated 2 hours; Thermal treatment temp is 1100 ℃, and oxygen partial pressure is controlled to be 10
-6MPa is incubated 2 hours.
The sample of making carries out electrical property as follows and measures.
Electrical capacity, dielectric loss and dielectric coefficient: (test frequency is 1kHz to adopt Agilent-4288 capacitance measuring tester specimen electrical capacity and dielectric loss, test level 500mV), and per sample electrical capacity, effective medium number of plies, dielectric thickness and active electrode planimeter are calculated medium ceramic material dielectric coefficient ε.
Insulating property: the sample two ends apply the insulation resistance of 2.0V/ micron dc voltage measurement sample.
Electrical capacity temperature profile: the temperature test chamber (ESPEC:MC-710P) that sample is placed precision temperature control, measure in-55 ℃～+ 125 ℃ scopes every the sample capacitance value at 10 ℃ of temperature spot places the relative variation (variation of capacitance with temperature) of electrical capacity when calculating relative 25 ℃ of each temperature spot electrical capacity.Because sample test result of the present invention is decline characteristic (negative characteristic---along with temperature rising capacity successively decreases), so the percentage of capacitance variation with temperature when only listing-55 ℃ and+125 ℃ among each embodiment.
The electrical capacity non-linear to voltage is measured: Fig. 1 illustrates test principle figure, when the direct supply no-output, reads the capacitance value that capacitance measuring tester records.Regulate the direct supply output voltage to desirable value, direct supply is through resistor R
1And R
2Give sample C
xCharging makes direct-current biasing of measured capacitance device load, reads the capacitance value that capacitance measuring tester at this moment records.
Because the capacitance value that capacitance measuring tester records is the electrical capacity of A, B point-to-point transmission, and because R
1, direct supply, R
2The alternating-current impedance of current branch under test frequency of forming is much larger than sample C
x, therefore, the electrical capacity that capacitance measuring tester records equals C
1, C
x, C
2Total capacitance after three electrical condensers are connected.According to electrical capacity data that record and known C
1And C
2Electrical capacity utilizes the series capacity calculation formula can calculate the electrical capacity of measured capacitance device sample.
Regulate the direct supply output voltage among Fig. 1, make the sample two ends 0V that loads successively, 5V, 10V, 15V, 20V, the direct-current biasing of 25V obtains corresponding capacitance measuring tester electrical capacity reading, according to known C
1, C
2Accurate observed value calculates the electrical capacity of measured capacitance device sample under the corresponding bias voltage.
Fig. 2 illustrates present embodiment sample 101 and comparative sample 1 (characteristic is the multilayer chip capacitor of X7R) and comparative sample 2 (characteristic is the multilayer chip capacitor of NP0) electrical capacity non-linear to voltage characteristic comparative test result.The result shows that present embodiment sample electrical capacity non-linear to voltage much smaller than comparative sample 1, approaches to contrast the non-linear to voltage characteristic of sample 2.When test comparison sample 1 and contrast sample 2,, determine to apply bias value, make the unit thickness bias voltage identical with test sample of the present invention according to the same batch sample thickness of dielectric layers of microscopical analysis.
Table 2 is listed the electric performance test result that correspondence table 1 is respectively organized sample.
Table 1, medium ceramic material chemical constitution (embodiment 1)
| Sample number into spectrum | Main composition (100mol): (Ca 0.67Sr 0.17Ba 0.16)(Ti 0.975Zr 0.025)O 3The first minor component MgO:1.0mol MnCO 3: 0.15mol the 3rd minor component (vitreous state material): 1.5wt% | Second minor component (mol) | |||
| ????Y 2O 3 | ????Dy 2O 3 | ????Ho 2O 3 | ????Er 2O 3 | ||
| ??101 | ????0.3 | ????0.3 | ????/ | ????/ | |
| ??102 | ????/ | ????/ | ????0.3 | ????0.3 | |
| ??103 | Yttrium trinitrate: 0.4 | ????/ | ????/ | ????/ | |
| ??104 | ????0.75 | ????0.75 | ????/ | ????/ | |
Table 2, sample electrical property (embodiment 1)
| Numbering | Dielectric coefficient ε | Dielectric loss tg δ | Insulation resistance Ω | Rate of change of capacitance Δ C under the direct-current biasing V/C(％) | Variation of capacitance with temperature Δ C T/C(％) | |
| ??(25℃) | ??(25℃) | ??20V/10μm | ????25V/10μm | ????-55℃ | ??125℃ | |
| 101 | ??308 | ??≤0.25％ | ??≥1×10 9 | ????-0.029 | ????10.2 | ??-13.5 |
| 102 | ??302 | ??≤0.25％ | ??≥1×10 9 | ????-0.028 | ????13.5 | ??-14.2 |
| 103 | ??312 | ??≤0.25％ | ??≥1×10 9 | ????-0.03 | ????13.2 | ??-13.8 |
| 104 | ??292 | ??≤0.25％ | ??≥1×10 9 | ????-0.028 | ????12.1 | ??-13.5 |
| Comparative sample 1 * | ??/ | ??1.5％ | ??≥1×10 9 | ????-31.2 | ????-12.0 | ??-14.5 |
| Comparative sample 2 ** | ??/ | ??0.05％ | ??≥1×10 10 | ????-0.008 | In ± 30ppm/ ℃ | |
*Comparative sample 1: characteristic is the multilayer chip capacitor sample of X7R.
*Comparative sample 2: characteristic is the multilayer chip capacitor sample of NP0.
Embodiment 2
Principal constituent is formed identical with embodiment 1, and chemical expression is:
(Ca
0.67Sr
0.17Ba
0.16)(Ti
0.975Zr
0.025)O
3。Adopt CaCO
3, SrCO
3, BaCO
3, TiO2, ZrO
2, by adding water for ball milling after principal constituent stoichiometric ratio batching, the mixing or stirring, dry back 1250 ℃ of calcinings in air are incubated 3 hours, add water high-speed stirring ball milling 5 hours, dry back acquisition principal constituent.
In first minor component, MgO and MnCO
3Addition see Table 3.
As second minor component, add Y
2O
3: 0.4mol%, Dy
2O
3: 0.4mol%.
Make the vitreous state material of forming as four kinds of different chemicals of the 3rd minor component with embodiment 1 same process, its chemical ingredients mol ratio is respectively:
A：SrCO
3∶CaCO
3∶BaCO
3∶B
2O
3∶SiO
2＝0.5∶0.5∶0.5∶1.5∶1.0
B：SrCO
3∶CaCO
3∶BaCO
3∶B
2O
3∶SiO
2＝0.5∶0.5∶0.2∶1.5∶0.8
C：SrCO
3∶CaCO
3∶BaCO
3∶B
2O
3∶SiO
2＝0.5∶0.5∶0.3∶1.0∶0.5
D：SrCO
3∶CaCO
3∶BaCO
3∶B
2O
3∶SiO
2＝0.5∶0.5∶0.3∶2.0∶1.0
Above-mentioned principal constituent, first minor component, second minor component and 5 hours after drying of the 3rd minor component mixing and water adding ball milling promptly are made into the media ceramic powder.Wherein the 3rd minor component numbering is listed in table 3 with addition.
Adopt above-mentioned resulting media ceramic powder, according to producing low nonlinearity chip capacitor sample with embodiment 1 same process method.
Each electrical capacity non-linear to voltage characteristic and other electric performance test of organizing sample the results are shown in table 4.
Table 3, medium ceramic material chemical constitution (embodiment 2)
| Main composition (100mol): (Ca 0.67Sr 0.17Ba 0.16)(Ti 0.975Zr 0.025)O 3Second minor component: Y 2O 3：0.4mol ??????????Dy 2O 3：0.4mol | The first secondary composition (mol) | The 3rd secondary composition (vitreous state material) | |||
| Numbering | ????MgO | ???MnCO 3 | The vitreous state stock number | Addition wt% | |
| 201 | ????1.0 | ????0.15 | ????A | ????1.5 | |
| 202 | ????0.8 | ????0.2 | ????B | ????1.5 | |
| 203 | ????1.5 | ????0.15 | ????C | ????1.5 | |
| 204 | ????1.5 | ????0.1 | ????D | ????1.5 | |
| 205 | ????1.5 | ????0.2 | ????B | ????1.0 | |
| 206 | ????1.5 | ????0.15 | ????B | ????2.0 | |
Table 4, sample electrical property (embodiment 2)
| Numbering | Dielectric coefficient ε | Dielectric loss tg δ | Insulation resistance Ω | Rate of change of capacitance Δ C under the direct-current biasing V/C(％) | Variation of capacitance with temperature Δ C T/C ????(％) | |
| ??(25℃) | ??(25℃) | ??20V/10μm | ????25V/10μm | ????-55℃ | ????125℃ | |
| ??201 | ??308 | ??≤0.25％ | ??≥1×10 9 | ????-0.038 | ????12.8 | ????-14.5 |
| ??202 | ??291 | ??≤0.25％ | ??≥1×10 9 | ????-0.025 | ????12.1 | ????-13.2 |
| ??203 | ??275 | ??≤0.25％ | ??≥1×10 9 | ????-0.030 | ????12.6 | ????-13.8 |
| ??204 | ??296 | ??≤0.25％ | ??≥1×10 9 | ????-0.032 | ????12.5 | ????-13.0 |
| ??205 | ??315 | ??≤0.25％ | ??≥1×10 9 | ????-0.035 | ????14.2 | ????-13.5 |
| ??206 | ??295 | ??≤0.25％ | ??≥1×10 9 | ????-0.042 | ????12.5 | ????-11.8 |
Embodiment 3
As first minor component, the MgO addition is 1.0mol (is 100mol in the principal constituent); MnO
2With MnCO
3Form adds, and addition is 0.15mol.
As second minor component, add Y
2O
3: 0.4mol, Dy
2O
3: 0.4mol.
The 3rd minor component adopts the vitreous state material C among the embodiment 2, and add-on is 1.5wt%.
Adjust principal constituent expression formula (Ca
1-x-ySr
xBa
y) (Ti
1-zZr
z) O
3The value of middle x, y, z.Adopt CaCO
3, SrCO
3, BaCO
3, TiO2, ZrO
2, the stoichiometric ratio batching of determining by the x in the table 5, y, z value, adding water for ball milling after mixing or stir, dry back 1250 ℃ of calcinings in air be incubateds 3 hours, add water high-speed stirring ball milling 5 hours, dry back acquisition 5 principal constituents.
Adopt above-mentioned 5 kinds of principal constituents to add above-mentioned first minor component, second minor component and the 3rd minor component respectively in proportion, add 5 hours after drying of water mixing and ball milling and promptly be made into 5 kinds of media ceramic powders.
Adopt above-mentioned 5 kinds of media ceramic powders, according to producing low nonlinearity chip capacitor sample with embodiment 1 same process method.
Each electrical capacity non-linear to voltage characteristic and other electric performance test of organizing sample the results are shown in table 6.
Table 5, medium ceramic material chemical constitution (embodiment 3)
| Numbering | First minor component: MgO:1.0mol MnCO 3: 0.15mol second minor component: Y 2O 3：0.4mol ????Dy 2O 3: 0.4mol the 3rd minor component: vitreous state material C:1.5wt% | Main composition (100mol): Ca 1-x-ySr xBa y)(Ti 1-zZr z)O 3 | ||
| ????x | ????y | ????z | ||
| ??301 | ????0.17 | ????0.16 | ????0.025 | |
| ??302 | ????0.15 | ????0.18 | ????0.025 | |
| ??303 | ????0.19 | ????0.14 | ????0.025 | |
| ??304 | ????0.17 | ????0.16 | ????0 | |
| ??305 * | ????0.17 | ????0.16 | ????0.05 | |
*Form and exceed the scope of the invention.
Table 6, sample electrical property (embodiment 3)
| Numbering | Dielectric coefficient ε | Dielectric loss tg δ | Insulation resistance Ω | Rate of change of capacitance Δ C under the direct-current biasing V/C ????(％) | Variation of capacitance with temperature Δ C T/C(％) | |
| ??(25℃) | ??(25℃) | ??20V/10μm | ????25V/10μm | ????-55℃ | ????125℃ | |
| ??301 | ??302 | ??≤0.25％ | ??≥1×10 9 | ????-0.033 | ????12.5 | ????-13.8 |
| ??302 | ??324 | ??≤0.25％ | ??≥1×10 9 | ????-0.046 | ????13.5 | ????-14.8 |
| ??303 | ??296 | ??≤0.25％ | ??≥1×10 9 | ????-0.032 | ????13.2 | ????-12.8 |
| ??304 | ??287 | ??≤0.25％ | ??≥1×10 9 | ????-0.028 | ????12.9 | ????-13.5 |
| ??305 | ??352 | ??≤0.25％ | ??≥1×10 9 | ????-0.152 | ????14.2 | ????-15.9 |
Claims (6)
1, a kind of preparation method of dielectric ceramic materials for chip capacitor is characterized in that comprising the steps:
The first step: each component of the 3rd minor component is mixed, be heated to fusion after, it is broken to adopt the cold quenching method to make glass, is crushed to particle diameter D50 in the particle≤1.0 μ m and promptly makes the vitreous state material;
Second step: preparation principal constituent: incite somebody to action synthetic CaTiO3, SrTiO in advance
3, BaTiO
3, Ca (Ti
0.8Zr
0.2) O
3Add water for ball milling by principal constituent stoichiometric ratio batching, after mixing or stir, dry back 1100～1300 ℃ of calcinings in air are incubated 0.5～5 hour, add water for ball milling particle diameter D50≤1.0 μ m to the particle, drying; Perhaps
With CaCO
3, SrCO
3, BaCO
3, TiO2, ZrO
2Add water for ball milling by principal constituent stoichiometric ratio batching, after mixing or stir, dry back 1100～1300 ℃ of calcinings in air are incubated 0.5～5 hour, add water for ball milling particle diameter D50≤1.0 μ m to the particle, drying;
The 3rd step: the vitreous state mixing of materials that principal constituent, first minor component, second minor component, the first step that second step was prepared obtains is even;
Described principal constituent expression formula: (Ca
1-x-ySr
xBa
y) (Ti
1-zZr
z) O
3, wherein, x=0.15～0.19, y=0.14～0.18, z=0～0.04;
First minor component is MgO, MnO
2Or its presoma;
Second minor component is rare earth oxide Re
2O
3Or its presoma;
The 3rd minor component is to adopt SrCO
3, CaCO
3, BaCO
3, B
2O
3, SiO
2The vitreous state material of making;
Each composition usage ratio is as follows:
Principal constituent 100mol
MgO is 0.8～1.5mol in the first minor component MgO or its presoma
MnO
2Or MnO in its presoma
2Be 0.1～0.2mol
The second minor component Re
2O
3Or Re in its presoma
2O
3Be 0.4～1.5mol
The 3rd minor component 1.0～2.0wt% (is 100wt% in main composition), wherein
SrO, CaO, BaO, B
2O
3, SiO
2Mol ratio be:
0.5∶0.5∶0.2～0.5∶1.0～2.0∶0.5～1.0。
2, the preparation method of dielectric ceramic materials for chip capacitor according to claim 1 is characterized in that described rare earth oxide Re
2O
3Be Y
2O
3, Sc
2O
3, Dy
2O
3, Ho
2O
3, Er
2O
3, Tm
2O
3, Yb
2O
3, Lu
2O
3In one or more mixtures.
3, the preparation method of dielectric ceramic materials for chip capacitor according to claim 1 and 2, the presoma that it is characterized in that described metal oxide is meant nitrate, carbonate, oxalate or the acetate of this metal.
4, the preparation method of dielectric ceramic materials for chip capacitor according to claim 3 is characterized in that described blending means of the 3rd step can adopt dry type to mix method, or wet mixing after drying method.
5, the preparation method of dielectric ceramic materials for chip capacitor according to claim 4 is characterized in that the described CaTiO3 of synthetic in advance, SrTiO
3, BaTiO
3, Ca (Ti
0.8Zr
0.2) O
3, its synthetic method adopts high temperature solid phase synthesis, liquid phase chemical co-precipitation postheat treatment synthesis method or hydrothermal synthesis method.
6, the dielectric ceramic materials for chip capacitor of the described method preparation of claim 1.
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