CN1652003A - Method for mfg. film transistor and liquid crystal display - Google Patents
Method for mfg. film transistor and liquid crystal display Download PDFInfo
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- CN1652003A CN1652003A CN 200510056841 CN200510056841A CN1652003A CN 1652003 A CN1652003 A CN 1652003A CN 200510056841 CN200510056841 CN 200510056841 CN 200510056841 A CN200510056841 A CN 200510056841A CN 1652003 A CN1652003 A CN 1652003A
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Abstract
The present invention provides a method for making thin film transistor. Said method includes the following steps: firstly, forming a patterned dielectric layer on baseplate, then forming a metal layer on said baseplate and covering said patterned dielectric layer, flattening said metal layer until the surface of the patterned dielectric layer is exposed, the remained metal layer is grid, then forming gate insulating layer on the patterned dielectric layer and grid, and forming semiconductor layer on the gate insulating layer over the grid, finally forming source and drain on the semiconductor layer.
Description
Technical field
The present invention relates to the method for manufacturing thin film transistor of a kind of Thin Film Transistor-LCD (TFT-LCD) and the manufacture method of LCD, and be particularly related to a kind of utilize mosaic procedure method for fabricating thin film transistor and the manufacture method of LCD.
Background technology
Multimedia society improves rapidly, is indebted to the tremendous progress of semiconductor subassembly or man-machine display device mostly.With regard to display, cathode-ray tube (CRT) (CRT:Cathode Ray Tube) is monopolized monitor market in recent years because of having excellent display quality and economy always.Yet, operate the environment of a plurality of terminating machines or display equipment on the table for the individual, or with the environmental protection and the viewpoint incision of saving the energy, still there are many problems in cathode-ray tube (CRT) for the usability in space and the consumption of the energy.Therefore add that cathode-ray tube (CRT) does not have effective workaround for demand light, thin, short, little and low consumpting power, have that high image quality, space utilization efficient are good, the Thin Film Transistor-LCD of low consumpting power, superiority such as radiationless becomes the main flow in market gradually.
Method of manufacturing thin film transistor is to form a grid (gate) earlier on a substrate in the prior art, then on substrate, deposit an insulation course (insulating layer) and semi-conductor layer in regular turn with cover grid, form source electrode or drain electrode (source/drain) then in the both sides of semiconductor layer respectively, make a thin film transistor (TFT) like this.
Yet, since in the prior art method of manufacturing thin film transistor all be mode with photoetching (photo-lithography) and etching (etching) with metal layer patternization to form grid, source electrode and drain electrode.Like this, the material of metal level need cooperatively interact with etching liquid or etching gas, can carry out etching procedure.Therefore, the prior art major part all is to select the metal with good etching condition for use, and aluminium for example is as the metal level material.Just because of this, on the electrode Material Selection of thin film transistor (TFT), many restrictions just have been subjected to.Especially relative other metal of aluminium has bigger resistance value, and along with the trend that the size of thin film transistor (TFT) is dwindled, the size of metallic resistance value will certainly influence the usefulness of thin film transistor (TFT).
Summary of the invention
The object of the present invention is to provide a kind of method of manufacturing thin film transistor, so that the electrode material of thin film transistor (TFT) has more selectivity.
Another object of the present invention provides a kind of method of manufacturing thin film transistor, to improve the usefulness of thin film transistor (TFT).
Another object of the present invention provides a kind of manufacture method of LCD, to improve the usefulness of LCD.
The invention provides a kind of method of manufacturing thin film transistor, this method comprises: form first pattern dielectric layer on substrate, form the first metal layer then on substrate, and cover first pattern dielectric layer; The first metal layer is carried out a planarisation step, and up to the surface that exposes first pattern dielectric layer, the first metal layer that wherein remains promptly is a grid; On first pattern dielectric layer and grid, form gate insulation layer, and on the gate insulation layer above the grid, form semi-conductor layer; On semiconductor layer, form an one source pole and a drain electrode.
Described planarisation step comprises a chemical-mechanical polishing process.
The material of described the first metal layer is selected from one of them of copper, tungsten, chromium, aluminium and combination thereof.
The method that forms described source electrode and drain electrode is: form second pattern dielectric layer on described gate insulation layer; On second pattern dielectric layer, form second metal level; Second metal level is carried out a planarisation step, expose up to the second patterned dielectric laminar surface, second metal level that wherein remains is exactly source electrode and drain electrode.
Described planarisation step comprises chemical-mechanical polishing process.
The material of described second metal level is selected from one of them of copper, tungsten, chromium, aluminium and combination thereof.
After forming source electrode and drain electrode, also comprise removing second pattern dielectric layer.
Before forming first pattern dielectric layer on the substrate, also be included in and form stress-buffer layer on the substrate.
Described stress-buffer layer is selected from one of them of one silica layer, a silicon nitride layer, a silicon oxynitride layer and combination thereof.
Described semiconductor layer comprises channel layer and ohmic contact layer.
The present invention also provides a kind of method of manufacturing thin film transistor, and this method comprises: at first form grid on substrate, form gate insulation layer then on substrate, to cover described grid; On the gate insulation layer above this grid, form semi-conductor layer, on gate insulation layer, form a pattern dielectric layer then; Form metal level on this pattern dielectric layer, and this metal level is carried out a planarisation step, expose up to the patterned dielectric laminar surface, the metal level that wherein remains is exactly source electrode and drain electrode.
Described planarisation step comprises chemical-mechanical polishing process.
The material of described metal level is selected from one of them of copper, tungsten, chromium, aluminium and combination thereof.
Before forming grid on the substrate, also be included on the described substrate and form stress-buffer layer.
Described stress-buffer layer is selected from one of them of one silica layer, a silicon nitride layer, a silicon oxynitride layer and combination thereof.
Described semiconductor layer comprises channel layer and ohmic contact layer.
The invention provides a kind of manufacture method of LCD, this method comprises: form a thin film transistor array layer on one first substrate, one second substrate is provided then, and form a liquid crystal layer between this first substrate and this second substrate; Wherein, described thin film transistor array layer comprises a plurality of thin film transistor (TFT)s and a plurality of pixel electrode, and each thin film transistor (TFT) comprises a grid, one source pole and a drain electrode, the method that wherein forms grid and/or drain electrode and source electrode is: form a pattern dielectric layer, on pattern dielectric layer, form a metal level then, this metal level is carried out a planarisation step, come out up to the surface of pattern dielectric layer.
Described planarisation step comprises a chemical-mechanical polishing process.
The material of described metal level is selected from one of them of copper, tungsten, chromium, aluminium and combination thereof.
Also comprise a chromatic filter layer on described second substrate.
In the manufacture method of method of manufacturing thin film transistor of the present invention and LCD,, therefore can increase the material selectivity of metal level because of the operation of photoetching and etching in the alternative prior art of employing mosaic procedure.In addition, in the manufacture process of the thin film transistor (TFT) of Thin Film Transistor-LCD, use mosaic procedure, just can adopt the lower metal of resistance value, thereby the usefulness that has improved thin film transistor (TFT) and used the LCD of this thin film transistor (TFT).
Description of drawings
Figure 1A to Fig. 1 D is the manufacturing process sectional view of the thin film transistor (TFT) of one embodiment of the invention in regular turn;
Fig. 2 A to Fig. 2 F is the manufacturing process sectional view of the thin film transistor (TFT) of another embodiment of the present invention in regular turn;
Fig. 3 A to Fig. 3 F is the manufacturing process sectional view of the thin film transistor (TFT) of yet another embodiment of the invention in regular turn;
Fig. 4 is the sectional view of a kind of LCD of one embodiment of the invention.
[primary clustering symbol description]
Substrate 100,200,300; Stress-buffer layer 110,210,310
First pattern dielectric layer 120,220; The first metal layer 130,230
Grid 132,232,320; Gate insulation layer 140,240,330
Semiconductor layer 150,250,340; Channel layer 152,252,342
Ohmic contact layer 154,254,344; Source electrode 162,262,362
Drain electrode 164,264,364; Protective seam 180,280,370
Thin film transistor (TFT) 190,290,390; Second metal level 260
Second pattern dielectric layer 270; Pattern dielectric layer 350
Metal level 360; First substrate 400
Thin film transistor array layer 410; Liquid crystal layer 420
Embodiment
Figure 1A to Fig. 1 D is the manufacturing process sectional view of the thin film transistor (TFT) of one embodiment of the invention in regular turn.At first, shown in Figure 1A, in the present embodiment, on substrate 100, form first pattern dielectric layer 120.In one embodiment, the method that forms first pattern dielectric layer 120 is to deposit a dielectric layer (not illustrating) earlier, utilizes photo-mask process and etching procedure with this dielectric layer patternization then.It should be noted that before forming first pattern dielectric layer 120, also can on substrate 100, form a stress-buffer layer 110 earlier,, avoid the damage of substrate 100 or break with buffering substrate 100 suffered stress in the thin film transistor (TFT) manufacture process.This stress-buffer layer 110 can be one of them of silicon oxide layer, silicon nitride layer, silicon oxynitride layer or its combination.
Shown in Figure 1B, on substrate 100, form the first metal layer 130, and the first metal layer 130 can cover first pattern dielectric layer 120.In one embodiment, these the first metal layer 130 materials can be selected one of them of copper, tungsten, chromium, aluminium and combination thereof for use.
Shown in Fig. 1 C, the first metal layer 130 is carried out a planarisation step, up to the surface that exposes first pattern dielectric layer 120.This planarisation step is a chemical-mechanical polishing process.And the first metal layer 130 that is remained after planarisation step promptly is a grid 132.
Shown in Fig. 1 D, on first pattern dielectric layer 120 and grid 132, form gate insulation layer 140, and on the gate insulation layer above the grid 132 140, form semi-conductor layer 150.In one embodiment, this semiconductor layer 150 comprises channel layer 152 and ohmic contact layer 154.In addition, the material of gate insulation layer 140 can be monox, silicon nitride or silicon oxynitride.The material of channel layer 152 is amorphous silicons.The material of ohmic contact layer 154 is n+ doped amorphous silicons.Then, on semiconductor layer 150, form source electrode 162 and drain 164, thereby form a thin film transistor (TFT) 190.In one embodiment, form source electrode 162 and 164 the method for draining is to utilize photo-mask process and etching procedure to form.After forming source electrode 162, drain electrode 164, can also on thin film transistor (TFT) 190, deposit layer protective layer (not illustrating).
Above-mentioned photo-mask process and the etching procedure of utilizing is to form source electrode 162 and to drain 164 only by being used in the example of the present invention.The present invention does not limit and can only use photo-mask process and etching procedure to form source electrode 162 and to drain 164, can select more suitable operation according to the actual fabrication program, for example can adopt mosaic procedure to make.Below at using mosaic procedure to form source electrode and drain electrode is illustrated for another embodiment.
Fig. 2 A to Fig. 2 F is the manufacturing process sectional view of the thin film transistor (TFT) of another embodiment of the present invention in regular turn.Wherein, the step of Fig. 2 A to Fig. 2 C promptly forms the method for stress-buffer layer 210, first pattern dielectric layer 220, grid 232, gate insulation layer 240 and semiconductor layer 250, and is identical with the step of Figure 1A to Fig. 1 C of the foregoing description, therefore repeats no more.
Shown in Fig. 2 D, on gate insulation layer 240, form second pattern dielectric layer 270, the method that forms second pattern dielectric layer 270 is to deposit a layer insulating (not illustrating) earlier, utilizes photo-mask process and etching procedure with this dielectric layer (not illustrating) patterning then.Formed second pattern dielectric layer 270 is formed on the gate insulation layer 240, but semiconductor layer 250 is not covered fully, and can expose part semiconductor layer 250.
Shown in Fig. 2 E, on second pattern dielectric layer 270, form second metal level 260.The material of second metal level 260 can be identical with the metal level material that adopted when forming grid in the foregoing description, can be to be selected from one of them of copper, tungsten, chromium, aluminium and combination thereof.
Shown in Fig. 2 F, second metal level 260 is carried out a planarisation step, up to the surface that exposes second pattern dielectric layer 270.This planarisation step is a chemical-mechanical polishing process.And after the process planarisation step, second metal level 260 that remains is exactly source electrode 262 and drains 264, thereby forms a thin film transistor (TFT) 290.Forming source electrode 262 and draining after 264, just can optionally second pattern dielectric layer 270 be removed.Then, on thin film transistor (TFT) 290, deposit layer protective layer (not illustrating) again.
Fig. 3 A to Fig. 3 F is the manufacturing process sectional view of the thin film transistor (TFT) of yet another embodiment of the invention in regular turn.At first as shown in Figure 3A, prior to forming grid 320 on the substrate 300, and the method that forms this grid 320 is photo-mask process and etching procedure.It should be noted that before forming grid 320, can on substrate 100, form a stress-buffer layer 310 earlier,, avoid the damage of substrate 300 or break with the stress that buffering substrate 300 is suffered in the thin film transistor (TFT) manufacture process.This stress-buffer layer 310 can be one of them of one silica layer, a silicon nitride layer, a silicon oxynitride layer and combination thereof.
Shown in Fig. 3 B, on substrate 300, form gate insulation layer 330, and cover grid 320.
Shown in Fig. 3 C, on the gate insulation layer above the grid 320 330, form semiconductor layer 340, this semiconductor layer 340 comprises channel layer 342 and ohmic contact layer 344.In the present embodiment, the material of gate insulation layer 330 can be monox, silicon nitride or silicon oxynitride.The material of channel layer 342 can be an amorphous silicon.The material of ohmic contact layer 344 can be the n+ doped amorphous silicon.
Shown in Fig. 3 D, on semiconductor layer 340, form a pattern dielectric layer 350.In one embodiment, the method that forms pattern dielectric layer 350 is to deposit a dielectric layer (not illustrating) earlier, utilizes photo-mask process and etching procedure with this dielectric layer (not illustrating) patterning then, to form pattern dielectric layer 350.Specifically, this pattern dielectric layer 350 can't cover semiconductor layer 340 fully, and only can cover part semiconductor layer 340.
Shown in Fig. 3 E, on this pattern dielectric layer 350, form metal level 360.The material of metal level 360 is to be selected from one of them of copper, tungsten, chromium, aluminium and combination thereof.
Shown in Fig. 3 F, metal level 360 is carried out planarisation step, up to the surface that exposes pattern dielectric layer 350.This planarisation step is a chemical-mechanical polishing process.And through after the planarisation step, to be retained the metal level 360 that gets off be exactly source electrode 362 and drain 364, thereby form a thin film transistor (TFT) 390.Forming source electrode 362 and draining after 364, pattern dielectric layer 350 can also be removed, on thin film transistor (TFT) 390, deposit layer protective layer (not illustrating) then.
Fig. 4 is the sectional view of a kind of LCD of one embodiment of the invention.Please refer to Fig. 4, the manufacture method of LCD 450 of the present invention is: at first form a thin film transistor array layer 410 on one first substrate 400.Wherein thin film transistor array layer 410 comprises a plurality of thin film transistor (TFT)s (not showing) and a plurality of pixel electrodes (not showing).Wherein, the method for the thin film transistor (TFT) of formation thin film transistor array layer 410 is to adopt above-mentioned mosaic procedure to form (as manufacturing process or the manufacturing process of Fig. 2 A to Fig. 2 F or the manufacturing process of Fig. 3 A to Fig. 3 F of Figure 1A to Fig. 1 D).After forming thin film transistor (TFT), define a plurality of pixel electrodes again, and each pixel electrode can electrically connect with corresponding thin film transistor (TFT).
Afterwards, provide one second substrate 440.Also comprise a chromatic filter layer 430 on second substrate 440.Then, between first substrate 400 and second substrate 440, form a liquid crystal layer 420, to constitute a Thin Film Transistor-LCD 450.At this, on second substrate 440, form the method for chromatic filter layer 430, and the method for formation liquid crystal layer 420 can adopt known any suitable mode to carry out between first substrate 400, second substrate 440.
In sum, in the method for manufacturing thin film transistor of Thin Film Transistor-LCD of the present invention, utilize mosaic procedure, therefore when selecting the electrode material of thin film transistor (TFT), more selection can be arranged to form the electrode of thin film transistor (TFT).In addition, if adopt the metal have than low-resistance value, copper for example, when being used as the electrode material of thin film transistor (TFT), the usefulness that can improve thin film transistor (TFT) and use the LCD of this thin film transistor (TFT).
The foregoing description only is used to illustrate the present invention, and is not to be used to limit the present invention.
Claims (20)
1. method of manufacturing thin film transistor is characterized in that comprising:
On a substrate, form one first pattern dielectric layer;
On described substrate, form a first metal layer, and cover described first pattern dielectric layer;
Described the first metal layer is carried out a planarisation step, expose up to the described first patterned dielectric laminar surface, the described the first metal layer that wherein remains is exactly a grid;
On described first pattern dielectric layer and described grid, form a gate insulation layer;
On the described gate insulation layer above the described grid, form semi-conductor layer; And
On this semiconductor layer, form an one source pole and a drain electrode.
2. method of manufacturing thin film transistor as claimed in claim 1 is characterized in that described planarisation step comprises a chemical-mechanical polishing process.
3. method of manufacturing thin film transistor as claimed in claim 1 is characterized in that the material of described the first metal layer is selected from one of them of copper, tungsten, chromium, aluminium and combination thereof.
4. method of manufacturing thin film transistor as claimed in claim 1 is characterized in that, the method that forms described source electrode and described drain electrode comprises:
On described gate insulation layer, form one second pattern dielectric layer;
On described second pattern dielectric layer, form one second metal level; And
This second metal level is carried out a planarisation step, expose up to the described second patterned dielectric laminar surface, described second metal level that wherein remains is exactly described source electrode and drain electrode.
5. method of manufacturing thin film transistor as claimed in claim 4 is characterized in that described planarisation step comprises a chemical-mechanical polishing process.
6. method of manufacturing thin film transistor as claimed in claim 4 is characterized in that the material of described second metal level is selected from one of them of copper, tungsten, chromium, aluminium and combination thereof.
7. method of manufacturing thin film transistor as claimed in claim 4 is characterized in that, after forming described source electrode and described drain electrode, also comprises removing described second pattern dielectric layer.
8. method of manufacturing thin film transistor as claimed in claim 1 is characterized in that, before forming described first pattern dielectric layer on the described substrate, also is included in and forms a stress-buffer layer on this substrate.
9. method of manufacturing thin film transistor as claimed in claim 8 is characterized in that, described stress-buffer layer is selected from one of them of one silica layer, a silicon nitride layer, a silicon oxynitride layer and combination thereof.
10. method of manufacturing thin film transistor as claimed in claim 1 is characterized in that, described semiconductor layer comprises a channel layer and an ohmic contact layer.
11. a method of manufacturing thin film transistor is characterized in that comprising:
On a substrate, form a grid;
On described substrate, form a gate insulation layer, cover this grid;
On the gate insulation layer above this grid, form semi-conductor layer;
On described gate insulation layer, form a pattern dielectric layer;
On this pattern dielectric layer, form a metal level; And
This metal level is carried out a planarisation step, expose up to described patterned dielectric laminar surface, the described metal level that wherein remains is exactly described source electrode and described drain electrode.
12. method of manufacturing thin film transistor as claimed in claim 11 is characterized in that, described planarisation step comprises a chemical-mechanical polishing process.
13. method of manufacturing thin film transistor as claimed in claim 11 is characterized in that, the material of described metal level is selected from one of them of copper, tungsten, chromium, aluminium and combination thereof.
14. method of manufacturing thin film transistor as claimed in claim 11 is characterized in that, before forming described grid on the described substrate, also is included in and forms a stress-buffer layer on the described substrate.
15. method of manufacturing thin film transistor as claimed in claim 14 is characterized in that, described stress-buffer layer is selected from one of them of one silica layer, a silicon nitride layer, a silicon oxynitride layer and combination thereof.
16. method of manufacturing thin film transistor as claimed in claim 11 is characterized in that, described semiconductor layer comprises a channel layer and an ohmic contact layer.
17. the manufacture method of a LCD is characterized in that comprising:
On one first substrate, form a thin film transistor array layer, this thin film transistor array layer comprises a plurality of thin film transistor (TFT)s and a plurality of pixel electrode, and each described thin film transistor (TFT) comprises a grid, one source pole and a drain electrode, and the method that wherein forms described grid and/or described drain electrode and source electrode comprises:
Form a pattern dielectric layer;
On this pattern dielectric layer, form a metal level;
This metal level is carried out a planarisation step, expose up to described patterned dielectric laminar surface;
One second substrate is provided; And
Between described first substrate and described second substrate, form a liquid crystal layer.
18. the manufacture method of LCD as claimed in claim 17 is characterized in that, described planarisation step comprises a chemical-mechanical polishing process.
19. the manufacture method of LCD as claimed in claim 17 is characterized in that, the material of described metal level is selected from one of them of copper, tungsten, chromium, aluminium and combination thereof.
20. the manufacture method of LCD as claimed in claim 17 also comprises a chromatic filter layer on described second substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510056841 CN1652003A (en) | 2005-03-22 | 2005-03-22 | Method for mfg. film transistor and liquid crystal display |
| CNB2005101359417A CN100452325C (en) | 2005-03-22 | 2005-12-29 | Production of thin-film transistor and liquid-crystal display devcie |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510056841 CN1652003A (en) | 2005-03-22 | 2005-03-22 | Method for mfg. film transistor and liquid crystal display |
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| CN1652003A true CN1652003A (en) | 2005-08-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200510056841 Pending CN1652003A (en) | 2005-03-22 | 2005-03-22 | Method for mfg. film transistor and liquid crystal display |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100463191C (en) * | 2006-04-30 | 2009-02-18 | 北京京东方光电科技有限公司 | Flattening active driving TFT matrix structure and method of manufacture |
| CN106876260A (en) * | 2017-03-03 | 2017-06-20 | 惠科股份有限公司 | Gate electrode structure, manufacturing method thereof and display device |
| CN108321148A (en) * | 2017-01-16 | 2018-07-24 | 群创光电股份有限公司 | Metal coating structure and high-frequency device comprising it |
-
2005
- 2005-03-22 CN CN 200510056841 patent/CN1652003A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100463191C (en) * | 2006-04-30 | 2009-02-18 | 北京京东方光电科技有限公司 | Flattening active driving TFT matrix structure and method of manufacture |
| CN108321148A (en) * | 2017-01-16 | 2018-07-24 | 群创光电股份有限公司 | Metal coating structure and high-frequency device comprising it |
| CN106876260A (en) * | 2017-03-03 | 2017-06-20 | 惠科股份有限公司 | Gate electrode structure, manufacturing method thereof and display device |
| WO2018157573A1 (en) * | 2017-03-03 | 2018-09-07 | 惠科股份有限公司 | Gate electrode structure and manufacturing method therefor, and display device |
| US10388678B2 (en) | 2017-03-03 | 2019-08-20 | HKC Corporation Limited | Gate structure, method for manufacturing gate structure, and display device |
| CN106876260B (en) * | 2017-03-03 | 2020-03-27 | 惠科股份有限公司 | Gate electrode structure, manufacturing method thereof and display device |
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