CN1645753A - Accelerating decoder - Google Patents
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- CN1645753A CN1645753A CN 200410095222 CN200410095222A CN1645753A CN 1645753 A CN1645753 A CN 1645753A CN 200410095222 CN200410095222 CN 200410095222 CN 200410095222 A CN200410095222 A CN 200410095222A CN 1645753 A CN1645753 A CN 1645753A
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Abstract
The errors in the result of checking accelerated decode is made at the same time of repeating converse decode. If no error is checked, then the result of decode is outputted. The decode process doesn't go on even though the decode operation is in repeat. Further more when the decoding where is preset decoding time is made, the error numbers checked in the result of decode is monitored. If the checked error numbers is less than a presetting value, then the decode operation is repeated. The one of first and second decoding results outputted by first and second decoders composing the accelerating decoder are selected as proper result that is outputted.
Description
The present invention is to be on March 1st, 1999 applying date, and denomination of invention is divided an application for the 99816223.X patent application of " accelerating decoder ".
Technical field
The present invention relates to a kind of accelerating decoder (turbo decoder), more particularly, relate to a kind of like this accelerating decoder, it uses the result that decoding obtains to received signal to decode, use the decoded result that obtains in succession by the number of times repeat decoding of setting then, and the data behind the output decoder.
Background technology
Adopt error correcting code in multiple systems, these error correcting codes are in order to correct in the received breath or the mistake that contains in the rebuilt information, thereby can correctly decode raw information.For example, when being applied to carrying out mobile communication, FAX (fax) or other data communication, error correcting code wants in those situations of error-free transmission data, and will be from large-capacity storage media (as disk or CD) in those situations of error-free data reconstruction.
In available error correcting code, determined to accept to quicken sign indicating number (turbo code) (seeing USP5,446,747 explanation) as the standard in the next generation mobile communication.Figure 14 is the block diagram that comprises the communication system of a turbo encoder and an accelerating decoder.Numeral 11 is represented turbo encoder, and it provides at data sending terminal, and numeral 12 is represented accelerating decoder, and it provides at data receiver.Numeral 13 representative data transmission paths.Have, it is the transmit information data of N that character u represents length again; Xa, xb, xc represent the data behind the coding that obtains with 11 pairs of information data u codings of turbo encoder; The signal that ya, yb, yc representative are received, they have been subjected to the influence of noise and decay as the result that coded data xa, xb, xc propagate by communication path 13; The decoded result that u ' representative obtains with accelerating decoder 12 couples of the data ya that received, yb, yc decoding.These data item are expressed as follows.Be noted that decoded result u ' comprises " certainty result (result ofdecision) " and " likelihood value (likelihood) ".
Initial data: u={u1, u2, u3 ..., u
N}
Data behind the coding: xa={X
A1, X
A2, X
A3..., X
Ak..., X
AN}
：xb＝{X
b1，X
b2，X
b3，...，X
bk，...，X
bN}
：xc＝{X
c1，X
c2，X
c3，...，X
ck，...，X
cN}
The data that receive: ya={y
A1, y
A2, y
A3..., y
Ak..., y
AN}
：yb＝{y
b1，y
b2，y
b3，...，y
bk，...，y
bN}
：yc＝{y
c1，y
c2，y
c3，...，y
ck，...，y
cN}
Information data u coding that 11 pairs of length of turbo encoder are N and data xa, xb, the xc behind the output encoder.Data xa behind the coding is information data u itself, data xb behind the coding carries out the data that convolution (convolutional) coding obtains with encoder ENC1 to information data u, and the data xc behind the coding be to information data u interweave (interteaving) (π) and with encoder ENC2 to the x as a result that interweaves
a' carry out the data that convolutional encoding obtains.In other words, quickening sign indicating number is that two convolution code combinations obtain.Being noted that interweave output xa ' with encode after the difference of data xa only be its order, so it is not output.
Figure 15 shows the details of turbo encoder 11.Numeral 11a, the identical convolution coder of 11b representative structure (ENC1, ENC2), digital 11c represents interleave unit (π).Convolution coder 11a, 11b are suitable for exporting the orderly convolutional code (recursive systematicconvolutional code) of recurrence, the formation of each is to connect two trigger FF1 and FF2 by mode shown in the figure, and 3 XOR gate EXOR1～EXOR3.Trigger FF1 and FF2 get 4 states (00), (01), (10), (11).If 0 or 1 is input in each of these state exchanges, these states then carry out changing shown in Figure 16, and encoder ENC1 output xa, xb.In Figure 16, the left side indication receives the state before the data input, state after the indication input of right side, the state exchange path of solid line indication when being input as " 0 ", the state exchange path of dotted line indication when being input as " 1 ", and 00,11,10,01 value of indicating output signal xa, xb on the path.For example, if " 0 " is input in the state 0 (00), then be output as 00 and state becomes 0 (00); If " 1 " is input, then be output as 11 and state becomes 1 (10).
Figure 17 is the block diagram of accelerating decoder.Quickening decoding is at first to use ya and yb among received signal ya, yb, the yc to be undertaken by first primary codec device (DEC1) 12a.Primary codec device 12a is a soft output primary codec device, its output decoder result's likelihood value.Next, use this likelihood value (it is the output of the first primary codec device 12a) and yc similarly to decode by second primary codec device (DEC2) 12b.In other words, the second primary codec device 12b also is a soft output primary codec device, its output decoder result's likelihood value.Here yc is the signal of receiving corresponding with xc, and xc interweaves to information data u and the result's coding that interweaves is obtained.Therefore, will be interleaved device (π) 12c from the likelihood value of first primary codec device 12a output before entering the second primary codec device DEC2 interweaves.
The likelihood value output of the second primary codec device 12b is deinterlaced device (deinterleaver) (π
-1) 12d removes and to interweave, and feeds back to the first primary codec device 12a as input then.Have, u ' is decoded data (decoded results) again, it at the deinterleaving result from the second primary codec device 12b provide " 0 ", " 1 " determined value obtains.Repeat above-mentioned decoding behaviour by pre-determined number and can reduce error rate.
Adopt to quicken decoding, just can reduce mistake in the decoded result whenever repeating decoding processing.Yet, there is such situation, be the wrong needed number of repetition eliminated in the decoded result and change because of the factors such as state of communication path.As a result, if data are correctly decoded repeating on a small quantity, accelerating decoder repeats unnecessary decode operation till having carried out set number of operations after this point so.
Have again, adopt accelerating decoder, just can reduce mistake in the decoded result whenever repeating decoding processing.Yet, there is such situation, promptly be not wrong can both being repaired, even having carried out set number of times, decoding processing also still has mistake.On quite big degree, reduced in the wrong situation, if carry out decoding processing again one time, just very likely correct whole mistakes.Utilize traditional accelerating decoder, when having carried out the decoding of set number of times, contain wrong decoded result and in statu quo export, and do not consider above-mentioned possibility.
Have, in traditional accelerating decoder, the first and second primary codec device 12a, 12b carry out first and second decode procedures at the combination of the unlike signal of being received again.Yet these decode operations are strict same.Therefore, have such possibility, promptly primary codec device is used for the first and second two decode procedures.Yet the arrangement in prior art is that two primary codec devices (i.e. the first and second primary codec devices) are used for first and second decode procedures.A large amount of hardware that this causes, with regard to energy resource consumption, this has also caused problem.
As shown in Figure 17, the output of accelerating decoder is that the result who interweaves is removed in the output of the second primary codec device 12b.As a result, if still there is mistake in decoded data, these mistakes can be disengaged the interleaving process randomization.As shown in Figure 18 (a), the speed code unit is very long in many cases, and in these situations, single speed code unit comprises a plurality of block of informations.If the mistake in these situations is disengaged the interleaving process randomization, then these mistakes are diffused in a plurality of block of informations, as shown in Figure 18 (b), error rate on each block of information basis has increased, and, if retransmit control (resend control) in the block of information unit, then the problem of Chan Shenging is to retransmit number of times to increase.
Have again, in next generation mobile communication, institute's information transmitted will be the combination of the information of various character, and depend on transmit the type of data, so in some situation, if Fault Distribution is burst and instantaneous then can be more quite a lot of in decoded data, and in other situations, if Fault Distribution be at random could be more quite a lot of.Yet, adopt traditional accelerating decoder, the Fault Distribution pattern that comprises in the data after the decoding of output can not become on demand burst or at random.
Therefore, an object of the present invention is to arrange like this it, if promptly before the decoding number of repetition reaches set number of times whole error correctings, the result of output decoder and stop decode operation immediately then.
Another object of the present invention is to arrange it like this, promptly when the set number of times of decoding processing executed, do not correct whole mistakes fully, pre-determine under the situation of quantity mistake but still exist, carry out the possibility that decoding processing just can be corrected whole mistakes again if exist, then will not stop decode operation and will carry out once again.
Another purpose of the present invention is to make it may use a primary codec device to be used for the first and second two decode procedures of prior art.
Another object of the present invention is to arrange it like this, and making the mistake that comprises in decoded data produce pattern (pattern) is that burst type produces.
A further object of the present invention is to arrange it like this, make the Fault Distribution pattern that in decoded data, comprises can become on demand burst or at random.
Summary of the invention
In repeat decoding, the mistake of quickening in the decoded result is detected.Even the repeat decoding operation is in process, there is not mistake if detect, then output decoder result, and termination decoding.If adopt this arrangement, then can shorten decode time and can reduce circuit power consumption.
When decode procedure carries out set point number, monitor in decoded result, to detect wrong number of times, be equal to or less than a set point if detect wrong number of times, then carry out decode operation once more.If adopt this arrangement, though still wrong when the decode operation of set point number finishes, if errors number is few, just and might carry out a decoding processing again and can correct whole mistakes, just carry out one time decode operation so in this case again.This makes may be in output decoder result under whole wrong states of all having corrected.
Make originally the one the second decode procedures of carrying out by the first and second primary codec devices carry out by single primary codec device, select the received signal used in each decode procedure according to the sequential of carrying out first and second decode procedures, selected signal is imported in this primary codec device.If adopt this arrangement, then can reduce hardware, thereby also can reduce power consumption.
In the accelerating decoder that two primary codec devices (i.e. the first and second primary codec devices) are arranged, make the order inversion in the order of receiving signal of receiving signal and being input to the second primary codec device that is input to the first primary codec device and the prior art, thereby make the generation error pattern that comprises in the decoded signal become burst type.If adopt this arrangement, then can reduce the error rate on each block of information basis, thereby also can reduce the repeating transmission number of times.
In an accelerating decoder, make first and second decode procedures of carrying out by the first and second primary codec devices originally carry out, and make at first decode procedure and be input to receiving signal and being inverted with respect to prior art of this primary codec device constantly in the two the order of signal of receiving that second decode procedure is input to this primary codec device constantly by single primary codec device.By adopting this arrangement, the generation error pattern that comprises in the signal after defeated decoding can become burst type, and the error rate on each block of information basis can reduce, thereby can reduce the repeating transmission number of times.Can also reduce amount of hardware.
Do such arrangement: one of first and second decoded results that the first and second primary codec devices that constitute accelerating decoder are exported are selected as suitable output, and come out.If adopt this arrangement, then can make as required the generation of Fault Distribution pattern in the decoded data become burst type or at random.For example, if error correction circuit is positioned at downstream (downstream), the generation of Fault Distribution pattern in the decoded data is made at random, and can carry out error correction by this error correction circuit.If can obtain retransmitting the function of the piece of makeing mistakes, then can make the generation of Fault Distribution pattern in the decoded data constitute burst type, thereby can reduce the repeating transmission number of times.
Originally carrying out first and second decode procedures by the first and second primary codec devices and will carry out in the accelerating decoder of these processes by single primary codec device now, select to be input to the received signal combination of this primary codec device in the moment of carrying out first decode procedure, and select to be input to the received signal of this primary codec device in the moment of carrying out second decode procedure, thereby can make as required the generation of Fault Distribution pattern in the decoded data make burst type or at random.In this case, a primary codec device can be used as two primary codec devices, consequently can reduce the scale of circuit.
Description of drawings
Fig. 1 is the first embodiment block diagram according to accelerating decoder of the present invention;
Fig. 2 explanation is to the modification according to first embodiment of accelerating decoder of the present invention;
Fig. 3 is the block diagram of second accelerating decoder of the present invention, has used a common primary decoder in this accelerating decoder;
Fig. 4 is according to the block diagram of the 3rd accelerating decoder of the present invention (this accelerating decoder makes wrong generation become burst type),
Fig. 5 is the diagram that is used to describe the 3rd embodiment;
Fig. 6 is the block diagram according to another accelerating decoder of third embodiment of the invention;
Fig. 7 is the 4th embodiment (selecting that class accelerating decoder of decoded result here) according to accelerating decoder of the present invention;
Fig. 8 is the diagram that is used to describe the generation of Fault Distribution pattern;
Fig. 9 is the diagram that is used to describe the situation of first-selected random error;
Figure 10 is used to describe the diagram of how selecting with the combined information piece;
The real row that Figure 11 display application is selected and made up;
Figure 12 shows the modification (be a kind of like this arrangement, the order that wherein is input to yb, the yc of DEC1 and DEC2 can be inverted) to fourth embodiment of the invention;
Figure 13 shows another modification (be a kind of like this arrangement, wherein use a common primary decoder) to fourth embodiment of the invention;
Figure 14 is the communication system schematic diagram;
Figure 15 is the block diagram of accelerating decoder;
Figure 16 shows the status transition of conventional decoder;
Figure 17 is the block diagram of accelerating decoder; And
Figure 18 is used for describing the speed code unit and the diagram of the Fault Distribution pattern that comprised by traditional accelerating decoder decoded results.
Embodiment
(a) first embodiment
Fig. 1 is the block diagram according to the accelerating decoder of first embodiment of the invention, wherein ya, yb, yc representative by coded data xa, the xb of transmitting terminal output, xc owing to be subjected to the received signal of noise and influence of fading by communication path.Coded data xa is information data u itself, and coded data xb carries out the data that convolutional encoding obtains to information data u, and coded data xc interweaves to information data u with again the result after interweaving being carried out the data that convolutional encoding obtains.
Receiving data storage 51 is signal ya, yb, the yc that the unit storage is all received with the speed code unit, and sensing element 52 was read the data ya, the yb that are received, yc and data are input to the first and second primary codec devices (DEC1, DEC2) 53,54 in the suitable moment from memory.The first and second primary codec devices 53,54 are carried out decode procedure according to well-known MAP (maximum A posterior probability) decoding algorithm, and they are soft decision input/soft decision output (soft-decision-input/soft-decision-output) decoders.
The first primary codec device 53 uses received signal ya, yb to carry out MAP decode operation and output decoder result's likelihood value (this operation representative quicken decoding the first half).Next, the second primary codec device 54 uses the signal yc that received and carries out similar MAP decode operation from the likelihood value of the first primary codec device, 53 outputs, and output decoder result's likelihood value (this operation representative quicken decoding the second half).Because received signal yc is the received signal corresponding with coded data xc, and coded data xc interweaves to information data u and the result coding of interweaving is obtained, so use the likelihood value of 55 pairs first primary codec devices of an interleaver (π), 53 outputs to interweave and the result is input to the second primary codec device 54.Remove interleaver (π
-1) likelihood value of 56 pairs second primary codec device 54 outputs removes and interweave and it is fed back to the first primary codec device 53.This has finished first circulation of accelerating decoder.By at the decode operation that carries out previously by the pre-determined number repetition thereafter, the error rate in the decoded result is reduced.
Read-out controller 61 control sensing elements 52 are read signal ya, yb, the yc that is received from memory 51, and according to its decoding processing sequential (decoding processing timing) these signals are input to the first and second primary codec devices 53,54.Have again, (1) when the signal of interest of receiving has been finished the set point number decode operation, and (2) decoded result no longer contains when wrong even the decoding number of repetition is less than set point number, reading of read-out controller 61 control sensing elements 52 decoded to the signal that the next one is newly received beginning.
Whenever the first and second primary codec devices 53,54 are finished first half-sum, second half of decode operation respectively, repeat counter 62 just increases counting and these countings is input to repetitive controller 63.
Decoding back data storage 65 is alternately stored from the decoding output result of the first primary codec device 53 with from the second decoding output result who removes interleaver 56.Show that the set point number decode operation finishes in case receive the signal DED from repetitive controller 63, perhaps receive the zero error signal ERZ from error detect circuit 64, then o controller 66 outputs have been stored in the decoded result in the data storage 65 of decoding back.
Like this, detect mistake in the decoded result abreast by error detect circuit 64 and decode operation.Even if carried out decoding but still wrong, then the first and second primary codec devices 53,54 carry out their decode operation set point number, just and o controller 66 response decoding end signal DED export its decoded result.Yet, if before the decode operation number of times reaches set point number, just from the decoding fruit, eliminated mistake, o controller 66 output decoder results and repeat to control 63 and stop decode operations then are with response zero error signal ERZ, even the repeat decoding operation is still underway.If adopt this arrangement, then can shorten decode time and reduce circuit power consumption.
(b) modification of first embodiment
To not stop decode operation and output decoder result even when finishing the set point number decoding, eliminate mistake as yet according to the accelerating decoder of first embodiment yet.Yet, there is such situation, promptly when the set point number decode operation finishes,, thereby there is a kind of possibility even still have mistake but number of errors is few, decoding processing institute is wrong all can be repaired if promptly carry out again.Carrying out decode operation and output in this case again, not have wrong decoded result be favourable.For realizing this point, revise shown in Fig. 2 an additional error detection time counter 67 and the threshold value decision package 68 of providing of the arrangement of first embodiment.Whenever detecting one when wrong, error detect circuit 64 is just exported an error detection signal ERR.So, 67 pairs of signal ERR countings of error detection time counter, thus the errors number that detects in the decoded result of set point number decode operation monitored.Threshold value decision package 68 compares detected errors number in the decoded result of threshold value and set point number decode operation, if the error detection number of times is equal to or less than threshold value, then notifies repetitive controller 63.
If the error detection number of times is greater than this threshold value, then repetitive controller 63 stops decode operation and to read-out controller 61 and o controller 66 output decoder end signal DED.As a result, o controller 66 output decoder results, and read-out controller 61 begins to control the signal of reading next new reception.
On the other hand, if the error detection number of times is equal to or less than this threshold value, then repetitive controller 63 does not make decode operation stop, and not to read-out controller 61 and o controller 66 output decoder end signal DED.As a result, decode operation carries out once again.Repetitive controller 63 is to read-out controller and o controller 66 output decoder end signal DED, no matter the error detection number of times is greater than or less than this threshold value then.As a result, o controller 66 output decoder results, and the next new signal that receives is read in read-out controller 61 controls.
If adopt this arrangement, when finishing, the set point number decode operation still has mistake, if but just errors number is few thereby exist and carry out the possibility that decode operation can be corrected whole mistakes again, will carry out one time decode operation more in this case.This makes might be in output decoder result under whole wrong states that all just are being repaired.
(c) second embodiment
Fig. 3 shows an embodiment of accelerating decoder, wherein adopts single primary codec device.
Here a primary codec device 21 is carried out with time-sharing format: (1) uses the decoding processing that received signal Ya, yb and second half hitch of decoding really carry out (decoding processing the first half) by the first primary codec device 53 of Fig. 1, and (2) use the decoding processing that the received signal yc and first half hitch of decoding really carry out (decoding processing the second half) by the second primary codec device 54 of Fig. 1.In other words, the timing of decode operation be divided into and carry out first (the first half) decoding processing first regularly and (the second half) decoding processing of carrying out second second regularly, the first half of decoding processing is regularly carried out first, and the second half regularly the carrying out second of decoding processing.
Carry out decoding processing the first half first regularly constantly, select circuit 22 to select the signal yb that received and with its input primary codec device 21, carry out decoding processing the second half second constantly in real time, select circuit 22 to select the signal yc that received and with its input primary codec device 21.The first half of 23 pairs of decoded results of interleaver interweave and the result are fed back to the input of primary codec device 21, and the second portion of removing 24 pairs of decoded results of interleaver is removed the input that interweaves and the result is fed back to primary codec device 21.Switch 25 and 26 switches, thereby first half-sum, second half point of decoded result is not imported interleaver 23 and removed interleaver 24, and the input side of signal feedback to primary codec device 21.
On overall operation, select circuit 22 regularly to switch to state shown in the practice among the figure to primary codec device 21 input received signal yb and switch 25,26 constantly first.Primary codec device 21 uses the signal ya, the yb that are received to carry out the MAP decode operation, thus output decoder result's likelihood value (this operation representative quicken decoding the first half).23 pairs of likelihood values from primary codec device 21 of interleaver interweave, and the result are fed back to the input of primary codec device 21.Next, when second regularly constantly arrives, select circuit 22 that the signal yc that receives is input to primary codec device 21, and switch 25,26 change over state shown in the dotted line among the figure.
This has just finished the period 1 of quickening decoding.Above-mentioned decode operation is repeated pre-determined number, just reduced the error rate in the decoded result.After decode operation had carried out pre-determined number, the output of releasing interleaver 24 sent out as the decoded result u ' of second timing.
If take this arrangement, the number of primary codec device can be made one, thereby allows to reduce amount of hardware.
(d) the 3rd embodiment
In prior art, as shown in Figure 18 (b), mistake is dispersed in a plurality of block of informations, increased based on the error rate of each block of information, and be that the unit carries out if retransmit control with block of information, then can cause and retransmit number of times and increase.So, in situation about retransmitting, mistake is put together more favourable than the mistake dispersion.By convolutional encoding, the Fault Distribution pattern in the decoded result of primary codec device is a burst type in nature.Utilize this character to make directly the output decoder result and do not insert to interweave or remove and interweave.
The block diagram of Fig. 4 shows the third embodiment of the present invention, and wherein the mistake generation pattern that comprises in the decoded result (decoded data) is rendered as burst type.
The signal ya that 30 pairs of interleavers are received interweaves and the result is imported the first primary codec device 31.31 couples of signal ya, yc that received of the first primary codec device carry out MAP decode operation and output decoder result's likelihood value.The likelihood value releasing of 32 pairs first primary codec devices of releasing interleaver, 31 outputs interweaves and the result is input to the second primary codec device 33.The second primary codec device 33 uses decoded result (likelihood value) that interweaved and the signal yb that receives to carry out the MAP decode operation, and output decoder result (likelihood value) u ', and it is the input of interleaver 30.
In the 3rd embodiment, signal ya, the yb that receives is input to the first primary codec device 31, and the signal ya that receives is input to the second primary codec device 33, from but at first carry out tradition and quicken the second half of decoding processing, carry out the first half of decoding processing then.As a result, the output of the second primary codec device 33 can send as decoded result u ' former state.As previously mentioned, use traditional decode procedure, the Fault Distribution pattern that comprises in the decoded result of a primary codec device is rendered as burst type.So according to the 3rd embodiment, mistake has been concentrated, as shown in Figure 5, the error rate in the block of information unit is lowered, and is reduced thereby retransmit number of times.
(e) to the modification of the 3rd embodiment
In the 3rd embodiment of Fig. 4, the mistake generation pattern that contains in the decoded result that uses the first and second primary codec devices to obtain is rendered as burst type.Yet, allowing the single primary codec device come in the situation of first and second decode procedures that execute script carried out by the first and second primary codec devices, also can make the mistake generation pattern that contains in the decoded result become burst type.Fig. 6 shows this modification to the 3rd embodiment.In this modification, those parts to it the similar character representation identical with the parts of second embodiment shown in Figure 3.
The difference of second embodiment of this modification and Fig. 3 is that (1) provides an interleaver 27 to be used for the signal ya that receives is interweaved and the result is input to primary codec device 21, (2) select circuit 22 the first half first regularly constantly the signal yc that receives be input to primary codec device 21 and the second half second regularly constantly the signal yb that receives is input to primary codec device 21, (3) switch 25,26 first regularly constantly the output of primary codec device 21 is input to releasing interleaver 24 and releasing interweaved after the result feed back to primary codec device 21, regularly constantly the output of primary codec device 21 is input to interleaver 23 and the result after interweaving is fed back to primary codec device 21 second, and (4) directly obtain decoded result u ' from the output of primary codec device 21 rather than from the output of removing interleaver 24.
On overall operation, regularly constantly select circuit 22 that the signal yc that receives is input to primary codec device 21 first, and switch 25,26 switch to state shown in the solid line among the figure.Primary codec device 21 uses the signal ya, the yc that receive to carry out the MAP decode operation, thus output decoder result's likelihood value.The likelihood value releasing of 24 pairs of primary codec devices of releasing interleaver, 21 outputs interweaves and the result is fed back to primary codec device 21.Next, when arriving second timing during moment, select circuit 22 that the signal yb that receive are input to primary codec device 21, and switch 25,26 is changed into state shown in the dotted line among the figure.
By taking this arrangement, at first carry out tradition and quicken the second half of decoding processing in the decoding, and then carry out the first half of decoding processing, even single primary codec device is arranged, but processing mode is similar to the 3rd embodiment.As a result, the output of primary codec device 21 can be sent as decoded result u ' former state, and the Fault Distribution pattern in decoded result can be rendered as burst type.Be noted that decoded result is as the u ' output of second timer time.
Have again, utilize the modification of Fig. 6, can reduce amount of hardware, and can reduce the error rate in the block of information unit, retransmit number of times thereby can reduce.
(f) the 4th embodiment
If can be arranged to the first and second primary codec devices output that can select to constitute accelerating decoder first and second results in the lump with its output, then can make as required the generation of the Fault Distribution pattern that contains in the data of decoding back present burst type or at random.For example, when in the downstream error correction circuit being arranged, the generation of Fault Distribution pattern can be made at random in decoded data, and can carry out error correction by error correction circuit.Can obtain resending in the situation of wrong function, the generation of Fault Distribution pattern can be made burst type in decoded data, retransmits number of times thereby can reduce.
The block diagram of Fig. 7 shows the 4th embodiment, the generation of the Fault Distribution pattern that contains in the wherein decoded data can make burst type or at random.If remove the selection circuit, then the structure of the structure of this accelerating decoder and traditional accelerating decoder is identical.At first use signal ya, the yb that receives, ya and the yb in the middle of the yc to quicken decoding by the first primary codec device (DEC1) 53.Primary codec device 53 is soft output primary codec device and output decoder result (likelihood value).Next, use the likelihood value of the first primary codec device, 53 outputs and the signal yc that receives similarly to decode by the second primary codec device 54.In other words, the second primary codec device 54 also is a soft output primary codec device and output decoder result (likelihood value).The signal yc that receives is the receive signal corresponding with xc, and xc interweaves to information data u and the result coding of interweaving is obtained.Therefore, the likelihood value from 53 outputs of the first primary codec device will be interweaved by interleaver (π) 55 before entering the second primary codec device 54.
The likelihood value of the second primary codec device, 54 outputs is by removing interleaver (π
-1) 56 remove and interweave, feed back to the first primary codec device 53 as input then.Select circuit 57 select the first decoded result A of the first primary codec device, 53 outputs and remove interleaver 56 outputs the second decoded result B the two one of.Because the first decoded result A does not interweave or removes interweaved, the mistake that produced is known distribution pattern and is rendered as burst type, shown in Fig. 8 (a).On the other hand, the second decoded result B obtains removing to interweave from the decoded result of the second primary codec device 54, so the distribution pattern of the error that produces becomes at random.Therefore, by select the first and second decoded result A and B in the lump with its output, in decoded data the generation of Fault Distribution pattern can be rendered as required burst type or at random.
Be noted that owing to interweaving and between the first and second primary codec devices 53 and 54, carry out, so the order of the second primary codec device, 54 dateouts is different from original information data.So the decoded result of the second primary codec device, 54 outputs is disengaged after reverting to original order and interweaves with dateout.On the other hand, because the order of the decoded result of the first primary codec device, 53 outputs is identical with the order of original information data, these data can in statu quo be exported and need not to change it in proper order.
Like this,, can be elected to be decoded data u ' to the output of the output of the first decoded result A or the second decoded result B, thereby make the quality that to improve transfer of data according to the character of the data that are transmitted.
For example, such a case is arranged, wherein further be subjected to the error correction of an independent error correction decoder 200 from the acceleration decoded result of accelerating decoder 100, as shown in Figure 9, just output decoder B as a result at this moment, wherein wrong generation pattern is randomized.If take this arrangement, shown in (a) among Fig. 9, the error bit that contains in the decoded result by accelerating decoder 100 outputs has been disperseed, thereby can be corrected by error correction decoder 200.Shown in (b) among Fig. 9, after correction, can improve error correction efficient.In allowing the situation of random error to a certain degree, for example the data of being transmitted are situations of voice etc., and output decoder B as a result also is suitable.
Have again, if in the speed code unit, contain a plurality of block of informations (as shown in Figure 10), on the basis of each block of information, from the block of information (a) and (b) of two accelerating decoders output, select the error-free information piece and export the combined result (c) of these selected pieces, so output decoder A as a result in this case.Figure 11 shows an example of selecting and making up.The accelerating decoder that numeral 101 representatives provide a base station, the accelerating decoder that 102 representatives provide in another base station, the 103rd, mobile unit, the 104th, the selector combiner that in mobile switch or base station control unit, provides.Selector combiner 104 has place diversity (diversity) function, is used to select fabulous block of information.If mobile unit 103 is positioned at the zone boundary of adjacent base station, receive that then first and second base stations from the signal of mobile unit 103 make signal be subjected to quickening decoding and decoded signal being input to mobile exchange station.Selector combiner 104 in mobile exchange station is selected the inerrancy piece on the basis of each block of information, as shown in Figure 10, and execution is based on the processing of selection and combined result.
The formation of selector combiner 104 comprises: memory 104a, 104b are used to store the decoded result of being sent into by first and second accelerating decoders 101,102, error detect circuit 104c, 104d are used for detecting the mistake of each decoded result, and selector 104e is used for selecting and output error-free information piece according to the error detection result.
(g) to the modification of the 4th embodiment
Figure 12 revises first of the 4th embodiment.Here can change the order of receiving signal yb, yc that is input to the first and second primary codec devices 53,54 by signal selecting circuit 71.In Figure 12, π represents interleaver, π
-1Interleaver, SW representation switch are removed in representative.
For the modification with Figure 12 obtains the effect similar to the 4th embodiment, according to decoding output result's character (promptly according to mistake generation pattern be burst type or at random) directly from the decoded result output (burst type) of the second primary codec device 54 with remove that the use switch switches between the output (at random) after interweaving.
In output decoder result's the situation, all switch SW all piece are changed to than upside (switching to position shown in the solid line) after releasing interweaves.Have, signal selecting circuit 71 is input to the first primary codec device 53 to the signal Yb that receives, the signal yc that receives is input to the second primary codec device 54 again.Interweave because remove at last under these conditions, thus any mistake that in decoded data, stays all be disperse and export as random error.
On the other hand, in the situation of output by its former state generation of primary codec device 54, all switch SW are switched to than downside (switching to position shown in the dotted line).Have, signal selecting circuit is input to the signal yc that receives the first primary codec device 53 and the signal yb that receives is input to the second primary codec device 54 again.Have, the signal ya that receives is input to the first primary codec device 53 after being interleaved again.Under these conditions, before data were imported into the second primary codec device 54, these data were disengaged and interweave so that it reverts to original order.So the output of the second primary codec device 54 can be used as u ' and directly sends.Consequently: if contain wrongly in decoded data, these mistakes are made into the mistake of burst type so.
(h) to other modifications of the 4th embodiment
Figure 13 shows the another kind modification to the 4th embodiment, and wherein identical with the parts of Fig. 3 and Fig. 6 parts are represented with similar reference character.This modification allows to go to carry out the decoding processing that the reason first and second primary codec devices are carried out with single primary codec device 21, allow to use switch between arranging shown in Fig. 3 and Fig. 6 (its signal extraction position difference), to switch, and make and may change the order of receiving signal yb, yc that is input to primary codec device 21, thereby make the mistake that comprises in the decoded result produce pattern be rendered as by rights burst type or at random.
, perhaps can be the signal yc that receives at first from selecting circuit 22 to be input to the data of primary codec device 21 or can being the signal yb that receives.In the input data is under the situation of the signal yb that receives, and used switch SW 1 was switched to than upside when the input data were the signal ya that receives; At the signal yc that receives is that switch SW 1 is switched to than downside under the input data conditions.When repeat decoding, select circuit 22 the input of primary codec device 21 is alternately switched receiving signal yb and receive between the signal yc.Have, be input in the situation of primary codec device 21 at the signal yb that receives, the output of primary codec device 21 is interleaved and by switch SW 2 is switched to than upside the result that interweaves is feedbacked.On the other hand, be input in the situation of primary codec device 21 at the signal yc that receives, the output of primary codec device 21 is disengaged and interweaves, and exports by switch SW 2 is switched to than downside.
Diverter switch SW3 in the following manner: if are the signal yb that receive to the input of primary codec device 21, then switch SW 3 switches to than downside to send this output.If it is wrong that contain this moment in decoded result u ', then mistake becomes the burst type mistake.If the input to primary codec device 21 is the signal yc that receives, then switch SW 3 switches to than upside to send this output.If it is wrong that contain this moment in decoded result u ', then wrong being randomized.
Now overall operation will be described.
In order to make mistake generation pattern in the decoded result be rendered as burst type, each switch is placed in state shown in the solid line among the figure (state shown in Fig. 3).Under these conditions, select circuit 22 regularly constantly the signal yb that receives to be input to primary codec device 21 first.Primary codec device 21 uses the signal ya, the yb that receive to carry out the MAP decode operation, thus output decoder result's likelihood value.The likelihood value of 23 pairs of primary codec devices of interleaver 21 output interweaves and the result is fed back to the input of primary codec device 21.Next, when second regularly constantly arrived, the signal yc that receive are input to primary codec device 21 to selection circuit 22 and switch 25,26 is switched to state shown in the dotted line among the figure.Primary codec device 21 uses the first half (likelihood values) of decoded results and the signal yc that is received to carry out the MAP decode operation, thereby exports the likelihood value of separating true result.Remove interleaver (π
-1) likelihood value of 24 pairs of primary codec device 21 outputs removes and interweave and the result is fed back to primary codec device 21.If first regularly constantly extract decoded result and from 21 outputs of primary codec device at this, then to produce pattern will be burst type to the mistake in these decoded results.
It will be in the randomized situation that mistake in decoded result produces pattern, and each switch is placed in state shown in the dotted line among the figure (state shown in Fig. 6).Under these conditions, regularly constantly select circuit 22 that the signal yc that receives is input to primary codec device 21 first.Primary codec device 21 uses the signal yc that receives signal ya and receive that is interleaved to carry out the MAP decode operation, thus output decoder result's likelihood value.Remove the likelihood value of 24 pairs of primary codec devices of interleaver, 21 outputs and remove the input that interweaves and the result is fed back to primary codec device 21.Next, when second regularly constantly arrived, the signal yb that receive are input to primary codec device 21 to selection circuit 22 and switch 25,26 is switched to position shown in the solid line among the figure.
Like this, even accelerating decoder utilizes single primary codec device, in decoded result the generation of Fault Distribution pattern can make burst type or at random.In this case, a primary codec device can be used as two primary codec devices, consequently can reduce circuit scale.
Like this, according to the present invention, when repeating to decode, carry out quickening the error detection in the decoded result.Do not have mistake if detect, then the output decoder result is still underway even repeat decoding is operated; And then termination decode procedure.As a result, decode time can be shortened and also circuit power consumption can be reduced.
Have again,, be arranged to supervision and in decoded result, detect wrong number of times when having carried out set point number when decoding, be equal to or less than a set point then carry out decode operation again one time if detect wrong number of times according to the present invention.The result, if still there is mistake in the decode operation of set point number when finishing, even so, if but just number of errors is few and existing in and carry out decoding processing again and will correct all wrong possibilities, will carry out decode operation again in the certain situation like this.This makes might be in output decoder result under whole wrong states that have been repaired.
Have again, according to the present invention, be arranged to by single primary codec device and remove to carry out first and second decode procedures of in prior art, carrying out by the first and second primary codec devices, the signal of receiving that uses in each decode procedure is selected constantly according to the timing of first and second decode procedures, and selected signal is imported into the primary codec device.As a result, hardware can be reduced and also therefore power consumption can be reduced.
Have again, according to the present invention, in the accelerating decoder that two primary codec devices (i.e. the first and second primary codec devices) are arranged, be arranged to the order inversion in the order of receiving signal of receiving signal and being input to the second primary codec device that is input to the first primary codec device and the prior art, thereby make the generation error pattern that comprises in the decoded signal become burst type.As a result, can reduce the error rate on each information unit piece basis, thereby also can reduce the repeating transmission number of times.
Have again, according to the present invention, be arranged to by single primary codec device and carry out first and second decode procedures of carrying out by the first and second primary codec devices in the prior art, and be input to receiving signal and being inverted with respect to prior art of this primary codec device constantly in the two the order of signal of receiving that second decode procedure is input to this primary codec device constantly at first decode procedure.As a result, can reduce amount of hardware, can reduce the error rate on each block of information basis, retransmit number of times thereby can reduce.
Have again, according to the present invention, be arranged to suitably the one the second primary codec device outputs of selecting to constitute accelerating decoder first and second decoded results in the lump with its output.As a result, can make as required the generation of Fault Distribution pattern in the decoded data become burst type or at random.Have, the first and second primary codec devices can be made single common primary decoder again, and can make as required the generation of Fault Distribution pattern in the decoded data become burst type or at random.
Claims (16)
1. accelerating decoder, be used to use decoded result to carry out second decoding processing, these decoded results obtain like this: first decoding processing is applied to a signal of receiving and another signal of receiving, use second decoded result and the described signal of receiving to carry out first decoding processing, use first decoded result and the described signal that another is received to carry out second decoding processing, and repeat first and second decoding processing thereafter, this accelerating decoder comprises:
A primary codec device is used to carry out described first and second decoding processing;
Select circuit, be used for according to performed be first or second decoding processing, that selects to stipulate receives signal and is entered into the primary codec device;
Interlaced device is used for first decoded result is interweaved;
Remove interlaced device, be used for second decoded result removed and interweave; And
Switching device shifter is used for via interweave means or releasing interlaced device first and second decoded results being input to the primary codec device.
2. accelerating decoder, be used to receive first data, to encode second data that obtain and of described first data to described first data the 3rd data of coding then that interweave, respectively as signal ya, yb and yc, and use these data of receiving to repeat decoding processing, this accelerating decoder comprises:
The first and second primary codec devices, be used to use decoded result to carry out second decoding processing, this decoded result obtains like this: signal ya, yc and another the signal yb that receives that first decoding processing is applied to stipulate, repeat then and use and two decoded results and describedly receive first decoding processing of signal ya, yc and use first decoded result and described another received second decoding processing of signal yb;
Interleave unit be used for the signal ya and second decoded result received are interweaved, and the result that will interweave is input to the first primary codec device with the signal yc that receives; And
Remove interleave unit, be used for first decoded result removed and interweave, and the result is input to the second primary codec device with the signal yb that receives;
The decoded result here is the output from the described second primary codec device.
3. accelerating decoder, be used to receive first data, to encode second data that obtain and of described first data to described first data the 3rd data of coding then that interweave, respectively as signal ya, yb and yc, and use these data of receiving to repeat decoding processing, this accelerating decoder comprises:
A primary codec device, be used to use decoded result to carry out second decoding processing, this decoded result obtains like this: first decoding processing is applied to a signal of receiving and another signal of receiving, repeats then and use second decoded result and described first decoding processing of signal and use first decoded result and described another received to receive second decoding processing of signal;
Interleave unit is used for the signal ya that the is received result that interweaves and will interweave is input to this primary codec device;
Select circuit, be used for when carrying out first decoding processing, selecting signal yc, when carrying out second decoding processing, select signal yb, and the signal of selecting is input to this primary codec device; And
The result of first decoding processing removed after interweaving, the result of second decoding processing being interweaved and releasing interweaved and interweave after the result be input to the device of this primary codec device.
4. accelerating decoder, its uses the result that the signal decoding of receiving is obtained to decode, and uses the set point number of decoded result repeat decoding that obtains in succession then, and this accelerating decoder comprises:
The first and second primary codec devices, be used to use decoded result to carry out second decoding processing, this decoded result obtains like this: receive the signal that signal and another are received to what first decoding processing was applied to stipulate, repeat then and use second decoded result and describedly receive first decoding processing of signal and use first decoded result and described another to receive second decoding processing of signal;
Select circuit, be used to select and export first and second decoded results of exporting by the described first and second primary codec devices;
Here control after the decoding of final output the character of wrong generation pattern in the data by data after the decoding of selecting to export.
5. accelerating decoder, its uses the result that the signal decoding of receiving is obtained to decode, and uses the set point number of decoded result repeat decoding that obtains in succession then, and this accelerating decoder comprises:
The first and second primary codec devices, be used to use decoded result to carry out second decoding processing, this decoded result obtains like this: first decoding processing is applied to a signal of receiving and another signal of receiving, repeats then and use second decoded result and described first decoding processing of signal and use first decoded result and described another received to receive second decoding processing of signal; And
Select circuit, the combination that is used to select to receive signal is being input to the first primary codec device of carrying out described first decoding processing, and the signal of selecting to receive is to be input to the second primary codec device of carrying out second decoding processing;
Here the signal of receiving that is input to the first and second primary codec devices by switching is controlled the character of wrong generation pattern in the decoded data.
6. accelerating decoder, its uses the result that the signal decoding of receiving is obtained to decode, and uses the set point number of decoded result repeat decoding that obtains in succession then, and this accelerating decoder comprises:
A primary codec device, be used to use decoded result to carry out second decoding processing, this decoded result obtains like this: first decoding processing is applied to a signal of receiving and another signal of receiving, repeats then and use second decoded result and described first decoding processing of signal and use first decoded result and described another received to receive second decoding processing of signal; And
Select circuit, be used for selecting to be input to receiving signal combination and selecting to be input to the signal of receiving of this primary codec device in the moment of carrying out described second decoding processing of this primary codec device in the moment of carrying out described first decoding processing;
Here the signal of receiving that is input to the primary codec device by the moment that switches in first and second decoding processing is controlled the character of wrong generation pattern in the decoded data.
7. accelerating decoder with accelerator module, be used for using first signal set of selecting from the signal of receiving to carry out first decoding processing, and use the secondary signal set of from the signal of receiving, selecting to carry out second decoding processing, this accelerating decoder comprises:
Decoder is used to carry out first and second decoding processing, and the signal that uses the result by first decoding processing that interweaves to obtain is carried out second decoding processing; And
Controller is used to control decoder, thereby carries out first decoding processing earlier, carries out second decoding processing again.
8. accelerating decoder with accelerator module, be used for using first signal set of selecting from the signal of receiving to carry out first decoding processing, and use the secondary signal set of from the signal of receiving, selecting to carry out second decoding processing, this accelerating decoder comprises:
Decoder is used to carry out first and second decoding processing, and the signal that uses the result by first decoding processing that interweaves to obtain is carried out second decoding processing; And
Output line is used to export the signal that deinterleaves and obtain by the result to second decoding processing, as the decoded result of described accelerating decoder.
9. accelerating decoder with accelerator module, be used for using first signal set of selecting from the signal of receiving to carry out first decoding processing, and use the secondary signal set of from the signal of receiving, selecting to carry out second decoding processing, this accelerating decoder comprises:
Decoder is used to carry out first and second decoding processing, and the signal that uses the result by first decoding processing that deinterleaves to obtain is carried out second decoding processing; And
Output device is used for directly exporting the result of described decoder decoding processing, and need not to relate to interleaving treatment or the processing that deinterleaves.
10. accelerating decoder with accelerator module, be used for using first signal set of selecting from the signal of receiving to carry out first decoding processing, and use the secondary signal set of from the signal of receiving, selecting to carry out second decoding processing, this accelerating decoder comprises:
Selector is used for selecting and exporting any one of first and second decoding process result.
11. according to the accelerating decoder of claim 10,
Wherein the signal that obtains in the result who uses by first decoding processing that interweaves is carried out under the situation of second decoding processing, the signal that described selector is selected and the result of output by second decoding processing that deinterleaves obtains is as the decoding output of described accelerating decoder.
12. accelerating decoder according to claim 10, wherein the signal that obtains in the result who uses by first decoding processing that interweaves is carried out under the situation of second decoding processing, the result of first decoding processing is selected and directly exported to described selector, and need not to relate to interleaving treatment or the processing that deinterleaves.
13. accelerating decoder with accelerator module, be used for using first signal set of selecting from the signal of receiving to carry out first decoding processing, and use the secondary signal set of from the signal of receiving, selecting to carry out second decoding processing, this accelerating decoder comprises:
Controller, be used between first order and second order, changing the order of first decoding processing and second decoding processing, wherein in described first order, carry out first decoding processing earlier, carry out second decoding processing again, in described second order, carry out second decoding processing earlier, carry out first decoding processing again.
14. accelerating decoder with accelerator module, be used for using first signal set of selecting from the signal of receiving to carry out first decoding processing, and use the secondary signal set of from the signal of receiving, selecting to carry out second decoding processing, this accelerating decoder comprises:
Decoder is used to carry out first and second decoding processing; And
Controller, be used between first order and second order, changing the order of first decoding processing and second decoding processing, wherein in described first order, carry out first decoding processing earlier, carry out second decoding processing again, in described second order, carry out second decoding processing earlier, carry out first decoding processing again.
15. accelerating decoder with accelerator module, be used for using first signal set of selecting from the signal of receiving to carry out first decoding processing, and use the secondary signal set of from the signal of receiving, selecting to carry out second decoding processing, this accelerating decoder comprises:
Decoder is used to carry out first and second decoding processing; And
Controller is used for exporting selectively of result of described first and second decoding processing, as the output of described accelerating decoder.
16. accelerating decoder with accelerator module, be used for using first signal set of selecting from the signal of receiving to carry out first decoding processing, and use the secondary signal set of from the signal of receiving, selecting to carry out second decoding processing, this accelerating decoder comprises:
Controller, be used to control decoding processing, thereby when accelerating decoder was carried out decoding processing to each unit of the speed code unit that is made of a plurality of block of informations, the signal that uses the result by described first decoding processing that deinterleaves to obtain was carried out second decoding processing.
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| CN 200410095222 CN1645753B (en) | 1999-03-01 | 1999-03-01 | Accelerating decoder |
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| CN 200410095222 CN1645753B (en) | 1999-03-01 | 1999-03-01 | Accelerating decoder |
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| CNB99816223XA Division CN100452659C (en) | 1999-03-01 | 1999-03-01 | Turbo-decoding device |
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| US5345472A (en) * | 1993-08-02 | 1994-09-06 | Motorola, Inc. | Method and apparatus for receiving and decoding communication signals in a CDMA receiver |
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