CN1645708A - Active electric filter by mixed harmonic detection - Google Patents
Active electric filter by mixed harmonic detection Download PDFInfo
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- CN1645708A CN1645708A CNA2005100489818A CN200510048981A CN1645708A CN 1645708 A CN1645708 A CN 1645708A CN A2005100489818 A CNA2005100489818 A CN A2005100489818A CN 200510048981 A CN200510048981 A CN 200510048981A CN 1645708 A CN1645708 A CN 1645708A
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- Y02E40/20—Active power filtering [APF]
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Abstract
The invention consists of main circuit of active power filter, and mixed type harmonic-testing circuit. The mixed type harmonic-testing circuit integrates advantages of analog and digital control that can either avoid error of digital sampling to signal containing high frequency component, or simplify DSP to extract the fundamental component of load circuit, so that the time delay introduced by digital control is limited in fundamental frequency. At the above bases, through algorithm for fundamental wave based synchronous rotating coordinates, the phase compensation strategy is introduced, which solves the problem of time delay caused by digital control.
Description
Technical field
The present invention relates to a kind of electric harmonic filter, further relate to a kind of Active Power Filter-APF that adopts mixed harmonic to detect.
Background technology
The mains by harmonics problem has caused that people extensively pay attention to, and harmonic standard has separately been formulated in many countries and area.China has also passed through " quality of power supply utility network harmonic wave " (GB/T-14594-93) in 1993, in order to the harmonic pollution of restriction electric power system and power consumption equipment.Development along with power electronic technology, active power filter is as the power electronic equipment of a kind of dynamic inhibition harmonic wave and compensating reactive power, can harmonic wave and the idle of variation that big or small and frequency all change be compensated, can effectively remedy the deficiency of traditional passive filter, be a kind of up-and-coming harmonic suppression apparatus, and stepped into the practicability stage.Wherein, shunt active power filter is the most basic form, and has obtained to use the most widely.
Active Power Filter-APF comprises main circuit and harmonics detection circuit two parts, and wherein main circuit comprises the Current Control link, drives link, 3-phase power converter and inductance.Influence the factor of active filter compensation precision, depend primarily on harmonic wave detection, Current Control and main circuit parameter design etc.Wherein, high accuracy, real-time harmonic detecting method and realization thereof will directly affect compensation performance.Traditional Active Power Filter-APF harmonics detection circuit is all realized by analogue device, needs a plurality of multipliers, the hardware cost height; And be subject to temperature and float influence with environmental change, exist that precision is low, defective such as poor anti-interference and circuit complexity.
In recent years, detect and be controlled at based on the harmonic wave of digital signal processor (DSP), microcontroller (MCU) and programmable logic device realizations such as (PLD) and be subjected to more welcome in the real system.Realize comparing with traditional analog, digital controlly overcome its intrinsic problem, be easy to realize advanced control, and reduced circuit cost, easily realize mass product production.Yet although the digital control technology real-time improves constantly, its intrinsic time delay has caused the error of important steps such as harmonic wave detection.Numerically controlled each link, mainly comprise pre-filtering, analog to digital conversion (A/D), based on the harmonic wave of ad hoc approach detect the digital algorithm operation, at last again through digital to analogy conversion (D/A) etc., these links will cause detected harmonic signal exist one time of delay Δ T.
In addition importantly, contain higher frequency content in the detected nonlinear load electric current, its frequency spectrum is abundant, and its harmonic components of real-time detection of digitlization harmonic wave detection system has been proposed challenge.Put into practice verified: this system exists than mistake, and one of them principal element is exactly that the delay of the sampled signal of load current and distortion are directly reflected in the harmonic wave testing result, and is especially very obvious in the reflection at load current mutation process place.
Obviously,, will inevitably cause the error of harmonic wave detection, and then influence the compensation performance of whole Active Power Filter-APF system owing to measure and time delay that factor such as numerical calculation causes.In addition, choosing with word length effect etc. of sample frequency also affects computational accuracy.
In order to improve the digital control time delay influence that brings, general employing speed is processor chips or adopt the design of processor chip (as many DSP) faster, by strengthening data sampling and processing speed, with this digital control delayed impact that weakens, obtain the further raising of harmonic wave accuracy of detection.Use in the business-like abroad active filter product of these measures.But these methods have been brought design complexity and defect of high cost, have caused obstacle for the further popularization of Active Power Filter-APF, particularly at home application.
Summary of the invention
At defective or the deficiency that prior art exists, purpose of the present invention aims to provide the Active Power Filter-APF that low, simple in structure, the practical employing mixed harmonic of a kind of price detects, and detects can realize high accuracy, real-time harmonic wave.
The Active Power Filter-APF that employing mixed harmonic of the present invention detects has main circuit and harmonics detection circuit two parts, and main circuit comprises the Current Control link, drives link, 3-phase power converter and inductance, it is characterized in that harmonics detection circuit comprises:
-current sensor is used for measuring in real time the nonlinear load electric current, its input termination load current, and output divides two the tunnel, and the input with signal conditioning circuit and analog adder links to each other respectively;
-signal conditioning circuit is used for the HF noise signal of filtering current sensor output current signal, and changes bipolar signal into unipolar signal;
-sample/hold circuit is used for the unipolarity three-phase current signal of signal conditioning circuit output is carried out the level maintenance at one time, exports synchronous threephase load current signal, and its input links to each other with the output of signal conditioning circuit;
-DSP chip, execution is based on the synchronously rotating reference frame algorithm of phase compensation, extract the fundamental positive sequence in the load current, an A/D end of convert of this chip links to each other with the output of sample/hold circuit, another A/D conversion termination voltage control regulated quantity;
-phase locking frequency multiplying circuit, be used for the zero crossing of line voltage is detected, form square-wave pulse signal, simultaneously with square-wave pulse signal N frequency multiplication, form the double frequency pulse signal, the square-wave pulse signal of formation all links to each other with the CAP mouth of DSP chip with the double frequency pulse signal;
-digital/analog converter is used for the fundamental positive sequence of threephase load electric current is converted to the unipolarity analog signal, and its input is connected with the digital quantity output of DSP chip;
-level shifting circuit, the unipolarity analog signal conversion that is used for digital/analog converter output is the positive sequential signal of ambipolar threephase load current first harmonics, its input is connected with the output of digital/analog converter;
-analog adder, two input connects the output of level shifting circuit and current sensor respectively, and input signal is subtracted each other, and the harmonic component that obtains in the nonlinear load electric current is defeated by main circuit.
The present invention has following characteristics:
1) by means of the combination of analog-and digital-realization, improved the signal flow of harmonic wave in detecting, avoided transmission to the digital sampled signal of the load current that contains high fdrequency component, effectively reduced distorted signals and error propagation;
2) changed original DSP function and be extracted as the fundametal compoment extraction by the harmonic wave numeral, be easy to guarantee that first-harmonic extracts precision on the one hand, make numerically controlled delayed impact only be confined to fundametal compoment on the other hand, thereby created prerequisite for further implementing the time delay equalization strategy;
3) on the basis of hybrid architecture, by being extracted, the first-harmonic based on synchronous rotating frame carries out the digit phase compensation, successfully solved time delay, guaranteed the extracted with high accuracy of fundametal compoment.
4) the phase locking frequency multiplying circuit can carry out real-time tracking to the line voltage frequency by to the obtaining of electric network voltage phase information, and has guaranteed that DSP carries out based on the first-harmonic extraction algorithm of synchronous coordinate system and the realization of the synchronous and phase compensation of line voltage; Frequency-doubled signal has then guaranteed N point equal interval sampling and the calculating to the nonlinear load electric current in the cycle of single line voltage.
Description of drawings
Fig. 1 is the Active Power Filter-APF theory diagram that employing mixed harmonic of the present invention detects;
Fig. 2 is a kind of physical circuit example of mixed harmonic testing circuit;
Fig. 3 is the synchronous rotating frame first-harmonic extraction algorithm flow chart based on phase compensation of the present invention;
Fig. 4 is the current on line side oscillogram after the Active Power Filter-APF of employing prior art compensates;
Fig. 5 is the current on line side oscillogram that adopts after Active Power Filter-APF of the present invention compensates.
Embodiment
With reference to Fig. 1, the Active Power Filter-APF that employing mixed harmonic of the present invention detects, have main circuit 1 and harmonics detection circuit 2 two parts, main circuit 1 comprises Current Control link 11, drive link 12,3-phase power converter 13 and the inductance 14 that is connected on AC side, harmonics detection circuit 2 is the mixed harmonic testing circuit, and it comprises: current sensor 3, signal conditioning circuit 4, sample/hold circuit 5, DSP chip (hereinafter to be referred as dsp processor) 6, phase locking frequency multiplying circuit 7, digital/analog converter (hereinafter to be referred as D/A converter) 8, level shifting circuit 9 and analog adder 10.
The nonlinear load current signal i that current sensor 3 is measured in real time
La, i
Lb, i
Lc, the one tunnel directly delivers to signal conditioning circuit 4, and analog adder 10 is then directly delivered on another road; Signal conditioning circuit 4 is used for filtering current sensor 3 output current signal i
La, i
Lb, i
LcIn HF noise signal, and change bipolar signal into unipolar signal i
La', i
Lb', i
Lc' be defeated by sample/hold circuit 5, by sample/hold circuit 5 this three-phase current signal being carried out level at one time keeps, what obtain to guarantee to sample is synchronous threephase load current signal, the output of sample/hold circuit 5 links to each other with an A/D conversion input of dsp processor 6, and another A/D conversion input of dsp processor 6 then is used for the regulated quantity Δ i of Active Power Filter-APF DC voltage control
dConnection; Dsp processor 6 utilizes built-in analog/digital converter, with the threephase load current signal and the voltage-regulation amount Δ i of input
dBe converted to digital quantity.The synchronously rotating reference frame algorithm that dsp processor 6 is carried out based on phase compensation extracts the fundamental positive sequence in the load current; This algorithm not only extracts the precision height, and can realize that the extraction of this sinusoidal fundamental wave component do not have time-delay.This fundamental positive sequence is input to D/A converter 8, is converted to unipolarity analog signal i by D/A converter 8
Af', i
Bf', i
Cf'; Then pass through level shifting circuit 9 with unipolarity analog signal i
Af', i
Bf', i
Cf' be converted to the positive sequential signal i of ambipolar threephase load current first harmonics
Af, i
Bf, i
CfAnd input analog adder 10, will be by analog adder 10 from two signals of level shifting circuit 9 and current sensor 3, i.e. three-phase positive sequence of fundamental frequency i
Af, i
Bf, i
CfWith corresponding threephase load current signal i
La, i
Lb, i
LcSubtract each other, obtain three-phase offset current instruction i
Ca *, i
Cb *, i
Cc *Be defeated by main circuit 1, wherein mainly comprise the harmonic component in the load current,, also may comprise fundamental reactive component and asymmetrical component etc. according to the load characteristic difference.Phase locking frequency multiplying circuit 7 is with line voltage e
aThe zero crossing of detection signal detect, form square-wave pulse signal T
1, simultaneously with T
1Signal N frequency multiplication forms pulse signal T
NThese two pulse signals all link to each other with the CAP mouth of dsp processor 6, are used to control the operation of dsp processor.
It is that hardware is simple that the digitlization harmonic wave detects biggest advantage, and algorithm is flexible, but the shortcoming that life period postpones and the realization precision is limit by resource.Compare with Digital Implementation, simulation realizes that maximum advantage is that speed is exceedingly fast, and does not have time delay substantially; And the transmission to high-frequency signal is easy to handle.The analog/digital hybrid type harmonic wave detection system that the present invention proposes has at first changed the function of DSP, multiple-harmonic extraction by high frequency changes the fundamental positive sequence of only extracting in the load current (containing the direct voltage controlled quentity controlled variable) into, frequency is single, feasible requirement to digital sample reduces greatly, and is easy to realize that the high accuracy first-harmonic extracts; Secondly,, realize other signals the error that this system can avoid all-digital signal that the sampling that contains the load current that enriches high fdrequency component is introduced because transmitting by hardware.Obviously, this mode can have been given play to the advantage separately of numeral and simulation control, thereby will effectively reduce the time delay and the error of each signal transmission/extraction, has improved the harmonic wave accuracy of detection; Because the function of DSP is only extracted for the fundametal compoment (containing the direct voltage controlled quentity controlled variable) in the load current, that is to say digital control introducing the time delay influence only be fundametal compoment.The influence of time delay is confined to single fundamental frequency signal, and just implementing time delay equalization targetedly for next step has created prerequisite for this.
Fig. 2 is a kind of instantiation of the harmonics detection circuit among the present invention.In the illustrated example, each the phase signals modulate circuit in the signal conditioning circuit 4 constitutes by frequency overlapped-resistable filter, level shift circuit and amplitude limiter circuit.With A is example mutually, and wherein frequency overlapped-resistable filter is made up of with corresponding resistive element RA1, RA2 and capacity cell CA1, CA2 the integrated computing amplification of half sheet chip U1A, is used for A phase load current detection signal i
La, i
Lb, i
LcIn high-frequency noise reject, to satisfy the undistorted sampling of inhibit signal under limited sample frequency; Level shift circuit amplifies chip U1B by the integrated computing of half sheet and corresponding resistive element RA3, RA4, R5 and R6 constitute, and changes current detection signal into unipolar signal i by bipolarity
La', i
Lb', i
Lc'; Amplitude limiter circuit is made of two Schottky diode DA1 and DA2, be used for making the incoming level of current detection signal be clamped on+5V and zero level between, to guarantee the work safety of the analog/digital converter spare that dsp processor is built-in.Here, the integrated computing amplification of half sheet of said frequency overlapped-resistable filter U1A and level shift circuit chip U1B can adopt chip LF412.B is identical mutually with A with the course of work with C signal conditioning circuit formation mutually mutually.A phase sampler/holding circuit is made of a slice integrated chip U4 and auxiliary capacity cell CM1, CM2; Accordingly, B phase sampler/holding circuit then is made of a slice integrated chip U5 and auxiliary capacitor element CM3, CM4, and C phase sampler/holding circuit is made of a slice integrated chip U6 and auxiliary capacitor element CM5, CM6.Wherein, all available LF398 of chip U4, U5 and U6., after keeping, handles by analog/digital conversion passage ADC2, ADC11 and ADC3 input dsp processor respectively again sampling hold circuit through the threephase load current signal behind the signal condition.
Phase locking frequency multiplying circuit 7 is to be made of zero cross detection circuit, shaping circuit, phase-locked loop and 1/N frequency dividing circuit.Wherein zero cross detection circuit is made of the integrated computing amplification chip U14A of half sheet and relevant detection transformer TP1, diode element DP1, DP2 and resistive element RP1, RP2, RP3.Shaping circuit U15A is the inverter CD40106 of band application schmitt trigger function, and except shaping feature, it has certain anti-interference capability.The low pass filter that phase-locked loop constitutes by phase-locked loop chip U16 (available CD4046) and by resistance R P8, capacitor C P1 and resistance R P6, RP7 and the capacitor C P2 of definite phase-locked loop centre frequency form; Capacitor C P3 and resistive element RP9 that the 1/N frequency dividing circuit increases progressively the counter chip U17 (available CD4040) of work by a slice and is used for counter reset form.The detection signal of line voltage obtains its positive and negative zero crossing through the zero passage testing circuit, and forming the corresponding duty ratio with enough steepness and width by shaping circuit is 0.5 square-wave pulse signal T
1T
1One tunnel CAP3 mouth of directly exporting to dsp processor 6 is captured, and synchronous with the execution maintenance and the line voltage of control figure algorithm, another road then flows to phase-locked loop, under the cooperation of 1/N frequency multiplier, forms the square-wave pulse signal T of N frequency multiplication
N, that is: T
N=NT
1T
NThen give the CAP4 mouth of dsp processor and capture the execution cycle of controlling sampling and digital algorithm with this.
Obviously, synchronous square-wave pulse signal T
1Can adapt to different line voltage frequencies automatically, as 50Hz or 60Hz electrical voltage system; Even there is under the situation of distortion square-wave pulse signal T in addition at line voltage
1Also can accurately reflect line voltage first-harmonic information, make that harmonic wave detection system of the present invention also can operate as normal.
And double frequency pulse signal T
NThen with square-wave pulse signal T
1Remaining synchronously and the relation of N multiple, utilizing that this frequency-doubled signal is for referencial use can to obtain equal interval sampling and control in a line voltage power frequency period, guaranteeing the precision of dsp processor Digital Implementation.Dsp processor 6 is fixed-point calculation type dsp chip U8, available TMS320F240, and clock frequency is decided to be 20MHz, and its unit instruction execution cycle is 50ns.For saving cost, adopted the built-in analog/digital converter of processor to carry out signal sampling; In each sampling period, dsp processor is connected to control its work with the S/H port of sampling/maintenance chip by the CAP1/IOPC4 port.The major function of dsp processor is according to the fundamental positive sequence in the specific algorithm extraction threephase load electric current in system.The fundametal compoment that dsp processor extracts outputs to D/A converter 8 by data I/O.D/A converter is a slice integrated chip U7, available MAX526, and the input of 12 parallel-by-bits has the fan-out capability of four-way.Dsp processor is connected with the LDAC port of MAX526 by the CAP2/IOPC5 port, to control its conversion; Address wire A0 and A1 then be used for selecting ALT-CH alternate channel (determine be A mutually, B mutually or the C phase), the three-phase simulation signal i that is converted to
Af', i
Bf' and i
Cf' respectively by port Vouta, Voutb and Voutc output.A phase level shifting circuit amplifies chip U9A by the integrated computing of half sheet and resistive element RC1, RC2 constitute.Correspondingly, B phase level shifting circuit is made of U9B and resistive element RC10, RC11; C phase level shifting circuit then is made of U12A and resistive element RC19, RC20.By level shifting circuit with unipolarity analog signal i
Af', i
Bf', i
Cf' be converted to the positive sequential signal i of ambipolar threephase load current first harmonics
Af, i
Bf, i
CfA phase analog addition circuit amplifies chip U10 by the integrated computing of a slice and corresponding resistive element R3～R9 constitutes, and finishes two signals from level shifting circuit and current sensor, i.e. A phase positive sequence of fundamental frequency i
AfWith corresponding A phase load current signal i
LaSubtract each other, similarly promptly, B also can similarly realize mutually with C mutually.Can obtain three-phase offset current instruction i like this
Ca *, i
Cb *, i
Cc *, wherein mainly comprise the harmonic component in the load current, in addition,, also may comprise fundamental reactive component and asymmetrical component etc. according to the load characteristic difference.
Fig. 3 is that the synchronous rotating frame first-harmonic based on the phase compensation strategy of the present invention extracts the digital algorithm flow chart.Based on the harmonic detecting method of reference synchronization coordinate system (Synchronous Reference Frame, be called for short SRF), it detects effect and is not subjected to line voltage distortion and factor affecting such as asymmetric, excellent performance, and be easy to Digital Implementation.The threephase load current i
La, i
Lb, i
LcAfter sampling, reject earlier its zero-sequence current component, utilize dq (synchronously rotating reference frame) conversion that it is transformed to the line voltage e mutually with A again
aSynchronously in the reference frame of rotation.In SRF, the fundamental positive sequence current component becomes DC quantity, can utilize low pass filter to leach, and is
Asymmetrical component and harmonic current components then are alternating quantity.Regulated quantity Δ i with DC voltage control
dWith
The phase adduction obtains three-phase fundamental positive sequence i required in the load current after the dq inverse transformation
Af, i
Bf, i
CfThe cosine and sine signal that uses in the algorithm adopts " look-up table ", and promptly calculated in advance goes out the sine and cosine value, respectively is 512 points, is positioned over when supplying computing in the memory directly to call, and reduces the routine processes time.Synchronous and the phase control of cosine and sine signal and electrical network then depends on the square-wave pulse signal T that the phase locking frequency multiplying circuit is carried
1And T
NThe dq transformation matrix of coordinates is among Fig. 3:
With the dsp processor be core to the nonlinear load electric current in fundametal compoment carry out in the Digital Extraction, because the time delay influence that digital system is intrinsic, make the fundamental signal of output have obvious time lag for actual signal, angle from the current phasor analysis, be equivalent to introduce an idle component, will influence compensation precision.The processing digit rates of the spectral characteristic of this delay and detected load, controlling of sampling frequency, digital signal processor etc. are relevant.In order to overcome the time delay that Digital Implementation is introduced, the present invention proposes the phase compensation strategy to realize that not having the time-delay first-harmonic extracts, it is characterized in that: in the transition matrix of three phase static coordinate system, introducing additive phase angle Δ θ by synchronous rotating frame, wherein, Δ θ=ω Δ T=2 π f Δ T, f is system's fundamental frequency, and Δ T is time of delay.Dq coordinate inverse transformation matrix is among Fig. 3:
Because nonlinear load is based on the circuit of power electronic device structure and realizes power transfer, it has introduced a large amount of harmonic waves in grid side, also may comprise reactive current.With reference to Fig. 1, Active Power Filter-APF inserts electrical network in the mode with the load parallel connection.After the harmonic wave detection system powers on, finish self check and and line voltage synchronously.The output of this mixed harmonic detection system offers parallel connection type active electric filter main circuit part current reference signal by way of compensation.Active Power Filter-APF main circuit 1 comprises that Current Control link 11, driving link 12,3-phase power converter 13 and AC side insert inductance 14.The current regulator root section produces three road PWM (pulse-width modulation) control waveform according to real-time measuring-signal of offset current and offset current reference signal, this pwm signal is used for driving 3-phase power converter by driving the link amplification, produce actual offset current and inject the electrical network public access point, reach the purpose of harmonic filtration and reactive power compensation.
Nonlinear load is the three-phase of band resistance sense load not controlled bridge-type rectification circuit, power output 15kW, electrical network phase voltage effective value 220V in the experiment.I among Fig. 4, Fig. 5
LBe load line electric current, i
CrBe the harmonic wave of Active Power Filter-APF compensation, i
SrThen be the grid side electric current after the compensation, take this to contrast investigation harmonic wave accuracy of detection.As adopt existing digital harmonic wave detection system, the current on line side i after compensating as seen from Figure 4
SrHave spine, this spine essence is time delay, and is very obvious at load current di/dt larger part especially, makes that the effect of active power filtering is relatively poor.And as seen from Figure 5, the current on line side i after the active filter that adopts mixed harmonic of the present invention to detect compensates
SrWaveform is smooth and do not have spine, and filter effect is very good, illustrates that the mixed harmonic detection that the present invention proposes has high-precision clear superiority.
Claims (4)
1. Active Power Filter-APF that adopts mixed harmonic to detect, have main circuit (1) and harmonics detection circuit (2) two parts, main circuit (1) comprises Current Control link (11), drives link (12), 3-phase power converter (13) and inductance (14), it is characterized in that harmonics detection circuit (2) comprising:
-current sensor (3) is used for measuring in real time the nonlinear load electric current, its input termination load current, and output divides two the tunnel, links to each other with the input of signal conditioning circuit (4) with analog adder (10) respectively;
-signal conditioning circuit (4) is used for filtering current sensor (3) output current signal (i
La, i
Lb, i
Lc) in HF noise signal, and change bipolar signal into unipolar signal (i
La', i
Lb', i
Lc');
-sample/hold circuit (5) is used for the unipolarity three-phase current signal (i to signal conditioning circuit (4) output
La', i
Lb', i
Lc') carry out the level maintenance at one time, export synchronous threephase load current signal, its input links to each other with the output of signal conditioning circuit (4);
-DSP chip (6), execution is based on the synchronously rotating reference frame algorithm of phase compensation, extract the fundamental positive sequence in the load current, an A/D conversion input of this chip links to each other with the output of sample/hold circuit (5), another A/D conversion input termination voltage control regulated quantity (Δ i
d);
-phase locking frequency multiplying circuit (7) is used for the zero crossing of line voltage is detected, and forms square-wave pulse signal (T
1), simultaneously with square-wave pulse signal (T
1) the N frequency multiplication, form double frequency pulse signal (T
N), the square-wave pulse signal (T of formation
1) and double frequency pulse signal (T
N) all the CAP mouth with DSP chip (6) link to each other;
-digital/analog converter (8) is used for the fundamental positive sequence of threephase load electric current is converted to unipolarity analog signal (i
Af', i
Bf', i
Cf'), its input is connected with the digital quantity output of DSP chip (6);
-level shifting circuit (9), the unipolarity analog signal conversion that is used for digital/analog converter (8) output is the positive sequential signal (i of ambipolar threephase load current first harmonics
Af, i
Bf, i
Cf), its input is connected with the output of digital/analog converter (8);
-analog adder (10), two input connect the output of level shifting circuit (9) and current sensor (3) respectively, and input signal is subtracted each other, and the harmonic component that obtains in the nonlinear load electric current is defeated by main circuit (1).
2. press the Active Power Filter-APF that the described employing mixed harmonic of claim 1 detects, it is characterized in that each phase signals modulate circuit in the said signal conditioning circuit (4) is by frequency overlapped-resistable filter, level shift circuit and amplitude limiter circuit constitute, wherein frequency overlapped-resistable filter amplifies chip (U1A) and corresponding resistive element RA1 by the integrated computing of half sheet, RA2 and capacity cell CA1, CA2 forms, level shift circuit amplifies chip (U1B) and corresponding resistive element RA3 by the integrated computing of half sheet, RA4, R5 and R6 form, and amplitude limiter circuit is made up of two Schottky diode DA1 and DA2.
3. press the Active Power Filter-APF that the described employing mixed harmonic of claim 1 detects, it is characterized in that said phase locking frequency multiplying circuit (7) is by zero cross detection circuit, shaping circuit, phase-locked loop and 1/N frequency dividing circuit constitute, wherein zero cross detection circuit amplifies chip U14A and relevant detection transformer (TP1) by the integrated computing of half sheet, diode DP1, DP2 and resistive element RP1, RP2, RP3 forms, shaping circuit is the inverter CD40106 of band application schmitt trigger function, and phase-locked loop and 1/N frequency dividing circuit then are made up of phase-locked loop chip (U16) sum counter chip (U17) and corresponding Resistor-Capacitor Unit.
4. the Active Power Filter-APF that detects by the described employing mixed harmonic of claim 3 is characterized in that said phase-locked loop chip (U16) is CD4046, and counter chip (U17) is CD4040.
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