CN1630038A - Etching solution and method for manufacturing conducting lug by selectively removing barrier layer with the same - Google Patents

Etching solution and method for manufacturing conducting lug by selectively removing barrier layer with the same Download PDF

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Publication number
CN1630038A
CN1630038A CNA2003101214870A CN200310121487A CN1630038A CN 1630038 A CN1630038 A CN 1630038A CN A2003101214870 A CNA2003101214870 A CN A2003101214870A CN 200310121487 A CN200310121487 A CN 200310121487A CN 1630038 A CN1630038 A CN 1630038A
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Prior art keywords
barrier layer
conductive projection
manufacture method
etching solution
conductive
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CNA2003101214870A
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CN100421216C (en
Inventor
孔令臣
邱绍玲
詹忠荣
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Ecker Advanced Polytron Technologies Inc
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UNITIVE SEMICONDUCTOR TAIWAN CORP
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849Reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An etching solution and the method for selectively removing barrier layer conductive bonding block contains providing a semiconductor substrate with prepared IC assembly wherein a metal layer or bonding pad to form a passivation layer on said substrate and exposing the surface of formed metal layer or bonding pad, forming a barrier layer on the passivation and exposed metal layer or bonding pad, forming a conductive under bump metallurgy layer on said barrier layer, defining boding block pattern on said conductive under bump metallurgy layer in coating exposing mode to form a hole, forming a conductive boding block layer to fill in said hole, removing residual coating material, etching said conductive under bump metallurgy layer, removing said barrier layer by special etching solution, dissolving and back flowing conductive bonding block by thermal process to form a spherical conductive boding block.

Description

Etching solution and use the conductive projection manufacture method of this etching solution selective removal barrier layer
Technical field
The invention relates to the etch recipe of a kind of semiconductor soldering projection (solder bump) processing procedure, is that the circuit structure that utilizes the etching solution of specific composition to avoid exposing comes to harm when etching.
Background technology
In manufacture of semiconductor, after the various assemblies on the wafer and interconnect are finished, can form connection gasket (bonding pad) and protective layer in the superiors, this protective layer be used for preventing that semiconductor subassembly and interconnect from being polluted, the influence of scratch and moisture.Follow-uply then can utilize little shadow and etch process; definition forms an opening on protective layer; expose to the open air out so that be arranged at the connection gasket (bonding pad) of protective layer bottom, make assembly see through the soldering projection (solder bump) on interconnect, weld pad and the weld pad and form and be electrically connected with the external circuitry plate.And the mode that is electrically connected at present then adopts crystalline substance (flip chip) technology of covering mostly.
The Flip Chip general reference of broad sense is carried out electricity through a metallic conductor with the external circuitry plate in ventricumbent mode and is engaged after chip is overturn.Generally speaking, metallic conductor includes metal coupling (metal bump), winding engages (tape-automated bonding), anisotropic conducting resinl (anisotropicconductive adhesives), macromolecular convex (polymer bump), routing balling-up (stud bump) or the like, this is wherein ripe with the metal coupling technology, also is widely used on the product of volume production.The forming method of metal coupling is a lot, common person has evaporation, sputter, plating, printing, routing moulding, injection molding etc., the material of metal coupling then according to different demands, has high temperature tin lead (SnPb), low temperature tin lead, gold, nickel, copper etc. to cover crystalline substance and plants ball (solder balls).
Please refer to Figure 1A to Fig. 1 F, it shows the schematic diagram of the manufacture method of known projection (bumping).Shown in Figure 1A, semiconductor substrate 10 is provided, it includes the integrated circuit package (not showing at this) that preparation is finished, and an aluminium pad (bonding pad) 12 and the protruding pad of metal (bumping pad) the 11st are arranged on this surface, semiconductor-based ends 10.Afterwards; please refer to Figure 1B; with a protective layer (passivation) the 14th, cover all integrated circuit packages on this surface, semiconductor-based ends 10, and one first opening 16 be the definition be formed on the protective layer 14 so that the surface portion of the protruding pad 11 of this metal exposes to the open air out.Secondly, shown in Fig. 1 C, on surface, the semiconductor-based ends 10, form a barrier layer (barrier layer) 18 and one metal level 20 in regular turn.Then, shown in Fig. 1 D, 10 surfaces are gone up and are formed a thick film photoresist layer 22 in the semiconductor-based ends, and it includes one second opening 24 is to be used for defining the pattern of metal bump location to be coated with little shadow mode.
Then, shown in Fig. 1 E, in second opening 24, electroplate a metal coupling 26 to form a conducting metal projection.Afterwards, shown in Fig. 1 F, after again thick film photoresist layer 22 being divested, in regular turn the metal level 20 beyond metal coupling 26 zones is removed with etching method with barrier layer 18, till exposing protective layer 14.At last, heating of metal projection 26 makes it form the spherical metal projection again.
Yet, on actual processing procedure experience, when in making the metal coupling process, facing the step of etch barrier, shown in Fig. 1 F, its etching solution tends to barrier layer is caused lateral erosion (side etch) 28, and also might be to exposed circuit structure such as aluminium pad (Al pad), fuse (fuse) etc. damages, and then influences component characteristic.Therefore, demand the road seeking to improve at the problems referred to above urgently, and make that production capacity and yield are promoted.
Summary of the invention
Because the problems referred to above, the object of the present invention is to provide a kind of etching solution and utilize the conductive projection manufacture method of this etching solution selective removal barrier layer, its alternative following barrier layer (barrier layer) of conductive projection (conductive bumping) of removing, and not injuring conductive projection and circuit structure such as aluminium pad (Al pad) to exposing, fuse (fuse) etc. damages.
For reaching above-mentioned purpose, the present invention provides a kind of etching solution, it is the composition liquid of hydrogen peroxide (Hydrogenperoxide), sulfonic group salicylic acid (Sulfosalicylic acid), potassium sulfate (Potassiumsulfate), BTA (Benzotriazole) and water (Water for makeup), this etching solution is controlled at suitable temperature and pH-value are alternative to be removed barrier layer and do not injure conductive projection, and uses this and invent manufacture method in conductive projection.
At first, provide one to prepare the semiconductor-based end of finishing integrated circuit package, and have a metal level (metal layer) and protruding pad (bonding pad) on it.Next, directly form a barrier layer in this metal level (metal layer) and protruding pad (bonding pad) surface.Subsequently, form a projection at the bottom of conducting shell (conductive under bump metallurgy layer) on this barrier layer.Follow-up, the mode with the coating exposure on conducting shell at the bottom of this projection defines the pattern of this projection to form a hole (hole); Afterwards, form a conductive bump layer again and insert this hole, and remove this residual coating thing.Conducting shell at the bottom of this projection of etching is removed this barrier layer with the etching solution of specific composition again.At last, heating this conductive projection makes it form a spherical conductive projection.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Illustrate:
Figure 1A-Fig. 1 F is that a known semiconductor conductive projection is made profile.
Fig. 2 A-Fig. 2 D makes profile for the semiconductor conductive projection in the preferred embodiment of the present invention.
Symbol description:
The semiconductor-based end-10; Aluminium pad-12; Metal protruding pad-11; Protective layer-14; First opening-16; Barrier layer-18; Metal level-20; Second opening-24; Photoresist layer-22; Metal coupling-26; Lateral erosion-28.
The semiconductor-based end-121; Metal level-119; Protruding pad-123; Hole-133; Barrier layer-127; Conducting shell at the bottom of the projection-129; Photoresist layer-131; Conductive projection-135.
Embodiment
For a conductive projection processing procedure, it has different structure utilizations in industry.Recommend an embodiment in spy herein and be applied in the conductive projection processing procedure so that method of the present invention to be described.
At first, please refer to Fig. 2 A, provide one to prepare the semiconductor-based end 121 of finishing the integrated circuit package (not shown), and has a metal level 119 on it, its material for example a metallic aluminium pad (Al pad) with usefulness as follow-up conductive projection processing procedure, and a protruding pad 123 (bonding pad), its material for example the protruding pad of a metallic aluminium (Al pad) with usefulness as follow-up wire bonding or test (testing).
Follow-up, please refer to Fig. 2 B, with sputtering method (sputting), vapour deposition method (evaporation) or chemical vapour deposition technique (CVD) compliance deposit a barrier layer 127 (barrier layer) in this metal level that exposes to the open air 119 and protruding pad 123 surfaces with as being used for the diffusion that barrier metal caused in the subsequent thermal processing procedure, the barrier layer material is a tungsten titanium coating (TiW) for example; And, before forming barrier layer 127, preferably handle to increase barrier layer 127 and 121 the tack in the semiconductor-based end prior to the surface cleaning of surface execution one wet type of the semiconductor-based ends 121 or dry type.Subsequently, conducting shell 129 (conductive under bump metallurgy layer) was on this barrier layer 127 at the bottom of compliance deposited a projection, it helps and is follow-up with the tack between the metal coupling that forms, and it for example is a metallic copper (Cu) for conductive material.Follow-up, on conducting shell 129 at the bottom of this projection, form a cover curtain layer 131 (masklayer) with coating method, material is a photoresistance or high-molecular photosensitive layer for example, again with the definition of the aligning Exposure mode of little shadow technology follow-up with conductive projection (conductive bump) pattern that forms on this semiconductor-based end 121 and form a hole 133 (hole), with plating template (platingtemplate) as follow-up formation conductive projection.At last, form 135 layers of conductive projections with plating mode and insert this hole 133, these conductive projection 135 materials are tin-based materials, for example tin lead (Sn-based, SnPb), tin (Sn), plumbous (Pb), silver (Ag) or copper (Cu) or contain the brazing metal of the alloy of above metal.
Next, please refer to Fig. 2 C, by implementing a wet type or dry-etching processing procedure to remove these conductive projection 135 patterns cover curtain layer 131 in addition.After cover curtain layer is removed, serve as the cover curtain with established conductive projection 135 again, remove that this wet etchant is an ammonium hydroxide (Ammonium Hydroxide) for example with conducting shell 129 at the bottom of waiting tropism's wet etching (isotropic etching) mode with this projection that exposes to the open air.Afterwards, use first-class tropism's wet etching mode again this barrier layer that exposes to the open air 127 is removed, and expose protruding pad 123 (Al pad) and fuse (fuse) district that does not make conductive projection 135.Because barrier layer etching solution of the present invention can not cause lateral erosion to barrier layer 127; also can be to exposed circuit structure such as aluminium pad (Al pad); fuse (fuse) etc. damages, so must more therefore not save one processing procedure in aluminium pad or the molten online layer protective layer that adds.This etching solution is by specific forming, a chemical mixture (chemical mixture) for example, and its content comprises:
1. hydrogen peroxide (Hydrogen peroxide): 10-20%
2. sulfonic group salicylic acid (Sulfosalicylic acid): 2-30 g/liter
3. potassium sulfate (Potassium sulfate): 25-200 g/liter
4. BTA (Benzotriazole): 1-10 g/liter
5. water (Water for makeup)
6. temperature: 30-70 ℃
7. pH-value<7
At last, please refer to Fig. 2 D, in for example thermal annealing mode conductive projection 135 is heated, make material production fusing (fluxed), backflow (reflowed) and the clean effect of welding portion, this conductive projection 135 forms a spherical conductive projection then, forms the preferable characteristic that is electrically connected in order to follow-up with the external circuitry plate.
The fill a prescription scope of its application of the etching solution of the invention described above comprises the plumbous even unleaded conductive projection processing procedure of the tin that is used in different proportion.This Ti-W etchant only can promptly not dissolve the Ti-W compound, and can not corrode for example aluminium, chromium, copper or plumber's solder, also can not cause lateral erosion to barrier layer, the more important thing is, can be to exposed circuit structure such as aluminium pad (Al pad), fuse (fuse) etc. damages, and can guarantee that component characteristic is unaffected.

Claims (18)

1. etching solution, it is alternative removes barrier layer and does not injure conductive projection, and it is formed with every liters of water is benchmark, comprising:
The hydrogen peroxide of 1000 milliliters of 10-20% volume ratios;
2-30 g sulfonic group salicylic acid;
25-200 g potassium sulfate; And
1-10 g BTA.
2. etching solution according to claim 1, wherein the temperature of this etching solution is 30-70 ℃.
3. etching solution according to claim 1, wherein the pH-value of this etching solution is less than 7.
4. etching solution according to claim 1, wherein this barrier layer is to comprise a tungsten titanium layer.
5. etching solution according to claim 1, wherein this conductive projection is the brazing metal that comprises a tin, lead, silver or copper or contain the alloy of above metal.
6. the conductive projection manufacture method of a selective removal barrier layer is applicable to that one contains the semiconductor-based end of integrated circuit, is formed with a metal level and a protruding pad on it, comprises the following steps:
Compliance forms a barrier layer on this metal level and protruding pad;
Electroplate and form a conductive projection on this barrier layer; And
Etching is removed barrier layer beyond this conductive projection to expose this metal level and protruding pad, the used etching solution of this step wherein, and it is formed with every liters of water is benchmark, comprising:
The hydrogen peroxide of 1000 milliliters of 10-20% volume ratios;
2-30 g sulfonic group salicylic acid;
25-200 g potassium sulfate; And
1-10 g BTA.
7. the conductive projection manufacture method of selective removal barrier layer according to claim 6, wherein this metal level is to comprise an aluminum metal layer.
8. the conductive projection manufacture method of selective removal barrier layer according to claim 6, wherein this barrier layer is to comprise a tungsten titanium layer.
9. the conductive projection manufacture method of selective removal barrier layer according to claim 6, wherein form more comprise before the conductive projection form a projection at the bottom of conducting shell on this barrier layer.
10. the conductive projection manufacture method of selective removal barrier layer according to claim 9, wherein conducting shell is to comprise a copper metal layer at the bottom of this projection.
11. the conductive projection manufacture method of selective removal barrier layer according to claim 6, wherein this conductive projection is the brazing metal that comprises a tin, lead, silver or copper or contain the alloy of above metal.
12. the conductive projection manufacture method of a selective removal barrier layer is applicable to that one contains the semiconductor-based end of integrated circuit, is formed with a metal level and a protruding pad on it, comprises the following steps:
Form a barrier layer on this metal level and protruding pad;
Form a conductive projection on this barrier layer; And
Remove this conductive projection barrier layer in addition, to expose this metal level and protruding pad; The used etching solution of this step wherein, it is formed with every liters of water is benchmark, comprising:
The hydrogen peroxide of 1000 milliliters of 10-20% volume ratios;
2-30 g sulfonic group salicylic acid;
25-200 g potassium sulfate; And
1-10 g BTA.
13. the conductive projection manufacture method of selective removal barrier layer according to claim 12, wherein this metal level is to comprise an aluminum metal layer.
14. the conductive projection manufacture method of selective removal barrier layer according to claim 12, wherein this protruding pad is to comprise an aluminum metal layer.
15. the conductive projection manufacture method of selective removal barrier layer according to claim 12, wherein this barrier layer is to comprise a tungsten titanium layer.
16. the conductive projection manufacture method of selective removal barrier layer according to claim 12, wherein form more comprise before the conductive projection form a projection at the bottom of conducting shell on this barrier layer.
17. the conductive projection manufacture method of selective removal barrier layer according to claim 16, wherein conducting shell is to comprise a copper metal layer at the bottom of this projection.
18. the conductive projection manufacture method of selective removal barrier layer according to claim 12, wherein this conductive projection is the brazing metal that comprises a tin, lead, silver or copper or contain the alloy of above metal.
CNB2003101214870A 2003-12-18 2003-12-18 Etching solution and method for manufacturing conducting lug by selectively removing barrier layer with the same Expired - Lifetime CN100421216C (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211798B (en) * 2006-12-29 2010-12-08 台湾积体电路制造股份有限公司 Solder tappet structure and its making method
CN110010576A (en) * 2018-01-05 2019-07-12 颀邦科技股份有限公司 Have the semiconductor device and its manufacturing method of projection cube structure
CN110310939A (en) * 2018-03-27 2019-10-08 矽品精密工业股份有限公司 Board structure and its preparation method and conductive bump
CN117497483A (en) * 2023-12-27 2024-02-02 日月新半导体(昆山)有限公司 Integrated circuit manufacturing method and integrated circuit device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5462638A (en) * 1994-06-15 1995-10-31 International Business Machines Corporation Selective etching of TiW for C4 fabrication
US6015505A (en) * 1997-10-30 2000-01-18 International Business Machines Corporation Process improvements for titanium-tungsten etching in the presence of electroplated C4's
JP2003293174A (en) * 2002-04-05 2003-10-15 Nippon Paint Co Ltd Acid etching solution for magnesium metal and/or alloy and surface treatment method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211798B (en) * 2006-12-29 2010-12-08 台湾积体电路制造股份有限公司 Solder tappet structure and its making method
CN110010576A (en) * 2018-01-05 2019-07-12 颀邦科技股份有限公司 Have the semiconductor device and its manufacturing method of projection cube structure
CN110310939A (en) * 2018-03-27 2019-10-08 矽品精密工业股份有限公司 Board structure and its preparation method and conductive bump
CN110310939B (en) * 2018-03-27 2021-04-30 矽品精密工业股份有限公司 Substrate structure and manufacturing method thereof and conductive bump
CN117497483A (en) * 2023-12-27 2024-02-02 日月新半导体(昆山)有限公司 Integrated circuit manufacturing method and integrated circuit device
CN117497483B (en) * 2023-12-27 2024-04-12 日月新半导体(昆山)有限公司 Integrated circuit manufacturing method and integrated circuit device

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Owner name: ECKEL ADVANCED TECHNOLOGY CO., LTD.

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