CN1627519A - Semiconductor and inverter structure and method for forming semiconductor structure - Google Patents
Semiconductor and inverter structure and method for forming semiconductor structure Download PDFInfo
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- CN1627519A CN1627519A CN 200410055185 CN200410055185A CN1627519A CN 1627519 A CN1627519 A CN 1627519A CN 200410055185 CN200410055185 CN 200410055185 CN 200410055185 A CN200410055185 A CN 200410055185A CN 1627519 A CN1627519 A CN 1627519A
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor device or circuit is formed on a semiconductor substrate with first and second semiconductor materials having different lattice-constants. A first transistor includes a channel region formed oppositely adjacent a source and drain region. At least a portion of the source and drain regions are formed in the second semiconductor material thereby forming lattice-mismatched zones in the first transistor. A second component is coupled to the transistor to form a circuit, e.g., an inverter. The second component can be a second transistor having a conductivity type differing from the first transistor or a resistor.
Description
Technical field
The invention relates to semiconductor subassembly, particularly relevant for a reverser and an integrated circuit that is applied in strained channel transistor (strained channel transistor).
Background technology
Between the past many decades for continuing to improve service speed, density and the cost of integrated circuit, the therefore size of dwindling gold-oxygen-half-court effect transistor (MOSFET), it comprise reduction of gate length with thickness of grid oxide layer.Typical integrated circuit comprises that many (for example: millions of) transistor, so industry attempts to improve those assemblies always constantly.
Reverser is one to be usually used in the semiconductor circuit of integrated circuit.Fig. 1 a shows an inverter circuit 104, and Fig. 1 b shows by these transistor 100,102 negative circuits of being formed 104 section Figure 106.One inverter 104 is to be used to reverse a logical states.One CMOS (CMOS) inverter comprises that a PMOS transistor 100 and a nmos pass transistor 102 are shown in Fig. 1 a and Fig. 1 b.In operation, as input terminal voltage V
INBe pressurized to supply voltage V
DD, i.e. logical states " 1 ", this nmos pass transistor 102 is a "open" state, this moment output end voltage V
OUTGround connection, i.e. logical states " 0 ".As this input V
INGround connection, and this output V
OUTBe driven to V
DDThe time, i.e. logical states " 1 ", this nmos pass transistor 102 in "off" state and this PMOS transistor 100 in "open" state.
Please refer to Fig. 1 b, the drain electrode 108 of this PMOS transistor 100 and this nmos pass transistor 102 all with output V
OUTConnect, its gate electrode 110 then is connected to an input V
INThe source electrode 112 of this PMOS transistor 100 is connected to supply voltage V
DDThe source electrode 114 of this nmos pass transistor 102 is ground connection then.
One load capacitance is with C
LExpression, the lumped capacity (lumpedcapacitance) of its representative between output and ground connection.Because this load capacitance C
LNeed to finish preceding charge or discharge so the effect of this reverser 104 and C in logic swing (logic swing)
LVery big influence is arranged.
This transmission delay (tp) is to demonstrate the speed that inverter 104 goes out to change through the input afterreaction, and this parameter is
t
p＝G
L.V
DD/I
av (Eq.1)
I wherein
AvBe the average current when voltage transitions, and V
DDIt then is a supply of current.In addition, transmission delay (t
PHL) relevant with nmos pass transistor 102 discharging currents, shown in Fig. 1 d; And transmission delay (t
PLH) then relevant with the charging current of PMOS transistor 100, shown in Fig. 1 c.This t
PHLWith t
PLHThe average delay of then representing inverter 104 integral body.For lowering the delay of this inverter 104, then need lower t
PHLValue, t
PLHValue or both all need be lowered.
The length of delay of inverter and other semiconductor circuit can reduce by increasing carrier transport factor.Past attempts report is used in silicon raceway groove biaxial stretch-formed stress under with effective enhancement whole transistor electronics hole mobility, should can be along the single shaft direction generation of parallel this source electrode to drain electrode by the tension force that high stress layer produces.By this, uniaxial tension stress improves electron mobility and single compressing stress is improved hole mobility.And germanium ion is implanted optionally in order to discharge this tension force.
Summary of the invention
In view of this, preferred embodiment of the present invention provides a kind of integrated circuit structure that utilizes strained channel transistor and forming method thereof.For example, comprise the attainable improvement invention of a strained channel transistor.
According to the first embodiment of the present invention, it comprises the first transistor that is formed at at semiconductor-based the end, and is formed at source electrode and the drain region that is adjacent to channel region in the substrate and relatively.Wherein, be formed in this second semi-conducting material to the source electrode and the drain region of small part, to form first, second lattice mismatch district (lattice-mismatched zones).One transistor seconds is formed at at semiconductor-based the end and has the conductive state different with the first transistor.
According to another preferred embodiment of the present invention, an inverter comprises a strained transistor and second half conductor assembly.This inverter was formed by the semiconductor-based end, and it comprises first, second semi-conducting material, and the lattice long number of this first semi-conducting material is different with second semi-conducting material.The source electrode of this strained transistor, drain electrode and channel region are formed at at semiconductor-based the end.First source electrode and drain region to small part are formed in second semi-conducting material, to form lattice mismatch district (lattice-mismatched zones) in the first transistor.This inverter also comprises that one is formed at at semiconductor-based the end and connects the load component of this first transistor.This load component can be any semiconductor subassembly, for example: a transistor seconds, one second strained transistor, or a resistance.
The advantage of preferred embodiment of the present invention is to lower the load capacitance of output precision.The attenuating of load capacitance can reduce the required time of the supercharging of output voltage assembly and step-down to increase the speed of this assembly.
Description of drawings
Fig. 1 a shows the inverter schematic diagram with lumped electric capacity of prior art between output and ground connection;
Fig. 1 b is the profile that shows the transistor formation inverter of prior art;
Fig. 1 c, Fig. 1 d are the operating characteristicses that shows an inverter;
Fig. 2 a-Fig. 2 c shows first, second, third embodiment of the present invention;
Fig. 3 a-Fig. 3 d shows alternative example structure;
Fig. 4 shows the preferred embodiment structure that another substitutes;
Fig. 5 a-Fig. 5 c is the integrated circuit that shows representative another embodiment more of the present invention;
Fig. 6 a-Fig. 6 h is the step that shows the preferred embodiment method of making semiconductor subassembly; And
Fig. 7 a-Fig. 7 c is the alternate embodiment that shows an inverter.
Symbol description:
100～PMOS transistor; 102～nmos pass transistor; 104～reverser; 106～negater circuit profile; 108～PMOS transistor drain; 110～gate electrode; 112～PMOS transistor source; 114～nmos pass transistor source electrode; V
In～input voltage; V
Out～output voltage; V
DD～power end voltage; V
SS～earth terminal voltage; CL～load capacitance; GROUNG～ground connection; N-～shallow the doping of N type; N+～N type heavy doping; t
PLH～transmission delay; t
PHL～transmission delay; 200～reverser; 201～nmos pass transistor; 202～PMOS strained transistor; 203,203a-c～isolation structure; 204～gate electrode; 205～grid spacer; 206～gate dielectric; 207～strained-channel nmos pass transistor; 208～channel region; 209～channel region; 210～NMOS drain region; 211～PMOS drain region; 212～drain electrode extension area; 213～drain electrode extension area; 214～dark drain region; 215～source electrode extension area; 216～nmos source district; 217～pmos source district; 218～source electrode extension area; 219～dark drain region; 220～deep source region; 221～deep source region; 222,304～stress riser; 223～lattice mismatch district; 226～silicon layer; 229,231,233,235～interconnect; 234～the second stress risers; 241～lattice mismatch district; 300～source electrode and drain region; 306,308,312,314～strained transistor; 315～metal silicide; 316～protrusion metal silicide; 318～source electrode or drain electrode extension area; 320～channel region; 330～transistor; 340～NAND grid; 342～NOR grid; 344～XOR grid; 408～the first active areas; 410～the second active areas; 412～stack; 418～hard mask; 420～auxiliary layer; 422～the first mask materials; 424～the second mask materials; 426～auxiliary compartment parting; 428～depressed area; 430～the second semi-conducting materials; 432～channel region; 434～transistor seconds; 436～the first transistor; 444～inner covering; 446～spacer body; 450～shallow trench region; 452～drain region; 770～resistance; 772,774～highly doped terminal part; 776～strained channel transistor; 778～resistance; 780～impedance part.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
The invention relates to the field of semiconductor subassembly and circuit, particularly make relevant for the negative circuit of utilizing strain channel field-effect transistor (strained channel field effect transistor).Below please cooperate Fig. 2 a-Fig. 2 c explanation the present invention first, second, third preferred embodiment, wherein those figure are generically and collectively referred to as Fig. 2.
Please refer to Fig. 2, provide first semi-conducting material 226 with as the semiconductor-based end, wherein this preferable material is a silicon.In addition, also comprise other semiconductor base compound, for example: GaAs (galliumarsenide) or the semiconductor that mixes, for example: silicon-germanium (silicon-germanium).And this parent material also can be the substrate that semiconductor (SOI) arranged on the insulating barrier, and the substrate of silicon is for example arranged on the insulating barrier.This parent material also comprises the doped region in a building crystal to grow semiconductor layer and/or the semiconductor substrate, for example: triple well constructions (triple well structure).
Please refer to Fig. 2 a, it is to show the inverter of being made up of transistor 2,01/,202 200.PMOS strained transistor 202 and nmos pass transistor 201 by the active area of isolation structure 203 definition.This PMOS strained transistor 202 has channel region 208, and this NMOS has a channel region 209 and have different conductive states with this PMOS channel region.
This gate electrode 204 forms and is arranged on the gate dielectric 206 by doping compound crystal silicon or compound crystal SiGe.In another embodiment, this gate electrode 204 can be formed by one or more metal, metal silicide, metal nitride or conducting metal oxide.In this preferred embodiment, this electrode 204 comprises a compound crystal silicon.Above-mentioned metal for example comprises: molybdenum (molybdenum), tungsten (tungsten), titanium (titanium), tantalum (tantalum), platinum (platinum) and hafnium (hafnium) can be used as top electrodes 204 parts.In addition, this above-mentioned metal nitride includes but not limited to molybdenum nitride (molybdenum nitride), tungsten nitride (tungsten nitride), titanium nitride (titanium nitride) and tantalum nitride (tantalumnitride).In addition, this metal silicide then includes but not limited to nickle silicide (nickel silicide), cobalt silicide (cobalt silicide), tungsten silicide (tungsten silicide), titanium silicide (titaniumsilicide), tantalum silicide (tantalum silicide), platinum silicide (platinum silicide) and silication erbium (erbium silicide).Conducting metal oxide then includes but not limited to ruthenium metal oxide (ruthenium oxide) and indium tin metal oxide (indium tin oxide).
In preferred embodiment of the present invention, this high dielectric constant material is a zirconia, and the average oxide thickness of the silicon of this dielectric medium 206 (EOT) is with preferable less than 50 , with better less than 20 , and even with better less than 10 .In addition, the thickness of this dielectric medium 206 is less than 100 , with better less than 50 , and even with better less than 20 persons.
This NMOS drain region 210 comprises a drain electrode extension area 212 that is connected with dark drain region 214, and this PMOS drain region 211 comprises a drain electrode extension area 213 that is connected with dark drain region 219.This nmos source district 216 comprises a source electrode extension area 218 that is connected with deep source region 221, and this pmos source district 217 comprises a source electrode extension area 215 that is connected with deep source region 220.
Shown in Fig. 2 a-Fig. 2 c, this first, second and the 3rd preferred embodiment more comprise interconnect 229,231,233,235.Wherein this interconnect is formed by metal or metal alloy, for example: aluminium, copper, tantalum, titanium, molybdenum, tungsten, platinum, hafnium, ruthenium or any above-mentioned connection.When utilize lead (for example: copper) link connector to another place and during the supply node, can be (for example: tungsten) contact this silicon area via conductive plunger.
Show among the one special embodiment that interconnect 235 connects this PMOS drain electrode 211 and this NMOS drain electrode 210 and transmits the output voltage V of this negative circuit
OUTAnother interconnect 233 provides a supply voltage V
DDTo pmos source district 217.One the 3rd interconnect 231 connects a supply voltage V
SSTo nmos source district 216.In a preferred embodiment, V
SSIt is an earth connection and voltage range that VDD provides is 0.3-5 volt (for example: be lower than 1.8 volts).In addition, be connected to supply of current V by the 4th interconnect 229 again after this gate electrode 204 interconnects
IN
One negative-phase sequence curent comprises said modules.If by this input voltage V
INThe voltage that provides equals or V no better than
DD, this output voltage V
OUTWill equal or voltage V no better than
SSOpposite, if one by this input voltage V
INThe voltage that provides equals or V no better than
SS, this output voltage V
OUTWill equal or voltage V no better than
DD
In a preferred embodiment, this channel region 208 comprises a compound crystal silicon.This compound crystal silicon has diamond lattice structure and should about 5.431 of essence lattice constant.This essence lattice constant is the lattice constant under the lax or equilibrium state that expands of this material.
In first preferred embodiment, a strained channel PMOS transistor 202 is connected to form an inverter, shown in Fig. 2 a with a nmos pass transistor 201.First stress riser 222 is the zone that the pmos source 217 and 211 districts that drain can not ignore, and it is formed at the zone near these PMOS raceway groove 208 both sides.Utilize lattice mismatch district (lattice-mismatched zones) 223 to define the face that connects of first, second semi-conducting material 226,222 in the PMOS transistor 202.At this, those figure there is no by actual ratio and represent.In preferred embodiment, when source electrode and drain electrode about 1,000 dusts of the degree of depth or when darker, the only about hundreds of dust of the actual (real) thickness of stress riser.Therefore, this stress riser is generally the sub-fraction of this source/drain regions.
This second semi-conducting material 222 comprises a doped semiconductor, and for example: essential lattice constant is silicon-germanium of 5.431-5.657 , and should the essence lattice constant depends on the concentration of germanium in silicon-germanium.One result from source electrode 217 and the channel region 208 of 211 directions that drain on compression stress, can increase the transistorized drive current of PMOS and make this PMOS transistor supply VDD to transmit higher charging current to output V from power
OUT, and should can make PMOS transistor 202 produce less transmission delay t than high charge current
PLHBy transmission delay t
PLHReduce the usefulness that can further reduce the delay of inverter 200 and improve inverter circuit.
Shown in Fig. 2 b, in second preferred embodiment, connect a PMOS transistor 205 and strained-channel nmos pass transistor 207 to form an inverter 200.One second stress riser 234 is formed near 209 liang of lateral areas of this NMOS raceway groove by the 3rd semi-conducting material and is the pith in this nmos source 216 and 210 districts that drain.Utilize lattice mismatch district (lattice-mismatched zones) 241 to define the face that connects of the first, the 3rd conductor material 226,234 in the nmos pass transistor 207.
The 3rd semi-conducting material 234 of this second stress riser 234 can comprise a doped semiconductor, for example: silicon-germanium-carbon (Si
1-x-yGe
xC
y) or silico-carbo (Si
1-yC
y).If the concentration of carbon of this silicon-germanium-carbon is greater than 1/10th of germanium concentration, then the lattice constant of this silicon-germanium-carbon will be less than silicon.This lattice mismatch district (lattice-mismatched zones) 241 also comprises the semiconductor of a lattice constant less than silicon, for example: silico-carbo (Si
1-yC
y), the about 0.01-0.04 of its mole fraction y.
This lattice mismatch district (lattice-mismatched zones) 241 comprises second stress riser 234 of this channel region 209 being implemented strain stress, wherein this stress riser 234 is made up of less than the 3rd semi-conducting material of first semi-conducting material 226 lattice constant, to produce a tensile stress on first semi-conducting material 226 of whole NMOS channel region 209.Wherein, can promote the electron mobility of this strain type NMOS channel transistor 207 along source electrode 216 to the tensile stress (u is along being parallel to source electrode to the online direction that drains) of drain electrode 210 directions, and then make nmos pass transistor 201 in this output V
OUTTransmit higher discharging current during ground connection.And this higher discharging current can make nmos pass transistor 207 produce less transmission delay t
PHLBy transmission delay t
PHLReduce the usefulness that can further reduce the delay of inverter 200 and improve inverter circuit.
Shown in Fig. 2 c, in the 3rd preferred embodiment, a PMOS transistor 202 is connected with strained-channel nmos pass transistor 207 to form an inverter 200.One first stress riser 222 is formed near 208 liang of lateral areas of this PMOS raceway groove and is the part that this pmos source 217 and 211 districts that drain can not ignore.Utilize lattice mismatch district (lattice-mismatched zones) to define the face that connects of first, second conductor material 226,222 in the PMOS transistor 202.This second stress riser 234 is formed near 209 liang of lateral areas of this NMOS raceway groove and is the pith in this nmos source 216 and 210 districts that drain.Utilize lattice mismatch district (lattice-mismatched zones) to define the face that connects of first, second conductor material 226,234 in the nmos pass transistor 207.
In sum, can promote the drive current of PMOS transistor 202 by the compression stress that PMOS channel region 208 produces, and can improve the discharging current of nmos pass transistor 207 by the strain stress that NMOS channel region 209 produces.As mentioned above, the present invention by higher PMOS transistor 202 drive currents to reduce t
PLHAnd by higher nmos pass transistor 201 discharging currents to reduce t
PLH, and then effectively improve the usefulness of inverter 200.
Fig. 3 a-Fig. 3 d is generically and collectively referred to as Fig. 3 at this, is a plurality of embodiment that show the stress riser in the strained channel transistor 306,308,312 and 314.This first, second stress riser is with 300 expressions.This strained transistor 306,308,312,314 of Fig. 3 is then represented strain type nmos pass transistor 207 and strain type PMOS transistor 202, and this source electrode and drain region 300 are then represented the source electrode 210 of strain type nmos pass transistor 207 and drained 216 and the source electrode 211 of strain type PMOS transistor 202 and drain 217.
In Fig. 3, the position of this stress riser 304 be for explanation with but be not limited thereto.Fig. 3 shows that this stress riser 304 can be formed at any part of source electrode or drain region 300.That this stress riser 300 is hidden for shallow embedding shown in Fig. 3 b and cover with silicon layer 226, and this preferable silicon layer is first semi-conducting material or its homologue.
An electric conducting material 315 as shown in Figure 3, for example a metal silicide (for example: titanium silicide, cobalt silicide, nickle silicide, tantalum silicide, silication erbium, silication iridium) is formed at source electrode and drain region 300 to reduce resistance coefficient.Other material comprises germanium cobalt silicide (cobalt germanosilicide), germanium nickle silicide (nickelgermanosilicide), carbon-cobalt silicide (cobalt carbon-silicide), carbon-nickle silicide (nickel carbon-silicide).This metal silicide 315 is formed in the substrate and under the surface of this gate dielectric, shown in Fig. 3 a, Fig. 3 b, perhaps forms the lip-deep protrusion metal silicide 316 that extends to this gate dielectric 206, shown in Fig. 3 c, Fig. 3 d.This stress riser 304 also can further extend to gate dielectric 206 surfaces and go up the source electrode and the drain region of raising with formation.Fig. 3 d shows that this stress riser 304 is formed at 226 times these first semi-conducting materials of substrate surface and then is formed on the substrate surface 226 and between metal silicide 315 and this stress riser 304.
In addition, as shown in Figure 4, this stress riser 300 can extend horizontally to this source electrode or drain electrode extension area 318.In transistor 330, this stress riser that is adjacent to channel region 320 is very relevant with the functional characteristic of required component.Form electronics or the hole mobility that 300 of this stress risers can be promoted this transistor 330 more near channel region more.
Fig. 5 a-Fig. 5 c is the circuit diagram that shows a plurality of embodiment, for example the present invention includes: NOR grid 342 (Fig. 5 a), NAND grid 340 (Fig. 5 b), XOR grid 344 (Fig. 5 c).Those embodiment are multiple circuit of display application notion of the present invention.For example, when this nmos pass transistor did not have strain, this PMOS transistor can be strained channel transistor and (sees Fig. 2 for details a).In another embodiment, this nmos pass transistor is by strain, and this PMOS transistor does not then have (seeing Fig. 2 b for details).At last, disclose as the embodiment of Fig. 2 c, this NMOS and PMOS transistor are all by strain.This for embodiment be in order to explanation the present invention but be not limited to this scope.
On the other hand, the present invention is that a kind of integration of proposition has the strained channel transistor method more than a kind of conductive state, and its influence to the transistorized carrier transport factor of another kind of conductive state can be reduced to minimum.The circuit diagram of this Fig. 5 a-Fig. 5 c provides the embodiment circuit diagram that utilizes those advantages.
Please refer to Fig. 6 a-Fig. 6 h, it is the manufacture method that shows the strained channel transistor integrated circuit with multiple conductive state.Provide semiconductor substrate 226 preferable, then in substrate, form isolation structure 203 to define active area with silicon base.This isolation structure 203 is to utilize the standard shallow trench isolation to form from (STI) processing procedure, for example comprise the following steps: to etch the groove that the degree of depth is 2000-6000 , utilize the chemical vapor deposition process filled dielectric material in this groove, and carry out a chemical-mechanical planarization, to form the cross-section structure shown in Fig. 6 a.At this, also can use other isolation structure, for example field oxide (promptly utilizing the local oxidation of silicon method to form).
Shown in Fig. 6 a, form a stack 412 in first, second active area 408/410.Wherein this stack 412 comprises a hard mask 418, a gate electrode 204 and a gate dielectric 206.Form hard mask 418 protective layers in these gate electrode 204 tops.This gate electrode 204 then is formed on this gate dielectric 206, can utilize any known and gate dielectric making step (for example: thermal oxidation method, nitriding, sputter-deposited method or chemical vapour deposition technique) of being applicable to the present technique field to form this gate dielectric 206 at this.The thickness range of this gate dielectric 206 is 5-100 .This gate dielectric 206 is a traditional gate dielectric, for example: silicon dioxide, silicon oxynitride, high K dielectric matter or above-mentioned combination.
Please refer to Fig. 6 b, an auxiliary layer 420 is formed on first, second active area 408/410.This auxiliary layer is to utilize chemical vapour deposition (CVD) or sputter-deposited one dielectric layer and form, and wherein should auxiliary can be oxide.In preferred embodiment of the present invention, these auxiliary layer 420 thickness are about 20-100 .
Then please refer to Fig. 6 c, one first mask material 422 is formed on first, second active area 408/410.This material 422 comprises, for example: silicon dioxide, silicon oxynitride or silicon nitride.In preferred embodiment of the present invention, this first mask material 422 is included in the silicon nitride on the silicon dioxide multiple layer.
Fig. 6 d be show to utilize deposition and little shadow technology form one second mask material 424 on this second active area 410 to cover this first mask material 422, expose this first mask material 422 simultaneously to the open air for first active area.This second mask material 424 can comprise any mask material different with first mask material 422.In preferred embodiment of the present invention, this second mask material comprises a photoresist.
Utilize first mask material 422 of this second mask material, 424 etchings, second active area 410.At this preferable etch process electric paste etching that is anisotropic.The result forms auxiliary compartment parting or inner covering 426 in stack 412 districts in abutting connection with this first active area 408 shown in Fig. 6 e.
After forming this auxiliary compartment parting 426, etching the depressed area 428 of roughly aliging with this auxiliary compartment parting 426 in this active area, is to utilize above-mentioned silicon etching chemistry technology to form at this.Behind this etch process, remove this second mask material 424.
Then, this second semi-conducting material 430 of building crystal to grow is to fill this depressed area 428, and wherein this growth is to utilize selectivity building crystal to grow (SEG) to finish.Should can be chemical vapour deposition technique (CVD), high vacuum chemical vapour deposition process (UHV-CVD) or molecular beam epitaxy (MBE) in order to the processing procedure of finishing building crystal to grow.Perhaps, also extensible this building crystal to grow material has formed source electrode and the drain electrode structure raised, shown in Fig. 6 f to channel region 432 surfaces of this first active area 408.
This second semi-conducting material 430 comprises that the germanium mole fraction is silicon-germanium of 0.1-0.9.This second semiconductor comprises that in addition the carbon mole fraction is the silico-carbo of 0.01-0.04.In addition, this second semiconductor also can comprise silicon-germanium-carbon (Si
1-x-yGe
zC
y).If the concentration of carbon of this silicon-germanium-carbon is higher than 1/10th of germanium concentration, then its lattice constant can be lower than silicon.
Cover hard mask 418 in gate electrode 204 tops in case building crystal to grow on this gate electrode 204.This auxiliary compartment parting 426 then can be avoided the building crystal to grow of gate electrode sidewalls.Behind this building crystal to grow, remove this hard mask 418, auxiliary layer 420, auxiliary compartment parting 426 and first mask material 422 to form the structure shown in Fig. 6 g.
In first semi-conducting material, 226 processes of building crystal to grow, can comprise in-situ doped or undope.If in growing up, do not mix, also can mix and utilize a Rapid Thermal tempering manufacturing process to activate this alloy again in subsequent process.The importing of this alloy can utilize conventional ion implantation, electricity slurry to immerse ionic-implantation (PIII), gas or solid source diffusion or any other is known and be applicable to the technology in present technique field.Any implantation defective and do not have the lattice arrangement structure and all can repair by the temper of follow-up intensification.
Fig. 6 h is the processing procedure that shows follow-up semiconductor subassembly.On Fig. 6 g structure, carry out one first shallow implantation with the shallow trench region 450 of mix first, second transistor source and drain region 452 and form this source/drain extension area.
Form sidewall spacer in gate electrode 204 both sides.In embodiment, utilize chemical vapour deposition (CVD) one dielectric material forming sept, this dielectric material for example: silicon dioxide or silicon nitride, then this dielectric material of anisotropic etching is to form a pair of sept.In the embodiment of Fig. 6 h, this sept is a compound interval insulant.This compound sept can comprise a dielectric medium inner covering 444 and a spacer body 446.Wherein this dielectric medium inner covering 444 can (for example: silicon dioxide) form, this spacer body 446 is then by for example: silicon nitride forms, and then utilizes reactive ion etching to carry out an anisotropic etching by deposition one dielectric medium inner covering material.In another embodiment, this inner covering 444 can be oxide, and this spacer body 446 can be nitride.
When covering transistor seconds 434, utilize ion to implant source electrode and the drain region that forms the first transistor 436, this preferable alloy is arsenic, phosphorus or both combinations.The source electrode of the first transistor 434 and drain region then are to utilize ion to implant when covering this first transistor 436 to form, and its preferable alloy is a boron.Then on this first, second active area 408/410, form a protective layer 448.
Fig. 7 a-Fig. 7 c shows the embodiment of another inverter.In this embodiment, this inverter 770 comprises the strained channel transistor 776 of the resistance 778 that is connected in series.As shown in Figure 2, a transistor is as load component, and this load component then is a resistance 778 in this embodiment.This strained channel transistor 776 can be nmos pass transistor (Fig. 7 b) or PMOS transistor (Fig. 7 c).And the transistorized conductive state on other chip position is depended in transistorized selection usually.
Please refer to Fig. 7 a, this resistance 778 comprises that one separates the impedance part 780 of two highly doped terminal parts 772,774.This terminal part 772 connects the source/drain regions 214 of this transistor 776.Show that in graphic an isolated groove 203b is formed between two districts 214,772.In some cases, when this two district 214,772 was same conductive state, removable this isolated groove 203b was to reduce this surface area.
This second terminal 774 is connected to voltage supply V
2Please refer to Fig. 7 b, this voltage supply node V
2Be this supply node V
DD, and this voltage supply node V
1Be this supply node V
SS(for example: ground connection).Please refer to Fig. 7 c, this voltage supply node V
2Be this supply node V
SS, and this voltage supply node V
1Be this supply node V
DDThough do not show at this, other assembly (for example: a transistor) can be connected in this supply node V
1, V
2And between the transistor of this inverter assembly 776,778.
In another embodiment, merge a resistance 778 that has been exposed in the Taiwan application number 93110079 disclosed resistance kenels in the co-applications and incorporate annex into as a reference.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (32)
1. semiconductor structure comprises:
The semiconductor substrate, it lattice constant that comprises first, second semi-conducting material and this first semi-conducting material is different with this second semi-conducting material;
One the first transistor, be formed in this semiconductor-based end, wherein this first transistor has first source electrode and the drain region that is formed in this substrate and is adjacent to one first channel region relatively, wherein a first grid dielectric medium covers this first channel region and a first grid electrode covers this first grid dielectric medium, and this first source electrode and the drain region of at least a portion are formed in this second semi-conducting material and this first channel region is formed in this first semi-conducting material; And
One transistor seconds, be formed in this semiconductor-based end, its conductive state is different with this first transistor, this transistor seconds has one and is formed in this substrate and is adjacent to second source electrode and the drain region of second channel region relatively, and wherein a second grid dielectric medium covers this second channel region and a second grid electrode covers this second grid dielectric medium.
2. semiconductor structure according to claim 1, wherein this first transistor is connected with this transistor seconds with the NOR circuit that forms an inverter, part, the NAND circuit of part or the XOR circuit of part.
3. semiconductor structure according to claim 1, wherein this first and the second grid dielectric medium be to form by a high dielectric constant material.
4. semiconductor structure according to claim 1, wherein the lattice constant of this second semi-conducting material is big than this first semi-conducting material person, and this first transistor is a PMOS transistor.
5. semiconductor structure according to claim 1, wherein this second semi-conducting material comprises silicon and germanium.
6. semiconductor structure according to claim 5, wherein the concentration of this germanium is greater than 10%.
7. semiconductor structure according to claim 1, wherein this second semi-conducting material comprises silicon, germanium and carbon.
8. semiconductor structure according to claim 1, wherein the lattice constant of this second semi-conducting material is little than this first semi-conducting material person, and this first transistor is a nmos pass transistor.
9. semiconductor structure according to claim 8, wherein this second semi-conducting material comprises silicon and carbon.
10. semiconductor structure according to claim 9, wherein the concentration range of this carbon is 0.01-0.04%.
11. semiconductor structure according to claim 1, wherein this second source electrode and the drain region to small part formed by one the 3rd semi-conducting material.
12. semiconductor structure according to claim 11, wherein the lattice constant of this second semi-conducting material is big than this first semi-conducting material person and lattice constant the 3rd material is little than this first material person.
13. semiconductor structure according to claim 12, wherein this first transistor is a PMOS and this transistor seconds is a NMOS.
14. semiconductor structure according to claim 12, wherein the 3rd semi-conducting material comprises silicon, germanium and carbon.
15. semiconductor structure according to claim 1, wherein this first, second source electrode and drain region and this first, second transistorized gate electrode distinctly comprise a silicide portions.
16. semiconductor structure according to claim 1, wherein the distance at the face that connects between this first and second semi-conducting material and this gate dielectric edge is less than 700 .
17. an inverter comprises:
One transistor, be formed at at semiconductor-based the end, this transistor has source electrode and the drain region that is formed in this substrate and is adjacent to a channel region relatively, wherein this raceway groove is formed in one first electric conducting material and this source electrode and the drain region of the small part that arrives are formed in one second electric conducting material, and this first electric conducting material is different with this second electric conducting material;
One load component was formed in this semiconductor-based end, and this load component is connected between this drain region and the one first voltage supply node; And
One second voltage supply node connects this source area.
18. inverter according to claim 17, wherein the lattice constant of this second semi-conducting material is big than this first semi-conducting material, and this transistor is a PMOS transistor.
19. inverter according to claim 17, wherein the lattice constant of this second semi-conducting material is little than this first semi-conducting material person, and this transistor is a nmos pass transistor.
20. a method that forms semiconductor structure comprises the following steps:
The semiconductor substrate is provided, and this substrate comprises the semiconductor main body that is formed by one first semi-conducting material;
Definition first and second active area in this semiconductor body;
Form a first transistor in this first active area, this the first transistor comprises source electrode and the drain region that is formed in this semiconductor body and is adjacent to a channel region relatively, this the first transistor comprises that more a gate dielectric and that is formed at this channel region is formed at the first grid electrode on this first grid dielectric medium, wherein this first channel region is formed in this first semi-conducting material and the source electrode and the drain region of this at least a portion are formed in one second semi-conducting material, and this second semi-conducting material has the lattice constant different with this first semi-conducting material;
Form one second assembly in this second active area; And
Form a conductor between this transistor drain and a load component.
21. the method for formation semiconductor structure according to claim 20, wherein this second assembly comprises a transistor seconds of different conduction forms with this first transistor, and this transistor seconds has second source electrode and the drain region that is formed at also relative adjacency one second channel region in this semiconductor, and wherein this conductor is formed between the source electrode of this first transistor and this transistor seconds.
22. the method for formation semiconductor structure according to claim 21 more comprises:
Electrically connect the source electrode and the one first voltage supply node of this first transistor; And the source electrode and the one second voltage supply node that electrically connect this transistor seconds.
23. the method for formation semiconductor structure according to claim 20, wherein this second assembly comprises a resistance.
24. the method for formation semiconductor structure according to claim 23, wherein this resistance comprises first and second end points so that this conductor is formed between one first end points of this transistor drain and this resistance, and this method more comprises:
Electrically connect source electrode and this first voltage supply node of this first transistor; And one second end points and this second voltage supply node that electrically connect this resistance.
25. the method for formation semiconductor structure according to claim 20 wherein forms this first transistor and comprises:
Form a stack, this storehouse comprises this gate dielectric and this gate electrode;
Form a dielectric layer on one first active area that includes this stack;
Non-grade to this dielectric layer of etching to form a sidewall spacer along this gate electrode sidewalls;
This semiconductor body of etching part is adjacent to the groove of this sidewall spacer with formation; And
Form this second semi-conducting material in this groove.
26. more comprising, the method for formation semiconductor structure according to claim 25 forms one first semiconductor material layer on this second semi-conducting material.
27. the method for formation semiconductor structure according to claim 20, wherein this second semi-conducting material comprises silicon and germanium, and its lattice constant is big than this first semi-conducting material person.
28. the method for formation semiconductor structure according to claim 27, wherein this second conductor material comprises silicon, germanium and carbon.
29. the method for formation semiconductor structure according to claim 27, wherein the concentration of this germanium is greater than 10%.
30. the method for formation semiconductor structure according to claim 20, wherein this second semi-conducting material comprises silicon and carbon, and its lattice constant is little than this first semi-conducting material.
31. the method for formation semiconductor structure according to claim 30, wherein this second semi-conducting material comprises silicon, germanium and carbon.
32. the method for formation semiconductor structure according to claim 31, wherein the concentration range of this germanium is 0.01-0.04%.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US49558403P | 2003-08-15 | 2003-08-15 | |
| US60/495,584 | 2003-08-15 | ||
| US10/729,092 | 2003-12-05 | ||
| US10/729,092 US20050035369A1 (en) | 2003-08-15 | 2003-12-05 | Structure and method of forming integrated circuits utilizing strained channel transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1627519A true CN1627519A (en) | 2005-06-15 |
| CN100334730C CN100334730C (en) | 2007-08-29 |
Family
ID=34798725
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100551852A Expired - Lifetime CN100334730C (en) | 2003-08-15 | 2004-08-12 | Semiconductor and inverter structure and method for forming semiconductor structure |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN100334730C (en) |
| SG (1) | SG120169A1 (en) |
| TW (1) | TWI241627B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101136434B (en) * | 2006-08-29 | 2010-07-21 | 台湾积体电路制造股份有限公司 | Semiconductor integrated circuit device |
| US7781277B2 (en) | 2006-05-12 | 2010-08-24 | Freescale Semiconductor, Inc. | Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit |
| US8527933B2 (en) | 2011-09-20 | 2013-09-03 | Freescale Semiconductor, Inc. | Layout technique for stress management cells |
| CN109977531A (en) * | 2019-03-20 | 2019-07-05 | 天津工业大学 | A kind of domain structure of the standard block for digital integrated electronic circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5155571A (en) * | 1990-08-06 | 1992-10-13 | The Regents Of The University Of California | Complementary field effect transistors having strained superlattice structure |
| WO2002047168A2 (en) * | 2000-12-04 | 2002-06-13 | Amberwave Systems Corporation | Cmos inverter circuits utilizing strained silicon surface channel mosfets |
| CN2751143Y (en) * | 2004-09-27 | 2006-01-11 | 高永祥 | Automobile exhaust gas measurement and control device |
-
2004
- 2004-06-17 SG SG200403815A patent/SG120169A1/en unknown
- 2004-07-06 TW TW93120208A patent/TWI241627B/en not_active IP Right Cessation
- 2004-08-12 CN CNB2004100551852A patent/CN100334730C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7781277B2 (en) | 2006-05-12 | 2010-08-24 | Freescale Semiconductor, Inc. | Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit |
| CN101136434B (en) * | 2006-08-29 | 2010-07-21 | 台湾积体电路制造股份有限公司 | Semiconductor integrated circuit device |
| US8527933B2 (en) | 2011-09-20 | 2013-09-03 | Freescale Semiconductor, Inc. | Layout technique for stress management cells |
| CN109977531A (en) * | 2019-03-20 | 2019-07-05 | 天津工业大学 | A kind of domain structure of the standard block for digital integrated electronic circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100334730C (en) | 2007-08-29 |
| TW200507037A (en) | 2005-02-16 |
| TWI241627B (en) | 2005-10-11 |
| SG120169A1 (en) | 2006-03-28 |
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