CN2724204Y - Semiconductor chip - Google Patents
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- CN2724204Y CN2724204Y CN 200420084399 CN200420084399U CN2724204Y CN 2724204 Y CN2724204 Y CN 2724204Y CN 200420084399 CN200420084399 CN 200420084399 CN 200420084399 U CN200420084399 U CN 200420084399U CN 2724204 Y CN2724204 Y CN 2724204Y
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Abstract
The utility model relates to a semiconductor chip which comprises a semiconductor base which is provided with a first and a second active areas, a resistor which is formed in the first active area and comprises a doped area formed between both endpoints, a strained channel transistor which is formed in the second active area and comprises a first and a second stress sources formed in the base oppositely adjacent to a strained channel area.
Description
Technical field
The utility model relates to a kind of semiconductor subassembly, and preferred embodiment is to be particularly to a kind of strain type raceway groove (strained channel) complementary type field-effect transistor (complementaryfield-effect transistor).
Background technology
Metal-oxide half field effect transistor (metal-oxide-semiconductor field-effecttransistor; MOSFET) method that size is dwindled can comprise grid length with the reduction of gate oxide thicknesses, it made speed performance, current densities and the per unit usefulness cost etc. of integrated circuit all have lasting improvement recent decades in past.For further strengthening transistorized usefulness, stress can be caused in the transistor channel to improve carrier transport factor (carrier mobility), therefore the enhancing by mobility that strain inducing causes is another approach that increases performance of transistors except dwindling size of components, and exists some guiding stress in the method for transistor channel region already.
Provide a relaxed silicon-Germanium resilient coating (relaxed SiGe buffer layer) under channel region in the one existing method.And in this class component, the semiconductor assembly is to comprise a strained silicon layer (strainedsilicon layer) to be formed on the relaxed silicon germanium layer and to adjoin each other, and this relaxed silicon germanium layer then is formed at a gradual change silicon germanium buffer (graded SiGe buffer layer) and goes up and adjoin each other.
The relaxed silicon-Germanium resilient coating has a bigger lattice constant (lattice constant) with respect to relaxed silicon (relaxed Si), therefore crystal silicon of heap of stone (epitaxial Si) thin layer of being longer than on the relaxed silicon germanium layer will make its lattice in extending laterally, and also refer to that it will be subjected to biaxial stretch-formed strain (biaxial tensilestrain); Therefore, one be formed at transistor on the brilliant strained silicon layer (eptiaxial strained silicon layer) of heap of stone one channel region that is subjected to biaxial stretch-formed strain will be arranged.In the method, the relaxed silicon-Germanium resilient coating can be considered a stress riser (stressor), and it causes stress in the channel region.In this example, stress riser is to be positioned at the transistor channel region below.
A kind of method that significantly strengthens electronics and hole mobility in bulk transistor (bulk transistor) simultaneously is to disclose already, and it utilizes biaxial stretch-formed strain to control a silicon raceway groove.In the said method, crystal silicon layer of heap of stone is promptly to be subjected to stress before transistor forms, therefore for using the stress relaxation (strain relaxation) that high temperature caused that a little misgivings are arranged in the CMOS manufacturing process thereafter.In addition, because the method need grow up to the silicon germanium buffer that a thickness is micron grade, so the required cost costliness that expends.And numerous difference row (dislocation) is present in the relaxed silicon-Germanium resilient coating, and wherein some difference is arranged even spread to strained silicon layer, causes substrate to have high defect concentration (defect density).Therefore, the method has the restriction about cost and stock characteristic.
In the other method, the stress of raceway groove is to be subjected to luring drawing after transistor forms again.In the method, a heavily stressed film (stress film) is formed on the perfect crystal tubular construction that is positioned at silicon base.Stress film or stress riser are to have applied remarkable influence for raceway groove, and it is in order to modifying the silicon crystal lattice spacing (lattice spacing) of channel region, and therefore cause the stress of channel region.In this example, stress riser is to be positioned on the perfect crystal tubular construction.This kind design is delivered in " Local mechanicalstress control (LMC): a new technology for CMOS performanceenhancement " by people such as A.Shimizu to set forth.
By stress that heavily stressed film provided through thinking that it is one to have single shaft (uniaxial) direction of parallel source electrode toward drain directions in essence, and uniaxial tension tension force (tensile strain) can reduce hole mobility (hole mobility), and uniaxial compression tension force (compressive strain) then reduces electron mobility (electron mobility).Therefore the implanting ions of germanium (ion implantation) can not reduce the mobility in electronics and electric hole in order to optionally relaxing stress, but this method is because of n-raceway groove and p-channel transistor distance close being difficult to carry out too.
Therefore need a kind of transistor of dealing with the improvement of the problems referred to above in the prior art.
Summary of the invention
Preferred embodiment of the present utility model is to disclose a strain type channel transistor to be formed on the identical semiconductor substrate with another assembly (component).Among first embodiment, this another assembly is a resistance (resistor); Among another embodiment, this another assembly is a transistor; And among other embodiment, this another assembly can be other assembly.
One of the utility model characteristics are to disclose a kind ofly to use same manufacturing process to form the method for an existing resistance and a strain type channel transistor on same substrate.Stress riser is to be defined as it in order to cause the stress of transistor channel region.In the prior art, induced stress is with stress riser guiding stress in transistorized design, and when it is of value to the mobility of first conductive-type transistor, will lower the transistorized mobility of second conductivity type (conduction type).
According to the utility model one preferred embodiment, the semiconductor chip is to comprise the semiconductor substrate, and it is provided with first and second active area (active region).One resistance is formed on first active area; And this resistance that comprises a doped region (doped region) is to be formed between the two-end-point (terminal).One strain type channel transistor is formed at second active area, and this transistor comprises first and second stress riser, and is formed at relative substrate of adjoining with a strain type channel region.
According to another preferred embodiment of the utility model, the semiconductor chip is formed on the semiconductor zone, and having on this semiconductor regions is one first semi-conducting material formation, one first and second active area of a natural lattice constant.One stack (gate stack) is formed on this second active area, and a mask layer (masking layer) is formed on this first active area; After forming this mask layer, at least one recess (recess) is formed on second active area that part is not subjected to stack and covered.One second semi-conducting material is longer than in this recess, and this second semi-conducting material has second a natural lattice constant that differs from this first natural lattice constant.Source electrode and drain region form in this second active area, to form a strain type channel transistor.This mask material is after removing, and the semiconductor assembly then forms in this first active area.
According to another preferred embodiment of the utility model, the semiconductor assembly is to be formed at one to have at the semiconductor-based end of one first semi-conducting material, and this substrate is to comprise second active area that first active area and with a first grid storehouse has a second grid storehouse.One film is formed on this first and second active area, and sept (spacer) is formed on the second grid storehouse sidewall that is positioned at this second active area.The recess of source electrode and drain electrode is the offside that is etched in this second grid storehouse, and is separated by by this sept and a channel region.One second semi-conducting material is to be longer than this source electrode and drain electrode recess.
According to another preferred embodiment of the utility model, the semiconductor assembly is by providing one to have the semiconductor layer of one first active area and second active area and form.One first grid storehouse is formed on this first active area, and a second grid storehouse then is formed on this second active area.One dielectric film (dielectric film) is formed on this first and second active area, and a mask layer be formed at the part be positioned on the dielectric film of this second active area.Disposable spacers is the sidewall that is formed at this first grid storehouse by this dielectric film of anisotropic etching.First and second recess is formed at this first active area, and corresponding arrangement with this disposable spacers substantially.This first and second recess is filled with the semiconductor material, be positioned at the source electrode of second active area of contiguous this second grid storehouse and drain region then via implanting ions.
Description of drawings
Fig. 1 shows that an existing resistance is formed at the diagram of part substrate.
Fig. 2 shows a strain type channel transistor.
Fig. 3 shows that a strain type raceway groove has combining of resistance now with one.
Fig. 4 a-Figure 41 is the flow chart that shows the utility model first embodiment.
Fig. 5 is the PMOS of comparison one an existing PMOS and a compressive tension.
Fig. 6 is the NMOS of comparison one an existing NMOS and a compressive tension.
Fig. 7-Figure 12 shows the integrating step of second and third embodiment of the utility model.
Figure 13-Figure 14 shows the additional step of the utility model second embodiment.
Figure 15-Figure 19 shows the additional step of the utility model the 3rd embodiment.
Symbol description:
100～resistance; 102～substrate; 104～resistance body; 106～isolation structure; 108～electric current; 110～end points; 114～strain type channel transistor; 116～channel region; 118～strain type channel region; 120～source electrode and drain region; 124～resistance; 126～substrate; 128～resistance body; 130～isolation structure; 132～strain type channel transistor; 134～electric current; 136～end points; 138～active area; 140～source electrode and drain region; 142～active area; 144～active area; 146～stack; 148～gate electrode; 150～gate dielectric; 152～gate mask; 154～mask material; 156～mask material; 158～sept or liner; 160～depressed area; 162～semi-conducting material; 164～channel region; 170～sept; The shallow ion doped region of 172～resistance body; 174～silicide; 176～etching stopping layer; 178～sheath; 180～contact hole; 200～substrate; 202～isolation structure; 204～ooze assorted well area; 206～doped well region; 208～active area; 210～active area; 212～stack; 214～gate electrode; 216～gate dielectric; 218～hard mask; 220～disposable type film; 222～mask material; 224～mask material; 226～sept or liner; 228～depressed area; The source electrode and the drain electrode structure of 230～projection; 232～channel region; 234～transistor; 236～transistor; 238～source electrode and drain electrode elongated area; 240～doped region; 244～dielectric medium liner; 246～sept body; 248～sheath; 250～silicide; 252～protective layer; D～recess the degree of depth.
Embodiment
For above-mentioned and other purpose of the present utility model, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
Resistance is often to use in semiconductor integrated circuit, for instance, resistance can be in uses such as for example simulation (analog), mixed mode simulations (mixed mode analog) and numeral (digital) circuit, and can be used in input and the output circuit, or sometimes can be as using as the part input protection circuit so that circuit resisting static discharge (electrostatic discharge to be provided as input and output resistance; ESD) protection of incident.In this example, resistance be in order to cut down static discharge voltage so that absorb and eliminate the energy of static discharge, and the big voltage of thousands of volts grade can appear at resistance two ends that are used in the electrostatic discharge applications.
The resistance of integrated circuit can form by a for example polysilicon layer (poly-crystalline siliconlayer), and can be formed on the monocrystalline silicon layer, for example, resistance can be formed in the substrate of part monocrystalline silicon bulk, or is positioned on the part monocrystalline silicon layer that silicon (silicon-on-insulator) substrate is arranged on the insulating barrier.In an example, a resistance 100 that is formed on part one monocrystal silicon substrate 102 is to show in Fig. 1.Resistance body (resistor body) the 104th with the substrate 102 opposite kenel of mixing, and for example is that shallow trench isolation is from (shallowtrench isolation by an isolation structure (isolation structure) 106; STI) define.As shown in Figure 1, electric current 108 is to flow through to be positioned at the resistance body 104 of 110 of resistance 100 two-end-points.And in resistance body 104, electric current 108 is the relations that are subjected to the current versus voltage of a linearity, and its typical definition is resistance (resistance).For have the knack of this skill personage known to, having a resistance that comprises a single crystal semiconductor resistance body is the characteristic with high stability and low noise (noise) compared to general polycrystalline electric resistance structure.
Provided the structure and the method that form a kind of transistor and a kind of strain type channel transistor in this preferred embodiment, and the method that forms this quasi-resistance with strain type channel transistor is provided.
Fig. 2 shows a strain type channel transistor 114, one first semi-conducting material that wherein is positioned at channel region 116 is because of a configuration that is positioned at second semi-conducting material 118 of part source electrode and drain region 120 is subjected to stress, and this second semi-conducting material has also formed part channel region 116.The lattice constant of this second semi-conducting material is different with the lattice constant of this first semi-conducting material, and therefore a stress is to impose on first semi-conducting material of this channel region, and will refer to be a stress riser after second semi-conducting material.The transistor 114 that comprises a strain type channel region 118 i.e. strain type channel transistor as generally known.As stress riser (Si for example
1-xGe
x) lattice constant during greater than this first semi-conducting material (for example Si), stress riser will cause a compressive tension in transistorized source electrode toward drain directions; And as second semi-conducting material (Si for example
1-yGe
y) lattice constant during less than this first semi-conducting material (for example Si), stress riser will cause a tensile stress in transistorized source electrode toward drain directions.Be the detailed description that discloses relevant strain type channel transistor in the Application No. case 10/379033, and incorporate this paper in the mode of mentioning.
In this preferred embodiment, this first semi-conducting material is a silicon, and second semi-conducting material is silicon Germanium compound (SiGe or Si
1-xGe
x), the strain type channel transistor then is a p-channel transistor.Shared mole fraction (mole fraction) x of germanium can be between about 0.1 to 0.9 scope in the silicon Germanium compound.Among another embodiment, this strain type channel transistor is a n-channel transistor, and first semi-conducting material is a silicon, and second semi-conducting material then is carbon-silicon compound (SiC or Si
1-yC
y), the mole fraction y of carbon is between scope about 0.01 to 0.04 in the carbon-silicon compound.Although Si
1-xGe
xAnd Si
1-yC
yBe available as this second semiconductor layer, but also can use other semi-conducting material equally.For instance, semiconductor alloy (semiconductor alloy) Si for example
1-x-yGe
xC
yCan use as this second semi-conducting material.
A relevant special background will be set forth among first embodiment of the present utility model, that is a kind of existing resistance of integrating is for for example having the method for the resistance of a strain type channel transistor.Among Fig. 3, an existing resistance 124 is formed in first active area 138 that is defined by area of isolation 130 in the part substrate 126, and a strain type channel transistor 132 then is formed at the other part of substrate 126.
Resistance 124 is the resistance bodies 128 that include once mixing, and electric current 134 is then flowed through, and this is positioned at the resistance body 128 of 136 of two resistance end points.Electric current 134 is to be subjected to a resistance when flowing through this resistance body 128, and its value size is the function of many parameters, for example: the size of dopant profile, doping content, layout (layout) and resistance body dimension etc.The dopant profile of doped resistor body 128 be be positioned at it under the dopant profile of semiconductor regions 126 opposite.For instance, the resistance body 128 that resistance 124 can comprise p-type doping is formed on the n-type doped region 138, and this n-type doped region 138 is to can be a n-type doped well region (doped well region) or a n-type doping substrate 126; Its dopant profile also can be opposite, for example n-type doped resistor body 128 is formed on the p-type doped region 138.Generally speaking dopant profiles or profile at the resistance body are heterogeneous, and it can have average doping content between every cubic centimeter 10 of scope
16To 10
19Between.
Fig. 3 illustrates semiconductor bulk substrate 126, and it is preferably a silicon base; Yet other substrate is semiconductor (semiconductor-on-insulator on insulating barrier for example; SOI) substrate also can be used equally.For instance, semiconductor can be silicon substrate of (silicon-on-insulator) on insulating barrier in the substrate on the insulating barrier, and it has a silicon layer on one silica layer, and this silicon oxide layer is to be positioned in the substrate.Contained silicon layer is to can be a relaxed si layer or a strained silicon layer in the substrate of silicon on insulating barrier.
Resistance 124 sections shown in Figure 3 are to show a body region 128, i.e. the resistance body known to, and it is formed on the part substrate 126.Resistance body 128 can define by isolation structure, for example is the fleet plough groove isolation structure 130 shown in Fig. 3.The dopant profile in body region territory 128 is opposite with thereunder semiconductor regions 138 dopant profile.For example, suppose that resistance body 128 is to be doped to the p-kenel, it can be formed in a n-type well area or the n-type substrate.The average doping content of resistance body 128 can be between every cubic centimeter 10 of scope
16To 10
19Between.One electric conducting material can form with the contact hole that resistance 124 end points are provided (contact) 136.
Strain type channel transistor 132 among Fig. 3 is to comprise source electrode and drain region 140 in the opposite side of channel region 164.Channel region 164 is formed by one first semi-conducting material 126, and it is covered by a gate dielectric 150 that is positioned at its top.One gate electrode 148 is on this gate dielectric 150, and the material of this gate electrode 148 is to can be polysilicon, polycrystalline silicon germanium, metal, metal silicide, metal nitride or conducting metal oxide.The sept 170 that comprises one or one above dielectric material is to be formed at this gate electrode 148 sidewalls.Part source electrode and drain region 140 are to comprise one second semi-conducting material 162, and this second semi-conducting material 162 then has second a natural lattice constant that differs from these first material, 126 natural lattice constants.One silicide (silicide) 174 is positioned on this gate electrode 148 and this source electrode and the drain region 140, and on the contrary, this doped region that contains the resistance body is not subjected to silication to maintain the situation of a high impedance.
A kind of resistance kenel that is disclosed in another number case 10/667871 that principle of the present utility model also can be applicable to the applicant is applied for, it will incorporate this paper in the mode of mentioning.Utilize the method for this announcement, resistance can form simultaneously with a strain type channel transistor.
The utility model is to disclose a kind ofly during the existing resistance 124 of formation, to form the method for strain type channel transistor 132 simultaneously on the identical semiconductor-based end 126 in using identical manufacturing or procedure for producing.
According to Fig. 4 a, it shows one in order to set forth the flow process of making a resistance and a strain type channel transistor simultaneously.Semiconductor substrate 126 is provided, and it is preferably a silicon base, and forms isolation structure 130 is positioned at substrate with definition active area.Isolation structure 130 can utilize general shallow trench separation process and form, for instance, for example comprise the trench etched depth bounds and irrigation canals and ditches filled dielectric material (trench fillingdielectric material) is filled steps such as irrigation canals and ditches to about 2000 to 6000 dusts and by chemical vapour deposition technique (chemical vapor deposition), it all shows its profile in Fig. 4 a.This irrigation canals and ditches packing material can for example be a silica.Implanting ions can carry out with form the n-type with and/or p-type well area (not shown).Show two active areas among Fig. 4 a: one has first active area 142 of an existing resistance 124; And second active area 144 with a strain type channel transistor 132; Those active areas can be mutually each other with conductivity type or different conductivity type.Though source/drain regions 140 does not form as yet, but still prior to showing among Fig. 4 a.
Show as Fig. 4 b, a stack 146 be in after be formed on second active area 144.This stack 146 is to comprise a gate electrode 148 on a gate dielectric 150, and can additionally comprise a gate mask (gate mask) 152 on this gate electrode.Introducing the purpose of this gate mask will understand in following narration gradually.
Stack can form by following processing procedure.One gate dielectric 150 is formed on this second active area 144, it is to utilize in any this skill gate dielectric known or that use to form processing procedure to form, for example thermal oxidation method (thermal oxidation), nitriding (nitridation), sputter-deposited method (sputter deposition) or chemical vapour deposition technique.The actual (real) thickness of this dielectric medium 150 (physical thickness) can be between about 5 to 100 dusts of scope.Transistor gate dielectric medium 150 can adopt one of following gate dielectric material or its combination: for example silica, silicon oxynitride or a high-k (high permittivity; High-k) gate dielectric material.
The dielectric material of high-k is preferablely to have a dielectric constant greater than 8.This dielectric material can be following compound or its combination more than one or: aluminium oxide (aluminum oxide; Al
2O
3), hafnium oxide (hafnium oxide; HfO
2), nitrogen hafnium oxide (hafnium oxynitride; HfON), hafnium silicate (hafnium silicate; HfSiO
4), zirconia (zirconium oxide; ZrO
2), nitrogen zirconia (zirconium oxynitride; ZrON), zirconium silicate (zirconium silicate; ZrSiO
4), yittrium oxide (yttrium oxide; Y
2O
3), lanthana (lanthalum oxide; La
2O
3), cerium oxide (ceriumoxide; CeO
2), titanium oxide (titanium oxide; TiO
2) or tantalum oxide (tantalum oxide; Ta
2O
5).In this preferred embodiment, the dielectric medium of this high-k is a hafnium oxide.The silicon equivalent oxide thickness of this dielectric medium 150 (silicon equivalent oxide thickness; EOT) be preferable, be more preferred from less than about 20 dusts approximately less than 50 dusts, and excellent be less than about 10 dusts.And the actual (real) thickness of dielectric medium 150 can be more preferred from less than about 50 dusts less than about 100 dusts, and excellent be less than about 20 dusts.
After gate dielectric 150 formed, a gate material 148 can then be deposited on this gate dielectric 150.This gate material 148 can be polysilicon, polycrystalline silicon germanium, metal, metal silicide, metal nitride, or conducting metal oxide.In this preferred embodiment, electrode 148 is to comprise polysilicon.And for example molybdenum, tungsten, titanium, tantalum, platinum, hafnium metal can be used for the part of electrode 148 tops.Metal nitride can comprise molybdenum nitride, tungsten nitride, titanium nitride and tantalum nitride, but be not be subject to above-mentioned in mentioned metal nitride.Metal silicide can comprise nickle silicide, cobalt silicide, tungsten silicide, titanium silicide, tantalum silicide, platinum silicide and silication erbium, but non-be subject to above-mentioned in mentioned metal silicide.Conducting metal oxide can comprise ruthenium-oxide (ruthenium oxide) or tin indium oxide (indium tinoxide; But non-ly be subject to mentioned conducting metal oxide ITO).
Shown in Fig. 4 c, one first mask material 154 is to be deposited on this stack 146, and this first mask material 154 can be a dielectric medium and for example is silica, silicon oxynitride or silicon nitride.In this preferred embodiment, this first mask material is to comprise the composite bed (siliconnitride on silicon oxide multi-layer) of a silicon nitride on silica.
One second mask material 156 be in after utilize deposition and little shadow technology to form this first mask material 154 that is covered in this first active area 142, be as shown in Fig. 4 d at this moment, it will expose first mask material 154 on this second active area 144.This second mask material 156 can be and comprises any mask material that differs from this first mask material 154.In this preferred embodiment, this second mask material is to comprise a photoresistance.
Then exist down first mask material 154 of this second active area 144 is carried out an etch process in this second mask material 156.This etch process is preferably an anisotropic etching that utilizes the electric paste etching technology, and this step will cause sept or liner (liner) 158 to be formed at stack 146 adjacent places on second active area 144, as shown in Fig. 4 e.This second mask material 156 can remove this moment.
Shown in Fig. 4 f, a recess with depth d is to form in source electrode and drain region one etching, and this etching can be finished by the electric paste etching of a use chlorine or bromine chemical action.The depth d of this recess can be between about 50 to 1000 dusts of scope.One alternative annealing process may be implemented in and helps the silicon migration with the suffered infringement of reparation etching, and is of heap of stone brilliant processing procedure (epitaxy process) afterwards smooth silicon surface a little.
Then, so that small part is filled this depressed area 160, can finish by selectivity building crystal to grow (selective epitaxial growth) by this step through building crystal to grow for one second semi-conducting material 162.Should be to can be chemical vapour deposition technique, long-pending method (the ultra-high vacuum chemical vapor deposition in high vacuum chemical gas phase Shen in order to the of heap of stone brilliant processing procedure of implementing building crystal to grow; UHV-CVD) or molecular beam epitaxy method (molecular beam epitaxy).The building crystal to grow material also can extend in channel region 164 surfaces of transistor 132, forms the source electrode and the drain electrode structure (not shown) of a projection.In first preferred embodiment, this second semi-conducting material 162 is to comprise silicon Germanium compound, and it has a germanium mole fraction between about 0.1 to 0.9; And in second preferred embodiment, lattice mismatch district (lattice-mismatched zone) comprises a carbon-silicon compound, and wherein the carbon mole fraction is between about 0.01 to 0.04.
One alternative cover layer (cap layer) can be through building crystal to grow to cover on this second semi-conducting material 162, and for example, this alternative cover layer can comprise one first semi-conducting material 126, shown in Fig. 4 g.Next form a low-resistance silicide in source electrode and drain region 140 and contain this tectal purpose for helping.
Behind the building crystal to grow, gate mask 152 is promptly removable, and this liner 158 optionally removes.
First and second semi-conducting material of building crystal to grow, it is respectively 126 and 162, and it can carry out original position (in-situ) and mix or non-impurity-doped during building crystal to grow.During the building crystal to grow if mixed, its can in after fabrication steps in mix, and alloy can activate by a rapid thermal annealing processing procedure (rapid thermalannealing process).This alloy can soak and put type implanting ions (plasma immersion ion implantation by existing implanting ions, electricity slurry; PIII), known in gaseous state or solid-state source diffusion (gasor solid source diffusion) or any other this skill or the technology of using and importing.The infringement that any implanting ions caused or decrystallized (amorphization) can through after in high temperature, anneal.At first can carry out one first shallow ion cloth and plant the shallow regional 172 of doped resistor body 128, and form the extension of source/drain regions, as transistor 132 140 in as shown in Fig. 4 h.
Form a sept 170 afterwards, then carry out one second and darker implanting ions again.This second implanting ions also forms the deep source and the drain region 140 of this strain type channel transistor 132 in the lump except that doped resistor body 128.The structure that this stage forms is to show in Fig. 4 i.
The resistance of transistorized source electrode and drain electrode can be by a silicide 174 being overlying on the source/drain regions 140 and is lowered, and for example uses one to aim at silication (self-aligned silicide voluntarily; Salicide) processing procedure or other metal deposition processing procedure.This is to set forth in Fig. 4 j.One mask generally is to comprise monoxide, and it is covered in part not in the substrate of desire generation silicification reaction usually before silicidation process.For instance, when oxide mask is covered in first active area 142 and exposes second active area 144, ensuing silicidation process will form the silicide 174 on the gate electrode 148, and the source electrode of strain type channel transistor 132 and drain region 140, form on this first active area 142 at resistance 124 places and there is no silicide this moment.Although in figure, do not show, can form by silicidation process the contact of resistance 124.
Form a contact etch stop layer (contact etch stop layer) 176 afterwards, then deposit a sheath (passivation layer) 178 again, shown in Fig. 4 k.One contact hole (contact hole) the 180th, in after be stopped on the contact etch stop layer 176 by sheath 178 through etching.To fill this contact hole 180 after one electric conducting material to form conduction contact, as shown in figure 41 to resistance 124 and this strain type channel transistor 132.
In first preferred embodiment, resistance and strain type channel transistor are to be integrated into a single component; And among the embodiment that follows, a strain type channel transistor is then as same non-strain type channel transistor (non-strained channel transistor) and to identical chips.Because a contact etch stop layer is used on this non-strain type channel transistor and may causes stress, and in this context, a non-strain type channel transistor is meant and comprises a transistor that does not use source/drain stressor.
Second embodiment is with regard to improving the integration flow process of complementary type mos devices and narrate in order to make described in this context.As previously mentioned, source electrode and drain region are to fill silicon, germanium, carbon or combination wherein once more after etching.This alloy by a selectivity building crystal to grow processing procedure being deposited on the silicon layer, and therefore generation one stress on the transistor channel between source electrode and the drain electrode.Bigger lattice spacing is to produce a compressive tension, and less lattice spacing will produce a tensile stress.
Fig. 5 and Fig. 6 are the carrier transport factors that shows that respectively compressive tension will increase the transistorized carrier transport factor of PMOS (carrier mobility) and reduce NMOS.The purpose of some embodiment is to separate n-raceway groove and p-channel transistor by the essence (nature) of the stress that changes transistor channel region and intensity in the utility model.It is preferably and causes the compressive tension of one source pole toward drain directions in the raceway groove of a p-channel transistor, and makes the n-channel transistor avoid being compressed tension force.And its same preferable tensile stress that in a n-channel transistor, causes one source pole toward drain directions, and make the p-channel transistor avoid being subjected to tensile stress.
In another preferred embodiment of the utility model be disclose a kind of in conjunction with the strain type channel transistor more than a kind of conductivity type to have the method that minimum carrier transport factor lowers.
With reference to Fig. 7, it shows a processing flow that has the reduction of minimum carrier transport factor and make the method for multiple conductivity type strain type channel transistor.Semiconductor substrate 200 is provided, and it is preferably a silicon base, and forms the active area of isolation structure 202 with the definition substrate.Isolation structure 202 can utilize general shallow trench separation process and form, for instance, for example comprise the trench etched depth bounds to about 2000 to 6000 dusts and by chemical vapour deposition technique with the irrigation canals and ditches filled dielectric material in order to fill step such as irrigation canals and ditches, it all shows its profile in Fig. 7.This irrigation canals and ditches packing material 202 can for example be a silica.Implanting ions can be carried out to form n-type well area 204 or p-type well area 206.Fig. 7 shows two active areas: one has first active area 208 of a p-type strain type channel transistor; And second active area 210 with a n-type channel transistor.
One stack 212 be in after be formed at this first and second active area 208/210, as shown in Figure 7.Stack 212 is to comprise a gate electrode 214 on a gate dielectric 216, and can comprise hard mask (a hard mask) 218 in addition on gate electrode 214.This gate dielectric 216 is can utilize in any this skill gate dielectric known or that use to form processing procedure to form, for example thermal oxidation method, nitriding, sputter-deposited method or chemical vapour deposition technique.The actual (real) thickness of this gate dielectric 216 can be between about 5 to 100 dusts of scope.Gate dielectric 216 can utilize one of following existing gate dielectric material or its combination: the gate dielectric material of silica, silicon oxynitride or a high-k for example.
The dielectric medium of high-k is to have a dielectric constant greater than 8.This dielectric material can be following material or its combination more than one or: aluminium oxide, hafnium oxide, nitrogen hafnium oxide, hafnium silicate, zirconia, nitrogen zirconia, zirconium silicate, yittrium oxide, lanthana, cerium oxide, titanium oxide or tantalum oxide.In this preferred embodiment, the dielectric medium of this high-k is a hafnium oxide.The silicon equivalent oxide thickness of dielectric medium 150 can be preferable approximately less than 50 dusts, be more preferred from less than about 20 dusts, and excellent be less than about 10 dusts; And the actual (real) thickness of this dielectric medium 150 can be more preferred from less than about 50 dusts less than about 100 dusts, and excellent be less than about 20 dusts.
After gate dielectric 216 formed, a gate material 214 can then be deposited on this gate dielectric 216.This gate material 214 can comprise polysilicon, polycrystalline silicon germanium, metal, metal silicide, metal nitride, or conducting metal oxide.In this preferred embodiment, electrode 212 is to comprise polysilicon; For example metals such as molybdenum, tungsten, titanium, tantalum, platinum, hafnium then can be used for electrode 214 upper sections.Metal nitride can comprise molybdenum nitride, tungsten nitride, titanium nitride or tantalum nitride, but be not limited to above-mentioned in mentioned metal nitride.Metal silicide can comprise nickle silicide, cobalt silicide, tungsten silicide, titanium silicide, tantalum silicide, platinum silicide or silication erbium, but non-be subject to above-mentioned in mentioned metal silicide.Conducting metal oxide can comprise ruthenium-oxide or tin indium oxide, but non-ly is subject to mentioned conducting metal oxide.
As shown in Figure 8, a disposable type film 220 is formed on this first and second active area 208/210.This disposable type film can be a dielectric film, utilizes a chemical vapour deposition technique or sputter-deposited and forms.In this preferred embodiment, this disposable type film 220 is between about 10 to 1000 dusts of thickness, and preferable between about 10 to 200 dusts of thickness.
Fig. 9 shows that one first mask material 222 is deposited on first and second active area 208/210, and it can be silica, silicon oxynitride or silicon nitride.In this preferred embodiment, this first mask material is to comprise the composite bed of a silicon nitride on silica.
Figure 10 shows that one second mask material 224 utilizes deposition and little shadow technology to be formed on this second active area 210 and is positioned on first mask material 222 of second active area 210 with covering, and expose first mask material 222 on first active area 208, as shown in figure 10.This second mask material 224 can comprise any mask material that differs from this first mask material 222.In this preferred embodiment, this second mask material is to comprise a photoresistance.
Then exist down first mask material 222 of this second active area 210 is implemented an etch process in this second mask material 224, this etch process is to be preferably an anisotropic etching that utilizes the electric paste etching technology, and this step will cause disposable spacers or liner 226 to be formed at stack 212 adjacent places of this first active area 208, as shown in Figure 11.
After forming this disposable spacers 226, depressed area 228 is etching active area and cardinal principle and these disposable spacers 226 corresponding arrangements, and a silicon etching chemistry then can be as using in the above-mentioned step.This second mask material 224 can remove after etching.
Then as shown in figure 12, so that small part is filled in this depressed area 228, can finish by the selectivity building crystal to grow by this step through building crystal to grow for second semi-conducting material 230.Should can be chemical vapour deposition technique, the long-pending method in high vacuum chemical gas phase Shen or molecular beam epitaxy method in order to the of heap of stone brilliant processing procedure of carrying out building crystal to grow.The building crystal to grow material also can extend in channel region 232 surfaces of this second active area 210, forms source electrode and drain electrode structure 230 just like projection shown in Figure 12.In second preferred embodiment, this second semi-conducting material 230 is to comprise silicon Germanium compound, and it is rough between 0.1 to 0.9 scope that it has a germanium mole fraction; And in second preferred embodiment, the lattice mismatch district comprises carbon-silicon compound, and it has a carbon mole fraction substantially between 0.01 to 0.04.
After the building crystal to grow, this gate mask 218, disposable type liner 226 and this first mask material can form structure as shown in figure 13 through removing.
First semi-conducting material 200 of building crystal to grow can carry out in-situ doped or non-impurity-doped during building crystal to grow.As being mixed during the building crystal to grow, then can in after fabrication steps in mix, but and alloy mat one rapid thermal annealing processing procedure and activating.Alloy can by existing implanting ions, electricity slurry soak put in type implanting ions, gaseous state or solid-state source diffusion or any other this skill known to or the technology used and importing.Infringement that any implanting ions caused or decrystallized can in high temperature, annealing afterwards.
Figure 14 shows semiconductor subassembly after further fabrication process, can carry out one first shallow ion cloth and plant shallow doped region with mix first and second transistor source and drain region, and the extension of formation source/drain regions, as shown in figure 14.
Sept (inclusion region 244 and 246) is the side that is formed at gate electrode 214.In one example, sept forms by chemical vapour deposition (CVD) one dielectric material, for example is silica or silicon nitride, then again by a non-grade to this dielectric material of etching to form the monospace thing; And in the example of Figure 14, this sept is compound sept (composite spacer).One compound sept can comprise a dielectric medium liner 244 and a sept body 246.But these dielectric medium liner 244 mats deposit a dielectric liner material and form, and for example are silica, and this sept body 246 then for example is a silicon nitride, then utilizes a reactive ion etching (reactive ion etching again; RIE) to carry out an anisotropic etching.In the additional embodiments, liner 244 can be monoxide, and sept body 246 then can be mononitride.。
The source electrode of the first transistor 236 and drain region are to utilize implanting ions and form when transistor seconds 234 is covered, and in the preferred embodiment, alloy is arsenic or phosphorus, or comprise both combinations.The source electrode of transistor seconds 234 and drain region are to utilize implanting ions and form when the first transistor 236 is covered, and in the preferred embodiment, then use an alloy for example to be boron.One sheath 248 is to be formed on this first and second active area 208/210.
The 3rd embodiment of the present utility model does an elaboration with reference to Figure 15 to Figure 19.Figure 15 be show structure shown in Figure 12 in after situation after further handling, especially after execution one source/drain ion cloth is as mentioned above planted step.In this example, source/drain regions is the doped portion 240 that comprises second semi-conducting material 230 and this first semi-conducting material 200.
Shown in Figure 16 1 the 3rd protective layer (protective layer) 252, it is preferably a photoresistance, be in after utilize deposition and little shadow technology to be covered on this first active area 208, this second active area 210 is then for exposing.As mentioned above, first mask material 222 of etching second active area 210 will cause disposable spacers 226 to be formed at stack 212 adjacent places on second active area 210, as shown in figure 16.
The doped region 240 of first semi-conducting material 200 is to utilize above-mentioned doping method and form, the infringement that any implanting ions caused or decrystallized can in after high annealing.After then carrying out a deep ion cloth and planting and remove the sept 226 of this first and second transistor 236/234, can implement an other shallow ion cloth and plant, and formed structure is to show in Figure 17 with the source electrode of this first and second transistor 236/234 that mixes and the elongated area 238 that drains.
Figure 18 shows the situation of semiconductor subassembly after further handling.Form a liner 244 and a sept 246 and extra step can be included in stack 212 sidewalls of first and second transistor 236/234, and form an etching stopping layer 248 on this first and second transistor 236/234.
Figure 19 shows another alternative embodiment, and wherein sept 244/246 is to remove.Among one embodiment, the purposes of sept is as shown in Figure 14, for instance, is in order to cover the source/drain extension area, for example light doped region (lightly dopeddrain) when forming dense impure source and drain region.Yet as Figure 16 and shown in Figure 17, dense doped region 240 is before being formed at its extension area 238 formation, so sept is being that prerequisite is next and nonessential with this purpose.Then can comprise not sept or other side wall spacer arranged with this dense doped source and drain region 240 among another embodiment that does not show.
The source electrode of first and second transistor 236/234 and drain electrode for example use one to aim at silicidation process or other metal deposition processing procedure voluntarily can lower by a silicide 250 being covered on gate electrode 214 and the source/drain regions 230/240 with the resistance of grid.Those silicide regions are to show in Figure 18.
Among described two embodiment, a strain type channel transistor is to be formed at identical substrate as a resistance and another transistor; And among another embodiment, three assemblies all can be formed at identical substrate.
Among other embodiment, other assembly can form in the lump with this strain type channel transistor, for example, one capacitor is to set forth in an application number case 10/627,218, and in another example, one diode (diode) or lubistor diode are then in application number case 10/628, set forth in 020, this two application is to incorporate this paper in the mode of mentioning, and utilizes the content that is wherein disclosed.Any structure that is disclosed in above-mentioned can be formed on the same substrate as this strain type channel transistor.
Though the utility model discloses as above with preferred embodiment; right its is not in order to limit the utility model; anyly have the knack of this skill person; in not breaking away from spirit and scope of the present utility model; when doing a little change and retouching, therefore protection range of the present utility model is as the criterion when looking appended the claim scope person of defining.
Claims (16)
1. a semiconductor chip is characterized in that, comprises:
The semiconductor substrate;
One first active area, it is positioned in this substrate;
One second active area, it is positioned in this substrate;
One resistance, it is formed on this first active area, and this resistance is to comprise a doped region that is formed between two-end-point; And
One strain type channel transistor, it is formed on this second active area, and this strain type raceway groove then comprises one first and one second stress riser and is formed at relative substrate of adjoining with a strain type channel region.
2. semiconductor chip according to claim 1, it is characterized in that, this channel region is to comprise first semi-conducting material with one first natural lattice constant, and this first and second stress riser respectively comprises second semi-conducting material with one second natural lattice constant that differs from this first natural lattice constant.
3. semiconductor chip according to claim 2 is characterized in that, this second natural lattice constant is greater than this first natural lattice constant.
4. semiconductor chip according to claim 2 is characterized in that, this first semi-conducting material is to comprise silicon, and this second semi-conducting material is to comprise silicon and germanium.
5. semiconductor chip according to claim 4 is characterized in that, this transistor is a p-channel transistor.
6. semiconductor chip according to claim 2 is characterized in that, this second natural lattice constant is less than this first natural lattice constant.
7. semiconductor chip according to claim 2 is characterized in that, this first semi-conducting material is a silicon, and this second semi-conducting material is to comprise silicon and carbon.
8. semiconductor chip according to claim 7 is characterized in that, this transistor is a n-channel transistor.
9. semiconductor chip according to claim 1 is characterized in that, this doped region is that the dopant profile in the part semiconductor zone under having a dopant profile and being positioned at it is opposite.
10. semiconductor chip according to claim 1 is characterized in that, this doped region is to have a doping content between every cubic centimeter 1016 to 1019 of scope.
11. semiconductor chip according to claim 1 is characterized in that, this doped region is to have a n-type to mix.
12. semiconductor chip according to claim 1 is characterized in that, this doped region is to have a p-type to mix.
13. semiconductor chip according to claim 1, it is characterized in that, this transistor more comprises a gate dielectric on this channel region, and this gate dielectric is to comprise one of following high dielectric constant material or its combination: aluminium oxide, hafnium oxide, nitrogen hafnium oxide, hafnium silicate, zirconia, nitrogen zirconia, zirconium silicate, yittrium oxide, lanthana, cerium oxide, titanium oxide or tantalum oxide.
14. semiconductor chip according to claim 13, it is characterized in that, this transistor more comprises a gate electrode on this gate dielectric, and this gate electrode is formed by one of following material or its combination: polysilicon, polycrystalline silicon germanium, metal, metal silicide, metal nitride, metal silicide or conducting metal oxide.
15. semiconductor chip according to claim 1 is characterized in that, this semiconductor-based end is to comprise the semiconductor-based end of a bulk.
16. semiconductor chip according to claim 1 is characterized in that, this semiconductor-based end is to comprise the substrate of semiconductor on insulating barrier.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US49781903P | 2003-08-26 | 2003-08-26 | |
| US60/497,819 | 2003-08-26 | ||
| US10/729,095 | 2003-12-05 | ||
| US10/729,095 US7112495B2 (en) | 2003-08-15 | 2003-12-05 | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
Publications (1)
| Publication Number | Publication Date |
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| CN2724204Y true CN2724204Y (en) | 2005-09-07 |
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| CNB200410058449XA Active CN100345298C (en) | 2003-08-15 | 2004-08-16 | Semiconductor chips and semiconductor components and their forming methods |
| CN 200420084399 Expired - Lifetime CN2724204Y (en) | 2003-08-26 | 2004-08-16 | Semiconductor chip |
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| CNB200410058449XA Active CN100345298C (en) | 2003-08-15 | 2004-08-16 | Semiconductor chips and semiconductor components and their forming methods |
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| SG (1) | SG152949A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100345298C (en) * | 2003-08-15 | 2007-10-24 | 台湾积体电路制造股份有限公司 | Semiconductor chips and semiconductor components and their forming methods |
| CN101989616A (en) * | 2009-07-30 | 2011-03-23 | 台湾积体电路制造股份有限公司 | Transistor and fabrication method thereof |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5114919B2 (en) * | 2006-10-26 | 2013-01-09 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| US7902032B2 (en) * | 2008-01-21 | 2011-03-08 | Texas Instruments Incorporated | Method for forming strained channel PMOS devices and integrated circuits therefrom |
| US8377784B2 (en) * | 2010-04-22 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a semiconductor device |
| US10330550B2 (en) * | 2015-12-03 | 2019-06-25 | Kistler Holding Ag | Piezoelectric pressure sensor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3443343B2 (en) * | 1997-12-03 | 2003-09-02 | 松下電器産業株式会社 | Semiconductor device |
| SG152949A1 (en) * | 2003-08-26 | 2009-06-29 | Taiwan Semiconductor Mfg | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
-
2004
- 2004-02-11 SG SG200718154-8A patent/SG152949A1/en unknown
- 2004-08-16 CN CNB200410058449XA patent/CN100345298C/en active Active
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100345298C (en) * | 2003-08-15 | 2007-10-24 | 台湾积体电路制造股份有限公司 | Semiconductor chips and semiconductor components and their forming methods |
| CN101989616A (en) * | 2009-07-30 | 2011-03-23 | 台湾积体电路制造股份有限公司 | Transistor and fabrication method thereof |
| CN101989616B (en) * | 2009-07-30 | 2012-07-18 | 台湾积体电路制造股份有限公司 | Transistor and fabrication method thereof |
Also Published As
| Publication number | Publication date |
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| CN100345298C (en) | 2007-10-24 |
| SG152949A1 (en) | 2009-06-29 |
| CN1645616A (en) | 2005-07-27 |
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