CN1622332A - Storing device and manufacturing method therefor - Google Patents
Storing device and manufacturing method therefor Download PDFInfo
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- CN1622332A CN1622332A CN200310118087.4A CN200310118087A CN1622332A CN 1622332 A CN1622332 A CN 1622332A CN 200310118087 A CN200310118087 A CN 200310118087A CN 1622332 A CN1622332 A CN 1622332A
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- 238000004519 manufacturing process Methods 0.000 title claims description 42
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 238000000034 method Methods 0.000 claims abstract description 69
- 238000003860 storage Methods 0.000 claims description 65
- 238000002955 isolation Methods 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims 6
- 230000008569 process Effects 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000006378 damage Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
The memory unit making process includes first forming several pairs of floating grids and several pairs of selecting grids on the active arean of the substrate, with the floating grid pair being between selecting grid pair; then forming dielectric layer on the floating grids and the selecting grids; forming control grids and source lines over the floating grids and the selecting grids and cross these active areas and isolating areas; forming source/drain areas on two sides of the control grids and source lines; covering one thick dielectric layer over the substrate while forming source line contacting windows in the thick dielectric layer for connection with the source/drain areas between source line pair and connecting to at least one of source line pairs.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, and particularly relate to a kind of storage device and manufacture method thereof.
Background technology
Flash memory devices can repeatedly carry out the actions such as depositing in, read, erase of information owing to having, and the advantage that the information that deposits in also can not disappear after outage, thus become PC and electronic equipments such as digital camera egative film, individual accompanied electronic notepad a kind of non-volatile memory of extensively adopting.
Currently used a kind of flash memory cell, stacking gate, source/drain of being made up of floating grid (floating gate) and control gate and the selection transistor that is positioned at stacking gate one side are constituted.Fig. 1 illustrates a kind of vertical view of traditional flash memory.Please refer to Fig. 1, control gate 114b, floating grid (not shown), selection grid 115b and source/drain 116 constitute first array storage unit 150, and control gate 114a, floating grid (not shown), selection grid 115a and source/drain 116 constitute secondary series memory cell 160.Source electrode line 170 among the shared active area 104 that is formed on substrate 100 of the memory cell 150,160 of adjacent two row.
Because source electrode line 170 is doped with source region 104 substrates 100 with the former.Therefore, the doping process that must additionally carry out, its processing step are comparatively complicated.In addition, because source electrode line 170 is formed in the substrate 100, must reserve the required active region area of source electrode line 170 in the substrate 100, and increase along with the increase of development length for fear of the resistance of source electrode line 170, typical technology can promptly increase a contact 180 every 16 to 32, being connected with metal wire on being formed on source electrode line 170, and reach the purpose that reduces resistance by contact 180.Therefore, said method can take more chip area, and makes that element can't the height productive setization.
In addition, because above-mentioned flash memory is in order to be formed on source electrode line 170 in the active area 104 of substrate 100, its isolation structure 102 is made into rectangular block shape.Yet, because the factor of photoetching process, the corner of rectangle isolation structure 102 may sphering, the aligning in case when the pattern of grid 115a, 115b is selected in definition, make a mistake, make and select grid 115b to stride across the corner of corners, as the shown person of dotted line 125b, select the channel width of grid 115b therefore to increase, select the channel width of grid 115a then constant.So, will cause electrically different problem of strange, even memory cell.For fear of this problem, typical way is to reserve certain distance when design element, so that the selection grid can be away from corner.And the method can make the distance of two adjacent memory cell increase, and takies more chip area, and makes that element can't the height productive setization.
Summary of the invention
The object of the present invention is to provide a kind of storage device and manufacture method thereof, its source electrode line can not take the area of wafer.
A further object of the present invention provides a kind of storage device and manufacture method thereof, and it can not need additionally to form contact again, and reduces the resistance of source electrode line.
Another purpose of the present invention provides a kind of storage device and manufacture method thereof, and it can avoid isolation structure corner sphering to problem strange, that even memory cell caused.
The present invention proposes a kind of storage device, this device is arranged in the substrate, dispose the strip isolation structure of a plurality of almost parallels each other in this substrate, and in this substrate, defining a plurality of strip active areas, this element comprises many to word line, a plurality of first grid, many to source electrode line, a plurality of second grid, first, second, third dielectric layer, multiple source, multiple source polar curve contact hole and an insulating barrier.Those word lines wherein, almost parallel ground is across being disposed on those strip isolation structures and those strip active areas each other for it, and those strip active areas are covered part by those to word line and define a plurality of first channel regions.First grid is disposed on first channel region and between substrate and the word line.Between first grid and the active area and and word line between, be separated by with first dielectric layer and second dielectric layer respectively.Each to source electrode line be disposed at each between the word line and with each to the word line almost parallel, and be across on those strip isolation structures and those strip active areas, the height of its height and word line about equally.Those strip active areas are covered part by those to source electrode line and define a plurality of second channel regions.Second grid is disposed on second channel region and between substrate and the source electrode line.Between second grid and the active area and and source electrode line between, be separated by with first dielectric layer and second dielectric layer respectively.All cover the 3rd dielectric layer on word line and the source electrode line.Source/drain regions is disposed among the active area of first grid and second grid both sides.The source electrode line contact hole penetrates the 3rd dielectric layer, and the source/drain regions between the source electrode line is connected, and one of them is electrically connected to source electrode line with each with each, and isolated with an insulating barrier between second grid and the source electrode line contact hole.
The present invention proposes a kind of manufacture method of storage device, the method at first forms the isolation structure of a plurality of strips in substrate, to define the active area of a plurality of strips, then, on each active area, form many to first grid and many to second grid, wherein each to the first grid between each is to second grid.Then, on first grid and second grid, form dielectric layer, on substrate, form one deck conductive layer again, and define this conductive layer, to form across those active areas and those isolation structures simultaneously and to be positioned at the word line of first grid top and across those active areas and those isolation structures and be positioned at above the second grid source electrode line across those active areas and those isolation structures, then, in the substrate of word line and source electrode line both sides, form source/drain regions, on substrate, cover a bed thickness dielectric layer again, and in thick dielectric layer, form the source electrode line contact hole, also one of them is connected to source electrode line with each at least with each the source/drain regions between the source electrode line is connected.
Described according to the embodiment of the invention, above-mentioned storage device comprises flash memory devices, and above-mentioned first grid is a floating grid, and second grid is selection grid.
And described according to the embodiment of the invention, the source electrode line of storage device of the present invention can not take the area of wafer.
In addition, the manufacture method of storage device of the present invention can not need additionally to form contact again, and reduces the resistance of source electrode line.
Moreover, storage device manufacture method of the present invention, strange, the even memory cell problem that can avoid isolation structure corner sphering to be caused.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 illustrates a kind of vertical view of traditional flash memory;
Fig. 2 A to 2D illustrates the vertical view of manufacture method of the memory of first and second embodiment of the present invention;
Fig. 3 A to 3D illustrates along the cutaway view of the manufacture method of the memory of a kind of first embodiment of the invention of the line III-III intercepting of Fig. 2 A to 2D;
Fig. 4 A to 4D illustrates along the cutaway view of the manufacture method of the memory of a kind of first embodiment of the invention of the line IV-IV intercepting of Fig. 2 A to 2D;
Fig. 5 A to 5D illustrates along the cutaway view of the manufacture method of the memory of a kind of second embodiment of the invention of the line III-III intercepting of Fig. 2 A to 2D;
Fig. 6 A to 6D illustrates along the cutaway view of the manufacture method of the memory of a kind of second embodiment of the invention of the line IV-IV intercepting of Fig. 2 A to 2D; And
Fig. 7 illustrates the vertical view of manufacture method of the memory of another embodiment of the present invention.
Description of reference numerals
100,200: substrate
102,202: isolation structure
104,204: active area
108: the contact contact hole
114a, 114b, 214a, 214b: control gate
115a, 115b, 125b, 209a, 209b: select grid
116,216: source/drain regions
150,160: column of memory cells
170,215a, 215b: source electrode line
206,212,220: dielectric layer
208: the strip conductive layer
208a, 208b: floating grid
210a, 210b, 211a, 211b: channel region
217: lining
218: clearance wall
219,219a: etch stop layer
222: the source electrode line contact window
224: the bit line contacting window opening
226: the source electrode line contact hole
228: bit line contacting window
Embodiment
The present invention is illustrated as embodiment with the manufacture method of flash memory.Yet in fact, the present invention is not limited in the making of flash memory.Any those skilled in the art without departing from the spirit and scope of the present invention, can make some and change and retouching.
First embodiment
Fig. 2 A to 2D illustrates the vertical view of manufacture method of the memory of the preferred embodiment of the present invention.Fig. 3 A to 3D illustrates along the cutaway view of the manufacture method of the memory of a kind of first embodiment of the invention of the line III-III intercepting of Fig. 2 A to 2D.Fig. 4 A to 4D illustrates along the cutaway view of the manufacture method of the memory of a kind of first embodiment of the invention of the line IV-IV intercepting of Fig. 2 A to 2D.
Please refer to Fig. 2 A, 3A, 4A, on substrate 200, form isolation structure 202, in substrate 200, to define active area 204.Isolation structure 202 for example forms with shallow groove isolation structure manufacturing method, and it preferably is arranged in the strip of almost parallel each other, to define the active area 204 of a plurality of strips that are not connected in substrate 200.Thereafter, form one dielectric layer 206 on substrate 200, the material of this dielectric layer 206 for example is a silica, and its formation method for example is a thermal oxidation method.Then, on the active area 204 of substrate 200, form the conductive layer 208 of a strip.The method that conductive layer 208 forms for example is with chemical vapor deposition method deposition layer of conductive material layer, for example is polysilicon layer, is patterned into strip with photoetching, etch process again.
, please refer to Fig. 2 B, 3B, 4B, on substrate 200, form another dielectric layer 212, to cover the conductive layer 208 and the dielectric layer 206 of strip thereafter.The material of dielectric layer 212 for example is silica, silica/silicon nitride, silicon oxide/silicon nitride/silicon oxide, or dielectric constant is at the dielectric material more than 8., on substrate 200 form another layer conductive layer, to cover dielectric layer 212 thereafter.Conductive layer 214 for example is made up of polysilicon layer and metal silicide layer, and its formation method for example is a chemical vapor deposition method.Afterwards, carry out photoetching, etch process,, the dielectric layer 206 that is covered on substrate 200 surfaces is come out with conductive layer patternization and simultaneously with strip conductive layer 208 patternings.Conductive layer is patterned into its strip control gate (word line) 214a, 214b and source electrode line 215a, 215b of almost parallel each other, and wherein source electrode line 215a, 215b are between control gate 214a, 214b.In this step, strip conductive layer 208 is patterned into floating grid 208a, 208b and selects grid 209a, 209b.Zone corresponding to floating grid 208a, 208b and selection grid 209a, 209b in the substrate 200 is respectively channel region 210a, 210b, 211a, 211b.
, on substrate 200 form a photoresist mask (not shown), and carry out ion implantation technology, with formation source/drain regions 216 in the substrate 200 of control gate 214a, 214b and source electrode line 215a, 215b both sides thereafter.
Afterwards, please refer to Fig. 2 C, 3C, 4C, at the sidewall formation clearance wall 218 of control gate 214a, 214b and source electrode line 215a, 215b.The formation method of clearance wall 218 for example is to form one deck spacer material layer on substrate 200, for example is silica, then, carries out etch-back again to form it.On substrate 200 form a bed thickness dielectric layer 220 thereafter.The material of thick dielectric layer 220 for example is a silica, and its formation method for example is a chemical vapor deposition method.Afterwards, in thick dielectric layer 220, form source electrode line contact window 222 and bit line contacting window opening 224.Source electrode line contact window 222 exposes on the same active area 204 source/drain regions 216 between two adjacent source electrode line 215 a, the 215b, and expose source electrode line 215a and 215b simultaneously or expose simultaneously source electrode line 215a, 215b one of them.Perhaps, please refer to Fig. 7, source electrode line contact window 222 also can expose several source/drain regions 216 between adjacent several active areas 204a, 204b last two adjacent source electrode line 215a, the 215b, and expose source electrode line 215a and 215b simultaneously or expose simultaneously source electrode line 215a, 215b one of them.The source electrode line contact window 222 of Fig. 7 illustrates and exposes on the two adjacent active areas 204 several source/drain regions 216 between two adjacent source electrode line 215a, the 215b and expose source electrode line 215a and 215b simultaneously.Source electrode line contact window 222 can be a self-aligned contacts window opening, and source electrode line contact window 222 and bit line contacting window opening 224 can see through that single photoetching, etch process form simultaneously or photoetching, etch process by twice form respectively.Preferably, before forming dielectric layer 220, can on substrate 200, form the conformal etch stop layer 219 of one deck, with when the subsequent etch dielectric layer 220 as etch stop layer, avoid clearance wall 218 in etched process, to wreck, select grid 209a, 209b to come out and make.
Thereafter, please refer to Fig. 2 D, 3D, 4D, remove conformal etch stop layer 219 that source electrode line contact window 222 and bit line contacting window opening 224 exposed with and the dielectric layer 206 of below so that source electrode line 215a, 215b with and each other source/drain regions 216 come out.Afterwards, in source electrode line contact window 222 and bit line contacting window opening 224, insert electric conducting material, to form source electrode line contact hole 226 and bit line contacting window 228.The method of inserting electric conducting material for example is to form the electric conducting material that one deck covers dielectric layer 220 and fills up source electrode line contact window 222 and bit line contacting window opening 224 earlier on substrate 200, afterwards, carry out CMP (Chemical Mechanical Polishing) process or etch back process again, remove the electric conducting material on the dielectric layer 220, to form it.
Second embodiment
Fig. 2 A to 2D illustrates the vertical view of manufacture method of the memory of the preferred embodiment of the present invention.Fig. 5 A to 5D illustrates along the cutaway view of the manufacture method of the memory of a kind of second embodiment of the invention of the line III-III intercepting of Fig. 2 A to 2D.Fig. 6 A to 6D illustrates along the cutaway view of the manufacture method of the memory of a kind of second embodiment of the invention of the line IV-IV intercepting of Fig. 2 A to 2D.
The technical method of second embodiment of the invention is roughly identical with first embodiment, and its maximum difference is further the clearance wall between the source electrode line to be removed, so that the spacing between memory cell can effectively be reduced.
Please refer to Fig. 2 A, 5A, 6A, the manufacture method of the storage device of the second embodiment of the present invention is the conductive layer 208 that forms isolation structure 202, dielectric layer 206 and strip according to the method for first embodiment in substrate 200.Please refer to Fig. 2 B, 5B, 6B, afterwards, form dielectric layer 212, control gate 214a, 214b, source electrode line 215a, 215b again, and the conductive layer 208 of strip is patterned as floating grid 208a, 208b and selection grid 209a, 209b, afterwards, in substrate 200, form source/drain regions 216 again.
, form clearance wall 218 before, earlier on substrate 200 form one deck conformal lining (not shown), then, form the spacer material layer more thereafter.Afterwards, eat-back the spacer material layer and the conformal lining that will cover on control gate 214a, 214b and source electrode line 215a, the 215b is removed, with sidewall formation lining 217 and clearance wall 218 at control gate 214a, 214b and source electrode line 215a, 215b.The material of lining 217 is different with the thick dielectric layer 220 of follow-up formation, and it for example is a silicon nitride.
Afterwards, please refer to Fig. 2 C, 5C, 6C, remove the clearance wall 218 between source electrode line 215a, the 215b, then, on substrate 200, form a bed thickness dielectric layer 220 again.Similarly, in follow-up etch process, suffer etched destruction and selection grid 209a, 209b are come out, can before forming dielectric layer 220, on substrate 200, form the conformal etch stop layer 219 of one deck earlier for fear of lining 217.After dielectric layer 220 forms, carry out photoetching and etch process again, in dielectric layer 220, to form source electrode line contact window 222 and bit line contacting window opening 224.Because removed the clearance wall 218 between source electrode line 215a, the 215b, therefore, the spacing between memory cell can effectively be reduced.
, please refer to Fig. 2 D, 5D, 6D thereafter, etch-back etch stop layer 219 so that source electrode line 215a, 215b with and each other source/drain regions 216 come out, and form an insulation wall 219a at the sidewall of source electrode line 215a, 215b.Afterwards, in source electrode line contact window 222 and bit line contacting window opening 224, insert electric conducting material, to form source electrode line contact hole 226 and bit line contacting window 228 with the method that is same as first embodiment.
Please refer to Fig. 2 D, 3D, 4D, storage device of the present invention is arranged in the substrate 200, disposes the strip isolation structure 202 of a plurality of almost parallels each other in the substrate 200, to define a plurality of disjunct strip active areas 204 in substrate 200.This storage device comprises many to strip control gate 214a, 214b, a plurality of floating grid 208a, 208b, many to source electrode line 215a, 215b, a plurality of selection grid 209a, 209b, dielectric layer 206,212 and 220, multiple source 216, multiple source polar curve contact hole 226 and a plurality of insulating barrier 218 (first embodiment) or a plurality of insulating barrier 217 and 219a (second embodiment, Fig. 5 D).Strip control gate 214a, 214b, almost parallel ground is across being disposed on strip isolation structure 202 and the strip active area 204 each other for it, and strip active area 204 Be Controlled grid 214a, 214b cover part and define a plurality of first channel region 210a, 210b.Floating grid 208a, 208b are disposed between the first channel region 210a, the 210b and strip control gate 214a, 214b of substrate 200.Between floating grid 208a, 208b and the substrate 200 and and control gate 214a, 214b between, be separated by with dielectric layer 206 and dielectric layer 212 respectively.Each to source electrode line 215a, 215b be disposed at each between strip control gate 214a, the 214b and with each to strip control gate 214a, 214b almost parallel, and be across on strip isolation structure 202 and the strip active area 204, and the profile of the height of the profile that just rises and falls of its height and surface and strip control gate 214a, 214b and surface height fluctuating about equally.Strip active area 204 is covered part by source electrode line 215a, 215b and defines a plurality of second channel region 211a, 211b.Select grid 209a, 209b, be disposed between the second channel region 211a, the 211b and source electrode line 215a, 215b of substrate 200.Select between grid 209a, 209b and the substrate 200 and and source electrode line 215a, 215b between, be separated by with dielectric layer 206 and dielectric layer 212 respectively.All cover thick dielectric layer 220 on control gate 214a, 214b and source electrode line 215a, the 215b.Source/drain regions 216 is disposed among the active area 204 of control gate 214a, 214b and source electrode line 215a, 215b both sides.Source electrode line contact hole 226, penetrate thick dielectric layer 220, and with each the source/drain regions between source electrode line 215a, the 215b 216 is connected, and one of them is electrically connected to source electrode line 215a, 215b with each, and selects between grid 209a, 209b and the source electrode line contact hole 226 isolated with 219a with insulating barrier 218 or insulating barrier 217.
The height of above-mentioned source electrode line 215a, 215b, between the height of the end face of the height of the end face of selecting grid 209a, 209b and control gate 214a, 214b, and with the height of control gate 214a, 214b about equally.
In addition, above-mentioned storage device also comprises a plurality of clearance walls 218 shown in Fig. 5 D, it is disposed between adjacent control gate 214a and source electrode line 215a or control gate 215b and the source electrode line 214b, 1/2nd thickness of each clearance wall 218 greater than each to the thickness of the insulating barrier between source electrode line 215a, the 215b 217 with the 219a sum of the two.
Please refer to Fig. 2 D, above-mentioned each source electrode line contact hole 226 connect on the single strip active area 204 two adjacent each to the source/drain regions between source electrode line 215a, the 215b 216 and connect at least this to source electrode line 215a, 215b one of them, or, please refer to Fig. 7, above-mentioned each source electrode line contact hole 226 connect on those adjacent more than two strip active areas 204 two adjacent each to those source/drain regions 216 between source electrode line 215a, the 215b and connect at least this to source electrode line 215a, 215b one of them.In addition, source electrode line contact hole 226 can be a self-aligned contacts window.
In addition, above-mentioned storage device also comprises a plurality of bit line contacting windows 228, those bit line contacting windows 228 penetrate dielectric layer 220, and the source/drain regions 216 beyond control gate 214a, the 214b both sides is connected, and the height of the height of the end face of bit line contacting window 228 and source electrode line contact hole 226 about equally with each.
Above-mentioned storage device is selected the grid top to be positioned at, and patterning conductor layer that material identical roughly contour with control gate be as source electrode line, connects source/drain regions in this source electrode line and the substrate with formed source electrode line contact hole in the dielectric layer again.Because being positioned at, source electrode line selects the grid top, therefore, can not take the area of wafer, and owing to the material as source electrode line comprises the metal silicide with low resistance, therefore, do not need to form the source electrode line contact terminal because resistance is excessive again every several memory cell again.Therefore, the present invention can reduce the resistance of source electrode line and can effectively reduce the area of memory cell.
In addition, because each is electrically connected source electrode line, therefore, the source electrode line contact hole only need be electrically connected each, and one of them gets final product to source electrode line.Therefore, the present invention can increase the aligning nargin that forms the source electrode line contact window.
In addition, isolation structure of the present invention is a strip, when definition control gate and source electrode line, can not face because of aligning mistake the tradition employing have corner that isolation structure produced was strange, the problem of even memory cell.So the present invention can not be required to be the distance of avoiding strange, even memory cell because of isolation structure corner sphering and wrong the aligning and reserving away from corner, therefore, the present invention can reduce the spacing between memory cell and the memory cell.
Though the present invention discloses as above with preferred embodiment; yet it is not to be used for limiting the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; can make some and change and retouching, so protection scope of the present invention should be with being as the criterion that claims were defined.
Claims (39)
1. storage device comprises:
A plurality of isolation structures, it is disposed in the substrate, and defines a plurality of active areas in this substrate;
Many to word line, almost parallel ground is across being disposed on those isolation structures and those active areas each other for it, and those strip active areas are covered part by those to word line and define a plurality of first channel regions;
A plurality of first grids are disposed on those first channel regions and between this substrate and those word lines;
Many to source electrode line, each to source electrode line be disposed at each between the word line and with each to the word line almost parallel, and be across on those isolation structures and those active areas, and those active areas are covered part by those to source electrode line and define a plurality of second channel regions;
A plurality of second grids are disposed on those second channel regions, between this substrate and those source electrode lines;
One first dielectric layer is disposed between those active areas and those first grids and between those active areas and those second grids;
One second dielectric layer is disposed between those first grids and those word lines and between those source electrode lines and those second grids;
One the 3rd dielectric layer is disposed on this substrate and covers those word lines and those source electrode lines;
Multiple source is disposed among those active areas of those first grids and those second grid both sides;
Multiple source polar curve contact hole penetrates the 3rd dielectric layer, and those source/drain regions between the source electrode line are connected, and one of them is electrically connected to source electrode line with each with each; And
A plurality of insulating barriers are disposed at respectively between those second grids and those source electrode line contact holes.
2. storage device as claimed in claim 1, wherein those isolation structures are strip, and it is disposed in this substrate each other almost parallel, and its those active areas that defined in this substrate are strip.
3. storage device as claimed in claim 1 wherein is positioned at the height of those source electrode lines on those second grids, between the height of the end face of the height of the end face of those second grids and those word lines.
4. storage device as claimed in claim 3 wherein is positioned at the height of those source electrode lines on those second grids, with the height of those word lines about equally.
5. storage device as claimed in claim 1, wherein the material of those source electrode lines is identical with the material of those word lines.
6. storage device as claimed in claim 1, wherein the material of the material of those source electrode lines and those word lines comprises polysilicon and metal silicide.
7. storage device as claimed in claim 1 also comprises a plurality of clearance walls, is disposed at respectively between these adjacent those word lines and those source electrode lines, and respectively the thickness of half of this clearance wall is greater than each thickness to this insulating barrier between the source electrode line.
8. storage device as claimed in claim 1, wherein respectively this source electrode line contact hole connect on the single active area two adjacent these to this source/drain regions between the source electrode line and connect at least this to source electrode line one of them.
9. storage device as claimed in claim 1, wherein respectively this source electrode line contact hole connect at least on those adjacent more than two active areas two adjacent these to those source/drain regions between the source electrode line wherein two and connect at least this to source electrode line one of them.
10. storage device as claimed in claim 1, wherein respectively this source electrode line contact hole is a self-aligned contacts window.
11. storage device as claimed in claim 1, also comprise a plurality of bit line contacting windows, those bit line contacting windows penetrate the 3rd dielectric layer, and be connected with each those source/drain regions to the word line both sides, and the height of the height of the pre-face of those bit line contacting windows and those source electrode line contact holes about equally.
12. storage device as claimed in claim 1, wherein this storage device comprises flash memory, and those first grids are floating grid, and those second grids are for selecting grid.
13. a storage device, this storage device configuration are on a substrate, it comprises many to word line and multiple source, and this storage device comprises:
Many to source electrode line, each is electrically connected source electrode line, and is disposed at each respectively between the word line, and make those source/drain regions between this word line respectively and respectively between this source electrode line and each to source electrode line between;
One dielectric layer covers those word lines, those source electrode lines and those source/drain regions; And
This storage device also comprises multiple source polar curve contact hole, penetrate this dielectric layer, and one of them is connected to those source/drain regions between the source electrode line with each at least, and one of them is electrically connected to source electrode line with each at least.
14. storage device as claimed in claim 13, wherein the height of those source electrode lines and those word lines about equally.
15. storage device as claimed in claim 13, wherein the material of those source electrode lines is identical with the material of those word lines.
16. storage device as claimed in claim 15, wherein the material of the material of those source electrode lines and those word lines comprises polysilicon and metal silicide.
17. storage device as claimed in claim 13 comprises:
Have a plurality of isolation structures that are strip on this substrate, in this substrate, to define a plurality of strip active areas; And
Each source electrode line contact hole connect on the single active area two adjacent these to this source/drain regions between the source electrode line and connect at least this to source electrode line one of them.
18. storage device as claimed in claim 13 comprises:
Have a plurality of isolation structures that are strip on this substrate, in this substrate, define a plurality of strip active areas; And
Respectively this source electrode line contact hole connect at least on those adjacent more than two active areas two adjacent these to those source/drain regions between the source electrode line wherein two and connect at least this to source electrode line one of them.
19. storage device as claimed in claim 13, wherein this source electrode line contact hole is a self-aligned contacts window.
20. storage device as claimed in claim 13, wherein this storage device also comprises several bit line contacting windows, those bit line contacting windows penetrate this dielectric layer, and be connected with each those source/drain regions to the word line both sides, wherein the height of the height of the end face of those bit line contacting windows and those source electrode line contact holes is about equally.
21. storage device as claimed in claim 13, wherein this storage device also comprises:
A plurality of first grids are disposed between this substrate and those word lines;
A plurality of second grids are disposed between this substrate and those source electrode lines;
One first dielectric layer is disposed between this substrate and those first grids and between this substrate and those second grids; And
One second dielectric layer is disposed between those first grids and those word lines and between those source electrode lines and those second grids.
22. storage device as claimed in claim 21, wherein this storage device is a flash memory, and those first grids are floating grid, and those second grids are for selecting grid.
23. the manufacture method of a storage device, this storage device are formed on the substrate, it comprises many to word line and multiple source, and this method comprises:
Between each is to word line, form the pair of source polar curve that is electrically connected respectively, make those source/drain regions between respectively this word line and respectively these source electrode line both sides; And
On this substrate, form a dielectric layer;
Form one source pole line contact hole respectively in to this dielectric layer between the source electrode line, one of them is electrically connected to source electrode line with each at least respectively to respectively this source/drain regions between the source electrode line to make each in each.
24. the manufacture method of storage device as claimed in claim 23, the step that wherein forms those word lines and those source electrode lines are that patterning is with one deck conductive layer.
25. the manufacture method of storage device as claimed in claim 23 also is included in and forms a plurality of bit line contacting windows in this dielectric layer, comprising:
In this dielectric layer, form multiple source polar curve contact window simultaneously and a plurality of bit line connects the window opening with same photoetching, etching step; And
Connect in those source electrode line contact windows and those bit lines and to insert an electric conducting material in the window opening, connect window to form those source electrode line contact holes and those bit lines.
26. the manufacture method of storage device as claimed in claim 23 also is included in and forms a plurality of bit line contacting windows in this dielectric layer, comprising:
Carry out one first photoetching, etching step, in this dielectric layer, to form multiple source polar curve contact window;
Carry out one second photoetching, etching step, with this dielectric layer in form a plurality of bit line contacting window openings; And
Connect in those source electrode line contact windows and those bit lines and to insert an electric conducting material in the window opening, connect window to form those source electrode line contact holes and those bit lines.
27. the manufacture method of storage device as claimed in claim 23, wherein those source electrode line contact holes are inserted electric conducting material again and are formed by form multiple source polar curve contact window in this dielectric layer, comprising:
Each source electrode line contact window is a self-aligned contacts window opening, and forming those self-aligned contacts window openings and forming between the step of this dielectric layer, also is included on this substrate and forms a conformal etch stop layer, and the step that forms those source electrode line contact windows comprises:
With this conformal etch stop layer is stop layer, etching is removed and is covered each to this dielectric layer on those source/drain regions between the source electrode line, and remove at least and cover each to source electrode line this dielectric layer on one of them, to form those self-aligned contacts window openings; And
This conformal etch stop layer that those self-aligned contacts window openings of etch-back are exposed, with expose those source/drain regions and expose at least each to source electrode line one of them.
28. the manufacture method of storage device as claimed in claim 23 wherein after forming those word lines and those source electrode lines, forms the sidewall that this dielectric layer also is included in those word lines and those source electrode lines before and forms a plurality of clearance walls, comprising:
Before forming those clearance walls, the side-walls that also is included in those word lines and those source electrode lines forms a lining, and after forming those clearance walls, also comprise removal each to those clearance walls between the source electrode line to expose this lining.
29. the manufacture method of storage device as claimed in claim 23 comprises:
On this substrate, form a plurality of strip isolation structures, a plurality ofly be strip and disjunct active area in this substrate, to define, and those word lines stride across those strip isolation structures and those are strip and disjunct active area.
30. the manufacture method of a storage device comprises:
In a substrate, form a plurality of strip isolation structures, in this substrate, to define a plurality of strip active areas, wherein each those active area comprise many to first channel region of arranged and many to second channel region with arranged, wherein each to second channel region between each is to second channel region;
On this substrate, form one first dielectric layer;
On this first dielectric layer of this first channel region respectively, form a first grid, and on this first dielectric layer of this second channel region respectively, form a second grid simultaneously;
On this first grid respectively and respectively, form one second dielectric layer on this second grid;
On this substrate, form one first conductive layer;
Define this first conductive layer, many to form simultaneously to word line and many to source electrode line, respectively this word line is across those strip isolation structures and those strip active areas and cover those second dielectric layers on those first channel regions of same row, and each to source electrode line between each is to word line, and across those strip isolation structures and those strip active areas and cover those second dielectric layers on those second channel regions of same row;
In this substrate of those word lines and those source electrode line both sides, form multiple source;
Form a clearance wall in this word line respectively and the sidewall of this source electrode line respectively;
On this substrate, form one the 3rd dielectric layer;
Form multiple source polar curve contact window layer by layer in the 3rd dielectric, those source electrode line contact windows expose each to those source/drain regions between the source electrode line and expose each at least to one of source electrode line; And
In those source electrode line contact windows, insert an electric conducting material, to form multiple source polar curve contact hole, those source/drain regions between the source electrode line are connected and one of source electrode line are connected at least with each with each.
31. the manufacture method of storage device as claimed in claim 30, wherein respectively this source electrode line contact window is a self-aligned contacts window opening, and forming those clearance walls and forming between the step of the 3rd dielectric layer, also is included on this substrate and forms a conformal etch stop layer, and the step that forms those source electrode line contact windows comprises:
With this conformal etch stop layer is stop layer, etching is removed and is covered each to the 3rd dielectric layer on those source/drain regions between the source electrode line, and remove at least and cover each to the 3rd dielectric layer of source electrode line on one of them, to form those self-aligned contacts window openings; And
This conformal etch stop layer that those self-aligned contacts window openings of etch-back are exposed, with expose those source/drain regions and expose at least each to source electrode line one of them.
32. the manufacture method of storage device as claimed in claim 30, wherein after forming those word lines and those source electrode lines, with before forming those clearance walls, the side-walls that also is included in those word lines and those source electrode lines forms a lining, and after forming those clearance walls, also comprise removal each to those clearance walls between the source electrode line to expose this lining.
33. the manufacture method of storage device as claimed in claim 30, wherein respectively this source electrode line contact window is a self-aligned contacts window opening, and remove each to those clearance walls between the source electrode line after, in the 3rd dielectric layer, forms also to be included in before those source electrode line contact windows and form a conformal etch stop layer on this substrate, and the step that forms those source electrode line contact windows comprises:
With this conformal etch stop layer is stop layer, etching is removed and is covered each to the 3rd dielectric layer on those source/drain regions between the source electrode line, and remove at least and cover each to the 3rd dielectric layer of source electrode line on one of them, to form those self-aligned contacts window openings; And
This conformal etch stop layer that those self-aligned contacts window openings of etch-back are exposed, with expose those source/drain regions and expose at least each to source electrode line one of them.
34. the manufacture method of storage device as claimed in claim 30, wherein respectively this source electrode line contact window expose on the single strip active area two adjacent these to this source/drain regions between the source electrode line and expose at least this to source electrode line one of them.
35. the manufacture method of storage device as claimed in claim 30, wherein respectively this source electrode line contact window expose on those adjacent more than two strip active areas two adjacent these to those source/drain regions between the source electrode line wherein two and expose at least this to source electrode line one of them.
36. the manufacture method of storage device as claimed in claim 30 also comprises:
In the 3rd dielectric layer, form a plurality of bit line contacting window openings, so that each bit line contacting window exposes each respectively this source/drain regions to the word line both sides; And
In each bit line contact window, insert another electric conducting material,, make each bit line contacting window connect each each source/drain regions the word line both sides to form a plurality of bit line contacting windows.
37. the manufacture method of storage device as claimed in claim 36, wherein those bit line contacting window openings and those source electrode line contact windows form simultaneously.
38. the manufacture method of storage device as claimed in claim 36, wherein those bit line contacting window openings and those source electrode line contact windows are non-forms simultaneously.
39. the manufacture method of storage device as claimed in claim 30, wherein the formation step of those first grids and those second grids comprises:
On this substrate, form one second conductive layer;
Define this second conductive layer, on each strip active area, to form a strip second conductive layer respectively; And
After forming this second dielectric layer, this first conductive layer, in this first conductive layer of definition, define this strip second conductive layer once more, to form those first grids and those second grids.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2003101180874A CN100353555C (en) | 2003-11-24 | 2003-11-24 | Storing device and manufacturing method therefor |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2003101180874A CN100353555C (en) | 2003-11-24 | 2003-11-24 | Storing device and manufacturing method therefor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102361030A (en) * | 2011-09-02 | 2012-02-22 | 长沙艾尔丰华电子科技有限公司 | One-time programmable memory cell array and manufacturing method thereof |
| CN111048512A (en) * | 2018-10-15 | 2020-04-21 | 联华电子股份有限公司 | Memory structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4083975B2 (en) * | 2000-12-11 | 2008-04-30 | 株式会社ルネサステクノロジ | Semiconductor device |
| US6646924B1 (en) * | 2002-08-02 | 2003-11-11 | Macronix International Co, Ltd. | Non-volatile memory and operating method thereof |
| JP3840193B2 (en) * | 2003-03-31 | 2006-11-01 | 株式会社東芝 | Semiconductor memory device |
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2003
- 2003-11-24 CN CNB2003101180874A patent/CN100353555C/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102361030A (en) * | 2011-09-02 | 2012-02-22 | 长沙艾尔丰华电子科技有限公司 | One-time programmable memory cell array and manufacturing method thereof |
| CN111048512A (en) * | 2018-10-15 | 2020-04-21 | 联华电子股份有限公司 | Memory structure |
| CN111048512B (en) * | 2018-10-15 | 2022-08-05 | 联华电子股份有限公司 | Memory structure |
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| CN100353555C (en) | 2007-12-05 |
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