CN1621337A - Method for preparing chip of MEMS electrically controlled dynamic gain equalizer - Google Patents
Method for preparing chip of MEMS electrically controlled dynamic gain equalizer Download PDFInfo
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- CN1621337A CN1621337A CNA2004100931442A CN200410093144A CN1621337A CN 1621337 A CN1621337 A CN 1621337A CN A2004100931442 A CNA2004100931442 A CN A2004100931442A CN 200410093144 A CN200410093144 A CN 200410093144A CN 1621337 A CN1621337 A CN 1621337A
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Abstract
The preparation process of the MEMS electrically controlled dynamic gain equalizer chip includes 14 technological steps: preparing the first silicon chip and the second silicon chip, depositing the first polysilicon layer and the second polysilicon layer, etching off the second polysilicon layer, eliminating the first glue layer, depositing the first SiN film and the second SiN film, depositing the third polysilicon layer and the fourth polysilicon layer, etching off the fourth polysilicon layer, preparing the fiber locating slot etching notch and the first and the second electrode etching notches, depositing SiO2 branch arm, preparing composite optical film F-P cavity and electrode hole, sputtering high reflectivity aluminum alloy film, bonding, and preparing fiber locating slot. The present invention has the advantages of great optical signal grain regulating range, high reliability, small product size and compatibility with large scale IC manufacture process.
Description
Technical field
The present invention relates to a kind of MEMS electrically controlled dynamic gain equalizer chip production method, definitely say, relate to the CWDM electrically controlled dynamic gain equalizer chip production method that a kind of MEMS of utilization technology realizes, belong to the microelectronic component preparing technical field.
Background technology
CWDM electrically controlled dynamic gain equalizer chip adopts micro-optic and micromechanics anti-reflection structure, its essence is a kind of new electronic control light intensity control spare, is a kind of core devices in the modern broadband light net.In coarse wavelength division multiplexer optical fiber optical-fiber network (CWDM Fiber Optical Networks), be used for adjusting the power of balanced each channel optical signal.Can also be used for simultaneously the optical power loss of the long Distance Transmission of analog optical fiber or the dynamic range of detected transmission system.Traditional opto-mechanical equalizer wide dynamic range (＞50db), but volume is big, the response time is grown (~ 1 second), power consumption is big, so limited its application prospect.The report of relevant micromechanics adjustable optical equalizer is extremely many in recent years, wherein mainly utilize the deflection of speculum and make in the majority that the luminous power that reflexes to output optical fibre changes, this equalizer has realized that volume is little, but response speed slow (Millisecond) awaits to improve.
Summary of the invention
The present invention aims to provide a kind of MEMS electrically controlled dynamic gain equalizer chip production method.
Technical scheme of the present invention is that this preparation method comprises 14 technological operation steps: prepare first silicon chip 0 and second silicon chip 1; Silicon dioxide thin film growth; Deposit first polysilicon layer 4 and second polysilicon layer 4 '; Etching off second polysilicon layer 4 '; Remove the first positive glue 5; Deposit first silicon nitride film 6 and second silicon nitride film 6 '; Deposit the 3rd polysilicon layer 7 and the 4th polysilicon layer 7 '; Etching off the 4th polysilicon layer 7 '; The preparation fiber orientation groove corrosion mouth 8 and the first electrode corrosion mouth 9, the second electrode corrosion mouth 9 '; Deposit silicon dioxide support arm 10; Preparation complex optical film F-P cavity 11 and electrode hole 12; The high reflective film 13 of sputter alloy aluminum; Bonding; Preparation fiber orientation groove 14 gets MEMS electrically controlled dynamic gain equalizer chip.
Now be described with reference to the accompanying drawings technical scheme of the present invention.A kind of MEMS electrically controlled dynamic gain equalizer chip production method is characterized in that operating procedure:
The first step prepares first silicon chip 0 and second silicon chip 1
The second one-step growth silica membrane
Alternately adopting the dry-oxygen oxidation and the wet-oxygen oxidation technology of thermal oxidation process is first silica membrane 2, second silica membrane 2 ' and the 3rd silica membrane 3, the 4th silica membrane 3 ' of 530 ± 50nm at first silicon chip 0 and second silicon chip, 1 two-sided equal growth thickness respectively;
The 3rd step deposit first polysilicon layer 4 and second polysilicon layer 4 '
Adopt low-pressure chemical vapor phase deposition, be first silica membrane 2 and second silica membrane 2 ' surface difference deposit first polysilicon layer 4 and second polysilicon layer 4 ' of LPCVD method at first silicon chip 0, thickness is 800nm ± 20nm, test diffusion sheet resistance Rs is 45～50 Ω/, and first polysilicon layer 4 and second polysilicon layer 4 ' are the arsenic-doped polysilicon layers;
The 4th step etching off second polysilicon layer 4 '
On first polysilicon layer 3, be coated with the first positive glue 5, adopt wet method etching off second polysilicon layer 4 ';
The 5th step was removed the first positive glue 5
Adopt acetone, under 40 degrees celsius, remove the first positive glue 5;
The 6th step deposit first silicon nitride film 6 and second silicon nitride film 6 '
Adopting low-pressure chemical vapor phase deposition technology, is first silicon nitride film 6 and second silicon nitride film 6 ' of 153nm ± 5nm at the two-sided deposition thickness of first silicon chip 0;
The 7th step deposit the 3rd polysilicon layer 7 and the 4th polysilicon layer 7 '
Adopt low-pressure chemical vapor phase deposition technology, two-sided deposition thickness at first silicon chip 0 is the 3rd polysilicon layer 7 and the 4th polysilicon layer 7 ' of 415nm ± 5nm, and first polysilicon layer 4, first silicon nitride film 6 and the 3rd polysilicon layer 7 that have prepared are together as complex optical film;
The 8th step etching off the 4th polysilicon layer 7 '
Be coated with the second positive glue 5 ' in first silicon chip, 0 front, acetone is adopted in etching off the 4th polysilicon layer 7 ' back, removes the second positive glue 5 ' under 40 degrees celsius;
The 9th step preparation fiber orientation groove corrosion mouth 8 and the first electrode corrosion mouth 9, the second electrode corrosion mouth 9 '
Be coated with the 3rd positive glue 5 at the back side of first silicon chip 0 "; adopt M5 fiber orientation groove and electrode mask exposure back to develop; at the 3rd positive glue 5 " go up the pattern of formation fiber orientation groove corrosion 8 and the first electrode corrosion mouth 9, the second electrode corrosion mouth 9 ', adopt the KOH reactive ion etching then, be that the RIE method erodes second silicon nitride film 6 ' in fiber orientation groove corrosion mouth 8 and the first electrode corrosion mouth 9, the second electrode corrosion mouth 9 ', expose second silica membrane 2 ', last plasma is removed the 3rd positive glue 5 ";
The tenth step deposit silicon dioxide support arm 10
Strengthen chemical gaseous phase at first silicon chip, 0 front using plasma, promptly PECVD depositing technics growthing silica support arm 10, and thickness is 1050nm ± 50nm;
The 11 step preparation complex optical film F-P cavity 11 and electrode hole 12
Be coated with the 4th positive glue 5_ in the front of first silicon chip 0; adopt M1 cavity mask exposure back to develop; on the 4th positive glue 5_, form the pattern of complex optical film F-P cavity 11 and electrode hole 12; be not subjected to the silicon dioxide support arm 10 of the 4th positive glue 5_ protection then with the corrosive liquid corrosion; remove at last the 4th positive glue 5_, the prescription of corrosive liquid is the HF of concentration 48%: NH
4F: H
2O=3ml: 6g: 10ml, remove the 4th positive glue 5_ at last:
The high reflective film 13 of the 12 step sputter alloy aluminum
Do the bottom electrode of prepared equalizer chip at the high reflective film 13 of second silicon chip, 1 surface sputtering alloy aluminum;
The 13 step bonding
With first silicon chip, 0 positive and second silicon chip, 1 front bonding under environment purification, get cavity body;
The 14 step preparation fiber orientation groove 14
Utilize first silica membrane 2 in the corrosive liquid corrosion fiber orientation groove corrosion mouth 8 and the first electrode corrosion mouth 9, the second electrode corrosion mouth 9 ', the prescription of corrosive liquid is the HF of concentration 48%: NH
4F: H
2O=3ml: 6g: 10ml, expose first silicon chip 0, utilize the anisotropy of silicon then, adopt concentration 25%TMAOH solution under 85 degrees centigrade condition, to corrode first silicon chip 0, time is 13 hours, expose the complex optical film and first polysilicon layer 4, first polysilicon layer 4 is double does the prepared equalizer chip power utmost point, adopt the complex optical film on the mechanical means removal electrode hole 12 then, bottom electrode alloy aluminum film 13 can be drawn from the surface, get MEMS electrically controlled dynamic gain equalizer chip.
Whole prepared process is shown in Fig. 1～14.
The present invention has following outstanding effect:
1. employing complex optical film, for the adjustable range of wavelength 1510nm, 1530nm, 1550nm, 1570nm optical signal gain greater than 15dB.
2. employing bonding technology improves product reliability.
3. cost is low, is suitable for producing in batches.
4. small product size is little, and is compatible mutually with the manufacture craft of large scale integrated circuit.
Description of drawings
Fig. 1 (a) is the schematic diagram of preparation first silicon chip 0.
Fig. 1 (b) is the schematic diagram of preparation second silicon chip 1.
Fig. 2 (a) is at first silicon chip, 0 silicon dioxide thin film growth schematic diagram.
Fig. 2 (b) is at second silicon chip, 1 silicon dioxide thin film growth schematic diagram.
Fig. 3 is that first polysilicon layer 4 of arsenic and the schematic diagram of second polysilicon layer 4 ' are mixed in deposit.
Fig. 4 is the schematic diagram of corrosion second polysilicon layer 4 '.
Fig. 5 is the schematic diagram of the first positive glue 5.
Fig. 6 is the schematic diagram of deposit first silicon nitride film 6 and second silicon nitride film 6 '.
Fig. 7 is the schematic diagram of deposit the 3rd polysilicon layer 7 and the 4th polysilicon layer 7 '.
Fig. 8 (a) is the schematic diagram of etching off the 4th polysilicon layer 7 '.
Fig. 8 (b) is a schematic diagram of removing the second positive glue 5 '.
Fig. 9 (a) is coated with the 3rd positive glue 5 " schematic diagram.
Fig. 9 (b) is the schematic diagram of preparation fiber orientation groove corrosion mouth 8 and the first electrode corrosion mouth 9, the second electrode corrosion mouth 9 '.
Fig. 9 (c) removes the 3rd positive glue 5 " schematic diagram.
Figure 10 is the schematic diagram of deposit silicon dioxide support arm 10.
Figure 11 (a) is the schematic diagram that is coated with the 4th positive glue 5_.
Figure 11 (b) is the schematic diagram of preparation complex optical film F-P cavity 11 and electrode hole 12.
Figure 11 (c) is a schematic diagram of removing the 4th positive glue 5_.
Figure 12 is the high reflective film 13 of sputter alloy aluminum, the i.e. schematic diagram of bottom electrode.
Figure 13 is a bonding technology, gets the schematic diagram of cavity body.
Figure 14 is the schematic diagram of preparation fiber orientation groove 14.
Embodiment
In the foregoing invention content, technical scheme of the present invention is illustrated in detail that this scheme is exactly an embodiment, just no longer repeat here.The present invention is particularly suitable for being used for preparing MEMS electrically controlled dynamic gain equalizer chip.Only need four to 16 equalizer unit designs on chip piece, just can make array MEMS electrically controlled dynamic gain equalizer chip.This device can constitute a kind of novel C WDM optical fiber communication Dynamic Gain Equalizer composite module, in coarse wavelength division multiplexer optical fiber optical-fiber network (the coarse wavelength division multiplexer system in the metropolitan area network), be used for adjusting the power of each channel signal, can also be used for the dynamic range of long Distance Transmission of analog optical fiber or detected transmission system etc. simultaneously.MEMS electrically controlled dynamic gain equalizer of the present invention is according to the interference of light principle, utilize electrostatic drive signal control suspension laminated film, when changing the air chamber size, make the output light intensity under the effect of control voltage, produce decay, reach the effect of controlled light intensity gain.For the adjustable range of wavelength 1510nm, 1530nm, 1550nm, 1570nm optical signal gain greater than 15dB.
Claims (1)
1. MEMS electrically controlled dynamic gain equalizer chip production method is characterized in that operating procedure:
The first step prepares first silicon chip (0) and second silicon chip (1)
First silicon chip (0) adopts n type＜100〉crystal orientation, and second silicon chip (1) crystal orientation can be chosen wantonly, and the thickness of first silicon chip (0) and second silicon chip (1) is 540 μ m ± 5 μ m, and resistivity is 10 Ω cm;
The second one-step growth silica membrane
Alternately adopting the dry-oxygen oxidation and the wet-oxygen oxidation technology of thermal oxidation process is first silica membrane (2), second silica membrane (2 ') and the 3rd silica membrane (3), the 4th silica membrane (3 ') of 530 ± 50nm at first silicon chip (0) and the two-sided equal growth thickness of second silicon chip (1) respectively;
The 3rd step deposit first polysilicon layer (4) and second polysilicon layer (4 ')
Adopt low-pressure chemical vapor phase deposition, be first silica membrane (2) and second silica membrane (2 ') surface difference deposit first polysilicon layer (4) and second polysilicon layer (4 ') of LPCVD method at first silicon chip (0), thickness is 800nm ± 20nm, test diffusion sheet resistance R
sBe 45～50 Ω/, first polysilicon layer (4) and second polysilicon layer (4 ') are the arsenic-doped polysilicon layers;
The 4th step etching off second polysilicon layer (4 ')
On first polysilicon layer 3, be coated with the first positive glue (5), adopt wet method etching off second polysilicon layer (4 ');
The 5th step was removed the first positive glue (5)
Adopt acetone, under 40 degrees celsius, remove the first positive glue (5);
The 6th step deposit first silicon nitride film (6) and second silicon nitride film (6 ')
Adopting low-pressure chemical vapor phase deposition technology, is first silicon nitride film (6) and second silicon nitride film (6 ') of 153nm ± 5nm at the two-sided deposition thickness of first silicon chip (0);
The 7th step deposit the 3rd polysilicon layer (7) and the 4th polysilicon layer (7 ')
Adopt low-pressure chemical vapor phase deposition technology, two-sided deposition thickness at first silicon chip (0) is the 3rd polysilicon layer (7) and the 4th polysilicon layer (7 ') of 415nm ± 5nm, and first polysilicon layer (4) that has prepared, first silicon nitride film (6) and the 3rd polysilicon layer (7) are together as complex optical film;
The 8th step etching off the 4th polysilicon layer (7 ')
Be coated with the second positive glue (5 '), etching off the 4th polysilicon layer (7 ') then in first silicon chip (0) front;
The 9th step preparation fiber orientation groove corrosion mouth (8) and the first electrode corrosion mouth (9), the second electrode corrosion mouth (9 ')
Be coated with the 3rd positive glue (5 ") at the back side of first silicon chip (0); adopt M5 fiber orientation groove and electrode mask exposure back to develop; go up the formation fiber orientation groove corrosion mouth (8) and the first electrode corrosion mouth (9) at the 3rd positive glue (5 "), the pattern of the second electrode corrosion mouth (9 '), adopt the KOH reactive ion etching then, be that the RIE method erodes the fiber orientation groove corrosion mouth (8) and the first electrode corrosion mouth (9), second silicon nitride film (6 ') in the second electrode corrosion mouth (9 '), expose second silica membrane (2 '), last plasma is removed the 3rd positive glue (5 ");
The tenth step deposit silicon dioxide support arm (10)
Strengthen chemical gaseous phase at first silicon chip (0) front using plasma, i.e. PECVD depositing technics growthing silica support arm (10), thickness is 1050nm ± 50nm;
The 11 step preparation complex optical film F-P cavity (11) and electrode hole (12)
Be coated with the 4th positive glue (5_) in the front of first silicon chip (0); adopt M1 cavity mask exposure back to develop; go up the pattern that forms complex optical film F-P cavity (11) and electrode hole (12) at the 4th positive glue (5_); be not subjected to the silicon dioxide support arm (10) of the 4th positive glue (5_) protection then with the corrosive liquid corrosion; remove at last the 4th positive glue (5_), the prescription of corrosive liquid is the HF of concentration 48%: NH
4F: H
2O=3ml: 6g: 10ml removes the 4th positive glue (5_) at last;
The 12 step high reflective film of sputter alloy aluminum (13)
Do the bottom electrode of prepared equalizer chip at the high reflective film of second silicon chip (1) surface sputtering alloy aluminum (13);
The 13 step bonding
Positive and second silicon chip (1) front bonding under environment purification gets cavity body with first silicon chip (0);
The 14 step preparation fiber orientation groove (14)
Utilize first silica membrane (2) in the corrosive liquid corrosion fiber orientation groove corrosion mouth (8) and the first electrode corrosion mouth (9), the second electrode corrosion mouth (9 '), the prescription of corrosive liquid is the HF of concentration 48%: NH
4F: H
2O=3ml: 6g: 10ml, expose first silicon chip (0), utilize the anisotropy of silicon then, adopt concentration 25%TMAOH solution under 85 degrees centigrade condition, to corrode first silicon chip (0), time is 13 hours, expose complex optical film and first polysilicon layer (4), first polysilicon layer (4) is double does the prepared equalizer chip power utmost point, adopt the complex optical film on the mechanical means removal electrode hole (12) then, bottom electrode alloy aluminum film (13) can be drawn from the surface, get MEMS electrically controlled dynamic gain equalizer chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100931442A CN1280178C (en) | 2004-12-17 | 2004-12-17 | Method for preparing chip of MEMS electrically controlled dynamic gain equalizer |
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| CNB2004100931442A CN1280178C (en) | 2004-12-17 | 2004-12-17 | Method for preparing chip of MEMS electrically controlled dynamic gain equalizer |
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| CN1280178C CN1280178C (en) | 2006-10-18 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101276020B (en) * | 2007-03-28 | 2010-04-14 | 中国科学院微电子研究所 | Method for preparing optical demultiplexer chip of micro-electromechanical system |
| CN102431956A (en) * | 2011-11-29 | 2012-05-02 | 北京大学 | Monolithic integration processing method for unequal-height silicon structure and integrated circuit |
| CN102026909B (en) * | 2008-05-14 | 2013-11-20 | 罗伯特·博世有限公司 | Method for producing chips |
-
2004
- 2004-12-17 CN CNB2004100931442A patent/CN1280178C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101276020B (en) * | 2007-03-28 | 2010-04-14 | 中国科学院微电子研究所 | Method for preparing optical demultiplexer chip of micro-electromechanical system |
| CN102026909B (en) * | 2008-05-14 | 2013-11-20 | 罗伯特·博世有限公司 | Method for producing chips |
| CN102431956A (en) * | 2011-11-29 | 2012-05-02 | 北京大学 | Monolithic integration processing method for unequal-height silicon structure and integrated circuit |
| CN102431956B (en) * | 2011-11-29 | 2014-08-27 | 北京大学 | Monolithic integration processing method for unequal-height silicon structure and integrated circuit |
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| CN1280178C (en) | 2006-10-18 |
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Granted publication date: 20061018 Termination date: 20101217 |