CN1620719A - Method of making layered superlattice material with ultra-thin top layer - Google Patents
Method of making layered superlattice material with ultra-thin top layer Download PDFInfo
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- CN1620719A CN1620719A CN02806150.0A CN02806150A CN1620719A CN 1620719 A CN1620719 A CN 1620719A CN 02806150 A CN02806150 A CN 02806150A CN 1620719 A CN1620719 A CN 1620719A
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Abstract
In the manufacture of an integrated circuit memory cell, a strontium bismuth tantalate or strontium bismuth tantalum niobate thin film layer (50) is deposited on a substrate (28, 49) and a carefully controlled UV baking process is performed on the strontium bismuth tantalate layer (50) prior to the deposition of an ultra-thin bismuth tantalate layer (51). A second electrode (52) is formed on top of the ultra-thin bismuth tantalate layer (51).
Description
Technical field
The present invention relates to a kind of method of utilizing the film layered superlattice material to make integrated circuit, especially relate to a kind of processing method that is used to improve the microstructure of this film.
Background technology
Also wish at present the layered superlattice material film is used for high density ferroelectric random memory (FeRAM).But, some problems are arranged in the layered superlattice material film, for example with Pb (Zr, Ti) O
3(PZT) to compare remanent polarization (Pr) lower for film, and crystallization temperature and surface roughness are higher.Particularly, the roughening of layered superlattice material film (in other words the layered superlattice material film is very highly porous) causes producing certain infringement in the processing procedure that makes layered superlattice material film formation figure, thereby causes the reliability of ferroelectric memory relatively poor.
Known in chemical solution deposition (CSD) is handled, the electrical characteristics of layered superlattice material and the crystallinity of this material are subjected to (comprising configuration of surface, crystal orientation etc.) influence of baking processing.In the baking (drying) of the wet film resemble the coating is handled (this baking processing is carried out on hot plate usually), the metallorganic in wet film can partially or completely decompose.In the prior art, to improve surface roughness be cost with the infringement polarizability always by regulating these processing parameters, and polarizability is ferroelectric key characteristic.Therefore, need select the good microstructure or the very high polarizability of integrated circuit.
Also known ultraviolet radiation can effectively be assisted film forming chemical reaction.For example, see the Japanese patent application No.61183921 of Kamei; The open No.60-128264 (NEC Corporation) of Japan Patent; Authorize the U.S. Patent No. 4811684 of Tashiro etc.; Authorize the U.S. Patent No. 4683147 of Eguchi etc.; The open No.62-22420 of Japan Patent; And A.Yamada, Y.Jia, " the photochemical VaporDeposition of Si/Si of M.Konagai and K.Takahashi
1-xGe
x250 ℃ of Strained Layer Superlattices at " Japanese Journal of Applied Physics, Vol.27, No.11, in November, 1988, pp.L2174-L2176.But, can promote the decomposition of precursor and improve some crystallization factor, also find to have reduced polarizability although have been found that UV.Therefore, in the manufacture process of integrated circuit, need to improve the exposure and the advantage of UV radiation, suppress adverse effect simultaneously the polarization intensity characteristic of layered superlattice material.
The invention brief introduction
The present invention has overcome porous surface form and crystal orientation problem in integrated circuit is made by ultra-thin non-ferroelectric dielectric material being deposited upon the layered superlattice material top.Preferably, this non-ferroelectric dielectric ultrathin membrane is a metal material, and wherein, metal is selected from the metal of forming layered superlattice material.Preferably, layered superlattice material is strontium bismuth tantalate, strontium or bismuth tantalum niobate hydrochlorate, and non-ferroelectric high dielectric material is the bismuth tantalates.Preferably, the thickness of superthin layer be from 5 nanometers (nm) to 70nm, preferably thickness is that 5nm is to 35nm again.Adding the ultra-thin dielectric layer makes dense material can prevent degraded in processing procedure subsequently.
The present invention is by relating to ultraviolet ray (UV) radiation of exact dose in the baking processing process of layered superlattice material, and with the combination of the non-ferroelectric dielectric layer of depositing ultrathin on layered superlattice material, thereby overcome porous surface form and crystal orientation problem in integrated circuit is made.The UV photon energy that produces by the UV source in bake process is decomposed metallo-organic compound.Chemical bond in metallorganic layered superlattice material solution has various particular combination energy according to the difference of chemical bond.Consider these in conjunction with energy, UV radiation source wavelength, UV radiosity and UV radiated time are chosen as can make more level and smooth layered superlattice material micro-structural.In the baking processing process, use the ultra-thin top layer combination of UV and non-ferroelectric material to cause forming dense material, this dense material can prevent degraded in processing procedure subsequently, good polarizability, lower leakage current, higher puncture voltage are also arranged and do not have fatigue under 1010 3.0 volts bipolar Cyclic Stress.
As mentioned above, non-ferroelectric material superthin layer preferably includes a large amount of metals, and these metals are the elements in the layered superlattice material film.Preferably, non-ferroelectric dielectric deposits by using metal organic deposit (MOD) solution.In a preferred embodiment, the first individual layer layered superlattice material film preferably deposits by the MOD method, thereby produces the layered superlattice material coating on the bottom electrode of capacitor.This coating is subjected to the UV radiation of exact dose in first bake process, carry out the second common baking subsequently.Repeat these steps, reach design thickness up to the layered superlattice material film.Also can select, in oxygen, the layered superlattice material film after the baking carried out furnace annealing under 700 ℃; Then, ultra-thin bismuth tantalic acid salt deposit passes through the MOD solution deposition on substrate, and toasts, and preferably in first and second baking procedures, carries out furnace annealing subsequently.
The invention provides a kind of method of making integrated circuit, this method comprises: the substrate and first precursor are provided, and this first precursor comprises the metal part of effective dose, is used for forming the layered superlattice material film by heating this precursor; This first precursor is coated on the substrate, so that form first coating; Handle this first coating, so that form the layered superlattice material film; And the manufacturing of finishing integrated circuit, so that in this integrated circuit, comprise at least a portion layered superlattice material film; The method is characterized in that: second precursor is provided, and this second precursor comprises the metal part of effective dose, is used for forming non-ferroelectric material by heating this second precursor; This second precursor is coated on the substrate, so that form second coating; Wherein, handling first coating comprises to first coating and applies ultraviolet radiation; And handle second coating; Thereby forming the layered superlattice material film on the substrate and on layered superlattice material, forming non-ferroelectric material ultrathin membrane; This is finished to handle and comprises the manufacturing of finishing integrated circuit, so that comprise the non-ferroelectric material ultrathin membrane of at least a portion on the layered superlattice material of integrated circuit.Preferably, the step of handling first coating comprises: first baking procedure, this first baking procedure are included in this first coating of baking under the temperature that is no more than 300 ℃, and the duration is no more than 60 minutes, makes the substrate of coating be subjected to power density at 0.1mW/cm simultaneously
2And 10mW/cm
2Between the radiation of UV ray radiation source, the duration is between 1 minute to 5 minutes.Preferably, the step of handling first coating comprises second baking procedure.Preferably, second baking procedure is included under the temperature that is no more than 300 ℃ and toasts, and the duration is no more than 60 minutes.Preferably, the step of handling first coating comprises rapid thermal annealing.Preferably, rapid thermal annealing carries out being no more than under 800 ℃ the temperature, and the duration is no more than 600 seconds.Preferably, rapid thermal annealing carries out under the temperature between 690 ℃ and 710 ℃, and the duration is between 30 seconds and 300 seconds.Preferably, the step of handling second coating comprises rapid thermal annealing.Preferably, second precursor comprises the MOD precursor.Preferably, layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate hydrochlorate, and non-ferroelectric material comprises the bismuth tantalates.Preferably, the power density of UV ray radiation source is 0.73mW/cm
2Preferably, the wavelength of UV ray radiation source is between 200nm to 300nm.Preferably, the wavelength of UV ray radiation source is 254nm.Preferably, the thickness of ultrathin membrane most preferably is between 5nm and 20nm less than 40nm.
On the other hand, the invention provides a kind of ferroelectric memory element, it comprises: substrate: be formed at the ferroelectric layered superlattice material film on this substrate, this layered superlattice material comprises first metal and is different from second metal of this first metal; Be formed at the non-ferroelectric dielectric material ultrathin membrane on the ferroelectric layered superlattice material, this non-ferroelectric material comprises first and second metals; And be formed at electrode on this ultrathin membrane.Preferably, layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate hydrochlorate, and ultrathin membrane comprises the bismuth tantalates.Preferably, the thickness of this ultrathin membrane most preferably is between 5nm and 20nm less than 40nm.
Dense non-porous material that can anti-integrated processing subsequently and ferroelectric material in forming layered superlattice material, have been used UV to combine to provide with good electrical sub-feature with the ultra-thin dielectric top layer of at least two elements of employing layered superlattice material.By following explanation also in conjunction with the accompanying drawings, can know other features, objects and advantages of the present invention.
Description of drawings
Fig. 1 has represented the cutaway view of integrated circuit of the present invention;
Fig. 2 has represented the vertical view of wafer, amplifies the film capacitor of having represented by the inventive method manufacturing on this wafer;
Fig. 3 is the cutaway view that the capacitor of Fig. 2 passes line 4-4;
Fig. 4 is expression SrBi
2Ta
2O
9The curve chart of the relation between polarization intensity of thin layer sample (unit is every square centimeter of a microcoulomb) and the field that applies (unit for kilovolt every square centimeter) is at SrBi
2Ta
2O
9In the bake process of thin layer, this SrBi
2Ta
2O
9Thin layer is subjected to strict UV radiation, and it has the ultra-thin top layer of bismuth tantalates;
Fig. 5 is the flow chart that is used to make the method for integrated circuit according to the present invention;
Fig. 6 represents to utilize as shown in Figure 3 SrBi
2Ta
2O
9As ferroelectric material with utilize the curve chart of bismuth tantalates as the relation of the 2Pr+ of the ferroelectric condenser of ultra-thin top layer and 2Pr-and conversion cycle number; And
Fig. 7 represents to utilize as shown in Figure 3 SrBi
2Ta
2O
9As ferroelectric material with utilize the PUND curve chart of bismuth tantalates as the relation of the polarization intensity of the ferroelectric condenser of ultra-thin top layer and positive and negative conversion cycle number.
Embodiment
1. summarize
Fig. 1 has represented the cutaway view of the part of integrated circuit 40, and these integrated circuit 40 parts have been represented to adopt integrated circuit of the present invention.Integrated circuit part 40 is memory cell of the memory of single-transistor, single ferroelectric condenser.Integrated circuit part 40 comprises transistor 42 and the capacitor 44 that is formed on the substrate 30.Preferably, substrate 30 comprises semiconductor, for example silicon, GaAs, SiGe or other semiconductor, and can comprise other backing material, for example ruby, glass or magnesium oxide.In a preferred embodiment, substrate 30 is a semiconductor silicon wafer.Oxide in field (field oxide region) 78 is formed on the surface of Semiconductor substrate 30.Semiconductor substrate 30 comprises highly doped source electrode (doped sorce) zone 54 and highly doped drain electrode (doped drain) zone 56 that is formed at around doped channel (doped channel) zone 43.Preferably, doped source zone 54, drain region 56 and channel region 43 are n type doped region.The gate insulator (gate insulator) 60 that comprises the high dielectric constant insulator film is positioned on the Semiconductor substrate 30, and on channel region 43.The thickness of gate insulator 60 from 1 nanometer (nm) in the scope of 50nm, preferably from 5nm to 20nm.Source region 54, drain region 56, channel region 43, gate insulator 60 and gate electrode 58 form MOSFET42 together.
Preferably first interlayer dielectric (ILD) layer of being made by boron Doping Phosphorus-silicate glass (BPSG) 76 is arranged on Semiconductor substrate 30 and the oxide in field 78.The figure of ILD76 is for forming the passage 70,64 that leads to source region 54 and drain region 56 respectively.Plug the 68, the 62nd, electric conductor generally includes polysilicon or tungsten.Electrical conductivity buffering/diffusion impervious layer 46 of the present invention is arranged on the ILD76 that electrically contacts with plug 62.Diffusion impervious layer is for example by IrO
2Make, thickness is 1nm to 30nm usually, preferably from 1nm to 5nm.
As shown in Figure 1, bottom electrode layer 48 is arranged on the diffusion impervious layer 46, and preferably this bottom electrode comprises not oxidation precious metal, for example platinum, palladium, silver and golden.Metal for example aluminium, aluminium alloy, alusil alloy, alumel, nickel alloy, copper alloy and aluminium copper also can be used for the electrode of dielectric or ferroelectric memory.In a preferred embodiment, first electrode 48 is made by platinum, and thickness is 200nm.Preferably, it also comprises at least one adhesive layer (not shown), and titanium for example is so that improve the bonding of this electrode and adjacent bottom or upper strata circuit.Be arranged on the bottom electrode layer 48 according to the layered superlattice material layer 50 that the present invention includes ferroelectric high dielectric constant insulator film.The thickness of layered superlattice material layer 50 at 5nm in the 500nm scope, preferably from 30nm to 100nm in.The non-ferroelectric dielectric material 51 that comprises a large amount of metals is formed on the top at this layered superlattice material 50, and these metals are the elements in the layered superlattice material 50.Preferably make and thickness is that the top electrode layer 52 of 200nm is formed on the layered superlattice material layer 50 by platinum.First electrode layer 48, layered superlattice material layer 50, ultrathin membrane 51 and top electrode layer 52 form holding capacitor 44 together.Diffusion impervious layer 46 prevents that metallic atom and oxygen are diffused into the Semiconductor substrate 30 from layered superlattice material layer 50 and bottom electrode 48.Preferably second interlevel dielectric layer of being made by undoped silicate glass (NSG) (ILD) 80 is arranged to cover ILD76, buffering/diffusion layer 46 and dielectric storage capacitor 44.Psg film or bpsg film or other suitable passivating material also can be used in the layer 80.According to the present invention, ILD76 and ILD80 also can make by layered superlattice material.ILD80 forms certain figure, so that form the passage 72 that leads to plug 68.The metallic circuit film is arranged to cover ILD80 and is full of passage 72, the certain figure of any formation, thus form source line 74 and top electrodes circuit 66.Circuit 74,66 preferably includes Al-Si-Cu standard interconnect metal, and thickness is about 200nm to 300nm.
Should be known in that in integrated circuit fields term " substrate " has the multiple meaning usually.Usually, it is used in reference to silicon, GaAs or other wafer, and for example 30 of Fig. 1, integrated circuit is made on it.Sometimes, this term is used in reference to incomplete (incomplete) part of integrated circuit, and certain layer is formed on this part.For example, in this sense, the top substrate 28 that forms capacitor 44 is the incomplete integrated circuits by layer 46 among Fig. 1.In addition, form the intermediate layer of material above term " substrate " also is used in reference to.In this sense, layer 46 is intermediate substrate of top formation capacitor 44.In this manual, form the random layer of other layer above term " substrate " is widely used in and refers to.When the layered superlattice material layer 50 among Fig. 1 for example is the layer of current introduction, so substrate 49 typically refer to first electrode 48 and all the incomplete integrated circuits this first electrode 48 below layer.
The directional terminology here for example " makes progress ", the meaning at " downwards ", " top ", " top ", " upside ", " being lower than ", " top " and " bottom side " is with respect to Semiconductor substrate 30.Just, if second element first element " above ", the meaning is that it is farther from substrate; If it another element " below ", so the meaning be that it is than the more close Semiconductor substrate 30 of this another element.Be that material is still less away from Semiconductor substrate 30 time in the lateral part to the meaning upward for negative material gradient.Term for example " top " and " following " self does not represent that one deck directly contacts with bottom.
The length dimension of Semiconductor substrate 30 has been determined a plane, and " level " plane is thought on this plane, thinks " vertically " direction perpendicular to the direction on this plane.Term " laterally " is meant the flat in-plane of film, just is parallel to the direction of horizontal direction.
The meaning of terminology used here " film " is with used identical in integrated circuit fields.Usually, it means that the thickness of film is less than one micron.Under situation then, the thickness of film described here is less than 0.5 micron.Preferably, ferroelectric thin film 50 is that 100nm to 300nm is thick, be more preferably into 100nm to 200nm thick.The film of integrated circuit fields should not obscured with the layered capacitor in little electric capacity field, and this layered capacitor is formed by diverse method, and this and integrated circuit fields are inconsistent.
The meaning of terminology used here " ultrathin membrane " be the thickness of film less than 70nm, 50nm or thinner preferably.Most preferably be that according to the present invention, the thickness of ultrathin membrane is 35nm or thinner.
Should be known in that integrated circuit part 40 only is an example.As known in the art, the ferroelectric integrated circuit memory is usually much complicated, and but, not shown these complex situations can't make the present invention can not the known various situations in covering power territory.The present invention can be used for any ferroelectric memory, comprises other design and use ferro-electric field effect transistor (FET) that uses ferroelectric condenser.
With reference to figure 2, represented to comprise the wafer 120 of a plurality of capacitors 102,106,150 etc. among the figure.Fig. 2 is the vertical view of wafer 120, and amplifications such as film capacitor 102,106,150 manufactured according to the present invention are illustrated on this wafer 120.Fig. 3 is the cutaway view that the part of Fig. 2 3-3 along the line cuts capacitor 150.Integrated-circuit capacitor 150 preferably is formed on the substrate 90, this substrate 90 can be silicon, GaAs, ruby or other semiconductor, perhaps insulator, for example glass or magnesium oxide (MgO), perhaps other material, in described preferred embodiment, it is that diameter is about 15-20 centimetre a P-type silicon wafer.Preferably, it is a monocrystalline.Approximately the silicon oxide layer 92 of 500nm grows in above the silicon wafer 90 by commonsense method, and titanium adhesive linkage 96 is deposited on above the silicon dioxide layer 92 again.The function of titanium adhesive linkage 96 is as bonded metal, prevents that the platinum parts from peeling off from oxide layer.Tantalum, iridium and yttrium oxide also can be used as adhesives.Titanium or the common sputter of other adhesives become thickness be 10nm to the 20nm scope, the platinum by sputter 100nm to 200nm on adhesive linkage 96 forms first electrode 48 then.This two-layer 96 and 48 preferably forms for example DC magnetron sputtering or radio frequency sputtering by the conventional ion sputtering technology.Then, this not exclusively installs and anneals in the oxygen stove, preferably carries out under 650 ℃ 30 minutes.Annealing at first is used for making the titanium stabilized of titanium layer 96 in oxygen.Not exclusively device forms substrate 49, and layered superlattice material 50 is formed on this substrate 49.
Layered superlattice material layer 50 is preferably formed by the material that dielectric and/or ferroelectric characteristics are arranged.Layered superlattice material layer 50 is made as described in detail as following, and preferably thickness is more preferably less than 200nm less than about 400nm.Layer 50 can be perovskite, for example barium strontium titanate or strontium titanate.Be more preferably, layer 50 is layered superlattice materials, most preferably is strontium bismuth tantalate or strontium bismuth tantalum niobate hydrochlorate.
The layered superlattice material of all types can be summarized by following average empirical equation:
(1) A1
W1 + a1A2
W2 + a2Aj
Wj + ajS1
X1 + s1S2
X2 + s2Sk
Xk + skB1
Y1 + b1B2
Y2 + b2B1
Y1 + b1Q
z -2Should be known in that formula (1) finger-type becomes the stoichiometric balance table of superstructure part.Formula (1) is not represented cell configuration, neither attempt to specify the composition of each layer.In formula (1), A1, A2 ... Aj preferably is illustrated in the A position element in the calcium iron ore shape octahedral structure, and it comprises for example other metal of strontium, calcium, barium, bismuth, lead and other elements and their mixture and similar ionic radius.S1, S2 ... Sk represents that superstructure produces element, and they preferably include only bismuth, but also can comprise three rank materials, for example yttrium, scandium, lanthanum, antimony, chromium and thallium.B1, B2 ... B1 preferably is illustrated in the B position element in the calcium iron ore shape octahedral structure, and it can be for example element titanium, tantalum, hafnium, tungsten, niobium, vanadium, zirconium and other element.Q represents anion, and it is oxygen preferably, but also can be other element, for example heterocomplex of fluorine, chlorine and these elements, for example oxyfluoride, oxychloride etc.The subscript of formula (1) is represented the chemical valence of each element.Subscript is illustrated in the atomicity of element-specific in the empirical equation mixture.For structure cell, subscript is represented the average atom number of element in structure cell.Subscript can be integer or mark.Just, formula (1) comprises the situation that structure cell can change in whole material, for example, and at Sr
.75Ba
.25Bi
2Ta
2O
9In, average 75% A position atom is Sr, 25% A position atom is Ba.When having only an A position element in compound, it is by " A1 " element representation, w2 ... Wj equals zero.When having only a B position element in compound, it is by " B1 " element representation, y2 ... y1 equals zero, and it also is like this that superstructure produces element.Actual conditions are that one or two B position element is arranged, although formula (1) is write as more common version because the present invention will comprise A position element, B position element and superstructure produce element can situation for a plurality of elements under.The Z value is obtained by following equation:
(2)(a1w1+a2w2…+ajwj)+(s1x1+s2x2…+skxk)+(b1y1+b2y2…+bjyj)＝2z
But layered superlattice material is not the material that comprises any adaption formula (1), but only self can form the composition of the obvious crystallizing layer of one deck automatically in crystallization process.This automatic crystallization is usually by means of constituents mixt being heat-treated or annealing.Improve temperature and help that superstructure is formed part and be organized into and help thermodynamic structure, for example perovskite shape octahedron.
Terminology used here " layered superlattice material " also comprises the layered superlattice material of doping.Just, any material that is contained in the formula (1) can mix by multiple material, for example silicon, germanium, uranium, zirconium, tin, chromium, dysprosium or hafnium.
Formula (1) comprises all three Smolenskii sections electricity layered superlattice materials at least, and promptly they have the corresponding experience formula:
(3)A
m-1S
2B
mO
3m+3；
(4) A
M+1B
mO
3m+1And
(5)A
mB
mO
3m+2
Wherein, A is the A position metal in perovskite shape superstructure; B is the B position metal in perovskite shape superstructure; S is that three rank superstructures produce metal, for example bismuth or thallium; And m is the number that is enough to the whole formula electric charge of balance.When m was mark, this population mean empirical equation provided the perovskite shape layer of a plurality of differences or mixing.Formula (5) most preferably.Layered superlattice material has carried out more detailed introduction in U.S. Patent No. 5519234, open day of this patent No.5519234 is on May 21st, 1996, authorizes CarlosA.Pazde Araujo etc., and this patent documentation is whole to be incorporated herein by reference.The mixing layered superlattice material that is also contained in overall term " layered superlattice material " describes in detail in U.S. Patent No. 5955754, open day of this patent No.5955754 is on September 21st, 1999, authorize Azuma etc., this patent documentation also is incorporated herein by reference.
Layered superlattice material layer 50 is handled by MOD and is covered on the substrate.MOD handles carboxylate or the alkoxyl carboxylate that comprises as precursor, also can comprise alkoxide.Usually, in MOD handled, first metal, ethanol and carboxylic acid reacted so that form the metal alkoxide carboxylate, then, this metal alkoxide carboxylate again with the alkoxide and/or the carboxylate reaction of second metal so that form precursor.Above-mentioned MOD handles in U.S. Patent No. 5514822 open, and open day of this patent No.5514822 is on May 7th, 1996, authorizes McMillan etc., and this patent documentation is whole to be incorporated herein by reference.In another aspect of this invention, the first layered superlattice material layer 50 is handled by Sol-Gel and is covered on the substrate.As known in the art, Sol-Gel handles and always includes only the alkoxide precursor.
Get back to Fig. 3, the second layer 51 is preferably handled the top that is deposited on the first layered superlattice material layer 50 by MOD.Layer 51 is non-ferroelectric dielectric material, and a large amount of metallic elements are arranged, and these metallic elements are identical with metallic element in the layered superlattice material 50.For example, when layered superlattice material 50 was strontium bismuth tantalate or strontium bismuth tantalum niobate hydrochlorate, layer 51 is the bismuth tantalates preferably.Layer 51 toasts and anneals as described below.Then, incite somebody to action preferably the top that is formed at layer 51 by thickness second electrode 52 that to be 1000 form to the platinum of 2000 by the conventional ion sputtering technology again.
2. the detailed description of manufacture method
Fig. 5 has represented to be used to make the exemplary method of the present invention of integrated circuit as Figure 1-3.Step 210 preferably includes provides substrate, and this substrate comprises wafer 90, SiO
2Layer 92, titanium bond layer 96 and first electrode 48.These parts are unimportant to the present invention, it will be appreciated by those skilled in the art that step 210 usually also comprises any substrate is made to state can apply layered superlattice material layer 50 time.Layer 92,96 and electrode 48 also apply by commonsense method, for example to SiO
2Thermal oxidation and to the sputter of metal level.Preferably, layer 96 is carrying out thermal oxidation 30 minutes in 650 ℃ stove under the oxygen environment.Preferably, to be deposited into thickness by the DC sputter at the top of oxide layer 96 be 200nm to first electrode.Be more preferably, step 210 also is included in temperature and is greater than or equal under the situation of the temperature of in described in the back any later step this substrate being handled the metallized substrates that comprises electrode 48 is carried out prebake conditions.Preferably, this prebake conditions is carried out in oxygen, preferably carries out in temperature is 500 ℃ to 1000 ℃ diffusion furnace before carry out step 212.This pre-bake step is removed from substrate surface and is anhydrated and organic impurities.The more important thing is that prebake conditions has reduced the internal stress of platinum layer 48 by its annealing effect, and reduced the mutually counterdiffusion of selective oxidation with adhesive linkage 96 metals.
Potential, layer 96 and 48 problem of peeling off that the interaction of layer between 92,96 and 48 reduced.And when adhesive linkage 96 was transition metal, selective oxidation made the stable chemical performance of metal.Therefore, the number that penetrates into the movable atom in layered superlattice material layer 50 film by platinum layer 48 reduces, and the crystallization of layered superlattice material layer 50 film is more level and smooth, does not promptly have the defective that causes owing to the ion that spreads.When not oxidation of substrate, silicon or other wafer preferably dewater at low temperatures.
Baking layer 50 in air or dried nitrogen then, preferably under 120 ℃ to 500 ℃ temperature, and certain time.In this first bake process, apply the UV radiation to layer 50.Under higher temperature, carry out baking procedure subsequently then.Then, layer 50 carries out rapid thermal annealing again under 675 ℃ to 700 ℃ temperature, and preferably maximum time is 40 seconds.When formed surface is not suitable thickness, can repeat again to deposit, the step of baking and rapid thermal annealing, up to obtaining suitable thickness.
The UV wavelength of UV radiation source is between 200nm to 300nm, and the UV radiated time was from 1 minute to 5 minutes, and power density is from 0.1mW/cm
2To 10mW/cm
2Be more preferably, the UV wavelength of UV radiation source is 260nm, and the UV radiated time is 4 minutes, and the UV power density is 1mW/cm
2
In step 216, utilize second baking processing, therefore by in air under 250 ℃ to 500 ℃ temperature (most preferably being 260 ℃) toast the film certain hour, for example 30 seconds to 30 minutes (most preferably being 4 minutes), thus make this film drying.The UV that uses in first baking also can select, in this baking, use UV, if but like this, should reduce, so that still in the UV predicted value.Drying steps 214 and 216 carries out in air or nitrogen, preferably about 40% or more under the low humidity.Step 218 is rapid thermal annealings of the layered superlattice material of drying.For example, for strontium bismuth tantalate, behind two drying stages of step 214 and 216, can under the situation that 100 ℃/second speed and maximum temperature are 725 ℃, carry out rapid thermal annealing 30 seconds.Be more preferably, the temperature of rapid thermal annealing is between 675 ℃ and 700 ℃, and continues 30 seconds in the oxygen environment.The thermal source of rapid thermal annealing baking procedure is provided from the radiation of Halogen lamp LED, infrared lamp or ultra-violet lamp.Preferably, rapid thermal anneal step 218 is carried out in the oxygen environment of 20% to 100% oxygen, and under the temperature between 500 ℃ to 850 ℃, speed is between 1 ℃/second to 200 ℃/second simultaneously, and the retention time is 5 seconds to 300 seconds.In fact, in the quick thermal annealing process process, all remaining organic substances are all burnt and/or are evaporated.Simultaneously, the fast temperature of rapid thermal annealing raises and has promoted nucleation, and promptly layer 50 produces a large amount of very little crystal grain.These crystal grain are as nucleus, by this nucleus with further crystallization.In baking processing, exist oxygen very important to forming these crystal grain.Repeating step 212,214,216 and 218 obtains suitable thickness up to layered superlattice material.
In step 216, utilize second baking processing, therefore by in air 250 ℃ to about 500 ℃ of temperature (most preferably being 260 ℃) toast the ultrathin membrane certain hour, for example 30 seconds to 30 minutes (most preferably being 4 minutes), thus make this ultrathin membrane drying.Drying steps 224 and 226 carries out in air or nitrogen, preferably about 40% or more under the low humidity.Step 228 is rapid thermal annealings of the layered superlattice material of drying.The treatment conditions of step 228 are identical with step 218.
Step 230 is selectable furnace annealings, and this furnace annealing carries out on substrate, so that form crystal grain in the dry superthin layer 51 of the non-ferroelectric material that is formed by step 222,224,226 and 228.This selectable annealing was preferably being carried out oxygen 80 minutes to about 850 ℃ temperature from about 700 ℃.
Step 232 comprises by any commonsense method sputter second electrode 52, for example DC magnetron sputtering or radio frequency sputtering.Step 234 comprises common sputter equipment, is used to form the similar circuit parts of required integrated circuit.Particularly, as known in the art, step 234 preferably includes and applies plus or minus photoresistance resist, carries out radiation by template subsequently.In step 238, on substrate, carry out the ashing treatment of etching and photoresistance resist, so that remove photoresist coatings.Preferably, step 234 and 236 comprises and makes layered superlattice material 50, ultra-thin rete 51 and first electrode 48 form figures.In step 240, recover annealing and in oxygen, under 700 ℃, carry out 30 fens clock times.In step 250, finish the ferroelectric layered superlattice material 50 of integrated circuit to cover by ultra-thin non-ferroelectric film 51 in the electronic unit that is included in integrated circuit, for example capacitor 44.
3. the example of manufacture method and correlated performance
Provide the example that is used for the manufacture method of wafer 120 shown in Fig. 2 and 3 according to the present invention below.
Example 1
Deposit strontium bismuth tantalate and utilize the UV radiation that bismuth tantalates top layer is toasted by MOD
On wafer 49, make and comprise strontium bismuth tantalate (Sr
0.9Bi
2.2Ta
2O
9) layered superlattice material layer 50.The KJC-MOD strontium bismuth tantalate precursor that Kojundo that use obtains in the U.S., Japanese company makes.The molar concentration of this precursor solution is about 0.1 mole every liter.The substrate 49 that comprises the platinum layer 48 that titanium layer 96 that thick silicon dioxide layer 92,200 of monocrystalline silicon layer 90,5000 are thick and 2000 are thick carried out prebake conditions 30 minutes in diffusion furnace under 800 ℃, the flow of oxygen is 6 liters/minute simultaneously.Precursor solution is deposited on the substrate 49 by MOD.Substrate 49 rotated 30 seconds under 2500RPM.Then, the substrate of coating places on the hot plate again, and toasts 1 minute in air under 160 ℃, is exposed to simultaneously under the UV radiation source.Strict control of UV radiation source and adjusting are so that the UV light of emission 254nm.And the power density of this UV radiation source is controlled to be 0.73mW/cm
2In this baking processing process, the UV radiated time is 4 minutes.Then, substrate and coating were toasted 4 minutes in air under 260 ℃.The coating of this substrate and baking was toasted 4 minutes in air under 260 ℃ again.The magnet of this substrate and baking sends rapid thermal anneal er again to, and the speed with 100 ℃/second is carried out rapid thermal annealing in oxygen under 700 ℃ then, and keeps 30 second time.Repeat again twice from the step that deposits to rapid thermal annealing.
The substrate that applies sends the settling chamber to, and then, having formula is Bi
1.1Ta
1.0O
4Bismuth tantalates superthin layer be deposited on layer 50 top by the MOD method.The molar concentration of ultra-thin precursor solution is about 0.05 mole every liter.Substrate 49 rotated 30 seconds under 3000RPM.Then, sample sends hot plate to, and substrate is carried out 1 minute baking processing in air under 160 ℃.Under 260 ℃, in air, carry out 4 minutes second baking subsequently.Then, the substrate of this coating sends rapid thermal anneal er again to, then under 700 ℃ in oxygen the speed with 100 ℃/second carry out rapid thermal annealing, the retention time is 30 seconds.Then, the substrate of coating sends quick stove to, and carries out furnace annealing 60 minutes in the oxygen environment under 700 ℃ of temperature.
Then, the substrate of coating sends the settling chamber to, and sputter second electrode 52, applies resist, carries out the standard light template subsequently and handles, and carry out the ion abrasion and carve.After the step that forms figure, carry out ashing treatment again.Wafer 120 sends quick stove again to, and carries out furnace annealing 60 minutes in the oxygen environment under 700 ℃ of temperature.At last, carry out standard and recover annealing.The final thickness of strontium bismuth tantalate layer is 2000A.Compare with the manufacture method of prior art, the more layered superlattice material of smooth surface morphology can be made in this aspect of the present invention.Finally, as introduce below, shown in Fig. 4,6 and 7 curve chart, Electronic Performance is fine.
Fig. 4 has represented to have the Sr of bismuth tantalates superthin layer in example 1
0.9Bi
2.2Ta
2O
9The initial B-H loop of sample.The B-H loop of Fig. 4 has represented that (unit is every square centimeter of μ C/cm of microcoulomb for polarization intensity on the y axle
2) VS for ± 1 volt, ± (unit is a kilovolt cm for the applied field of 3 volts and ± 5 volts voltage cycle
2).Magnetic hysteresis is measured and is carried out on uncompensated Sawyer-Tower circuit.As everyone knows, represent that the B-H loop of good ferroelectric properties will be for wide relatively and high along the polarization intensity direction, and expression is thin and linear.Made in the example 1, comprise that control uses the B-H loop of the device of UV and the bismuth tantalates top layer on the strontium bismuth tantalate ferroelectric layer to represent fabulous ferroelectric properties.
The conversion cycle number of times of Fig. 6 ferroelectric condenser that to be Pr+, Pr-and 2Pr VS made by the method for example 1.Curve representation the polarization intensity on the y axle (unit is for for every square centimeter of μ C/em of microcoulomb
2) the conversion cycle number of times of VS on the x axle.Polarization charge 2Pr is by making for example 150 electric charges that become in opposite direction the state of (for direction vertically downward) perfact polarization to produce from the state-transition along a direction (described for vertically upward direction) perfact polarization of capacitor.Here, the meaning of " perfact polarization " is when the ferroelectric material perfact polarization and the state when removing.According to for example B-H loop shown in Fig. 4, it is the difference between some Pr+ when B-H loop and positive polarization axle (y axle) intersect and the some Pr-when B-H loop and negative polarization axle (y axle) are crossing.When not having other explanation, the value of Pr+, Pr-and 2Pr is to obtain from the magnetic hysteresis measured value under maximum pressure.Circular in definition is for example 150 conversions of being undertaken by a square pulse of capacitor.Polarization intensity 2Pr is approximately the twice of remanent polarization Pr.Polarizability is not only very high, and very flat, up to 10
9Just show tired (fatigue) a little.In fact, for any ferroelectric material, the best fatigue results of the most flat curve representation.
Fig. 7 is that (unit is every square centimeter of μ C/cm of microcoulomb along the polarization intensity of y axle
2) VS is along the PUND curve chart of the number of times of the conversion cycle of x axle.The PUND curve negotiating produces so in normal way, promptly at first with the impulse starting sample of negative direction, then a string four potential pulses are measured polarization intensity, the measurement pulse that these four potential pulses are given is: just (P) pulse, second positive pulse or upwards (U) pulse, negative (N) pulse and another negative pulse or (D) pulse downwards.All pulses have identical absolute amplitude.Initial negative pulse guarantees that material begins with negative polarization intensity.Therefore first positive pulse (P) makes material transition become positive polarization intensity.Because sample is positive polarization, second pulse or " U " impulsive measurement are along the variation of forward between remanent polarization and saturated polarization.Equally, the negative electric current that changes of " N " impulsive measurement, " D " impulsive measurement is along the variation of negative sense between remanent polarization and saturated polarization.Each P, U, N and D curve are all very flat, represent very for a short time with the variation of cycle-index, show that this material has highly stable ferroelectric properties in the useful life of memory.
Method of the present invention provides configuration of surface obviously finer and close and more level and smooth than prior art ferroelectric material, thereby the problem that occurs when forming the capacitor figure of integrated circuit still less.And the polarizability of ferroelectric material does not reduce owing to making to handle.According to sample, dielectric breakdown voltage (VBD) is between 14 volts and 15 volts.This is 1.2MV/cm corresponding to breakdown electric field.
Example 2
Deposit the strontium bismuth tantalum niobate hydrochlorate and utilize the UV radiation that bismuth tantalates top layer is toasted by MOD
Capacitor 150 forms by the method identical with example 1, except layered superlattice material is strontium bismuth tantalum niobate hydrochlorate (Sr
0.9Bi
2.2(Ta
y, Nb
1-y) O
9).The KJC-MOD strontium bismuth tantalum niobate hydrochlorate precursor that Kojundo that use obtains in the U.S., Japanese company makes.The configuration of surface of this sample even finer and close and more level and smooth than example 1 has very high polarization intensity and other good electrical characteristics simultaneously, although they tilt a little than example 1.
Example 3
Deposit strontium bismuth tantalate and utilize the UV radiation that bismuth tantalates top layer is toasted by Sol-Gel
Capacitor 150 forms by the method identical with example 1, except handling precursors to deposit solution on substrate 49 by Sol-Gel.Sol-Gel handles and always includes only the alkoxide precursor.This precursor is the alkoxide precursor of the Japanese Tokyo Oka strontium bismuth tantalate making, obtain on American market.Result and example 1 are similar, although not all parameter is all good equally.
Example 4
Deposit the strontium bismuth tantalum niobate hydrochlorate and utilize the UV radiation that bismuth tantalates top layer is toasted by Sol-Gel
Capacitor 150 forms by the method identical with example 1, except handling precursors to deposit solution on substrate 49 by Sol-Gel.Sol-Gel handles and always includes only the alkoxide precursor.This precursor is the alkoxide precursor of the Japanese Tokyo Oka strontium bismuth tantalum niobate hydrochlorate making, obtain on American market.Result and example 2 are similar, although not all parameter is all good equally.
Example 5
Strontium bismuth tantalate and bismuth tantalates top layer by the MOD deposition
Form a series of capacitors 150 by the method identical, except not using UV in the method with example 1.Bismuth tantalates MOD precursor uses various molar concentrations: promptly molar concentration is .03M .04M .05M .06M and .07M.For the bismuth tantalates ultrathin membrane of being made by the 0.03M precursor, the ferroelectric polarizability 2Pr of strontium bismuth tantalate surpasses 15 μ C/cm
2, and leakage current, puncture voltage and fatigue are also fine, although less than the method that adopts UV to handle.Polarizability tilts to drop to 11 μ C/cm when the molar concentration of 0.07M to the molar concentration increase
20.05M the polarizability of the precursor substantially polarizability with the method for example 1 is identical, electrical property is less than it, although still in fine scope.
Example 6
Strontium bismuth tantalum niobate hydrochlorate and bismuth tantalates top layer by the MOD deposition
Capacitor 150 forms by the method identical with example 5, except using the strontium bismuth tantalum niobate hydrochlorate precursor of KJC-MOD.The compactness of formed ferroelectric layer and flatness are better than example 5 a little, and other electrical property is also fine, although compare a little with the coupon results of example 5.
By in first baking procedure, on the layered superlattice material film, adopting based on the non-ferroelectric material top layer of the ultra-thin stratiform of MOD solution, improved configuration of surface really, can not reduce electrical characteristics simultaneously.
Electrical characteristics with layered superlattice material film of bismuth tantalic acid salt deposit depend on the thickness of bismuth tantalic acid salt deposit very much, because its non-ferroelectricity.Need very accurately to control the thickness of bismuth tantalates film.Behind the thickness optimization that makes bismuth tantalates top layer, can obtain 2Pr character identical and almost smooth film surface with there not being bismuth tantalates top layer.But, breakdown voltage has significantly improved above 10 volts.
In above-mentioned example, also changed the strontium/bismuth ratio of various layered superlattice materials.Relatively strontium/bismuth is than the film for 0.0/2.2 and 0.9/2.3, and the film and the combination of bismuth tantalates top layer of more being rich in bismuthino will help improving configuration of surface.
(the UV wavelength is about 254nm, and the UV power density is 0.73mW/cm in UV radiation in the baking processing process
2) successfully make the surface roughness of layered superlattice material improve.Particularly, the UV radiation after 160 ℃ at first baking processing will have great role to the raising of configuration of surface; But, 2Pr will be reduced.This phenomenon is caused by its C axle orientation.Up to the UV radiation is the burnt every square centimeter of (mJ/cm of about 83 millis
2) see that just configuration of surface improves.At 100mJ/cm
2After the radiation, 2Pr begins obvious decline.Therefore, the gross energy of UV radiation is control accurately, and the UV radiation causes surface roughness not change very little, and too many UV radiation causes 2Pr obviously to reduce.The UV energy must be by force to can disconnecting any metallorganic or other organic key, but again can not be by force to causing C axle orientation.Reduce for improving configuration of surface and reducing 2Pr, only applying the UV radiation to ground floor is the best approach.
By above-mentioned and other example, determined that the pre-metering of UV should be in following parameter area: wavelength should be 200nm to 300nm, preferably about 254nm; The time that applies UV should be between 1 minute and 5 minutes, preferably about 4 minutes; Power density should be from 0.1mW/cm
2To 10mW/cm
2, preferably about 0.73mW/cm
2
The combination of above-mentioned by adopting " UV radiation treatment " and above-mentioned " processing of bismuth tantalates top layer " can be made the most reliable thin strontium bismuth tantalate basement membrane.
Although introduced the present invention by the preferred embodiments of the present invention, should be known under the situation that does not break away from spirit of the present invention or essential characteristic, can implement with other particular form.For example,, also can adopt other substrate, for example GaAs, germanium, SiGe and other substrate although the present invention is introduced by silicon substrate.Also can use other ferroelectric memory structure.And, proved the advantage and the machinability that are combined in when carrying out the UV radiation in the bake process and making ultra-thin non-ferroelectric top layer that a plurality of element that has with the layered superlattice material surface be arranged here, can also use other stratified material.Therefore, present embodiment is as an illustration, rather than limits.Scope of the present invention will be represented by additional invention protection range.
Claims (22)
1. method of making integrated circuit (40), described method comprises: the substrate (28,49) and first precursor are provided, and this first precursor comprises the metal part of effective dose, is used for forming layered superlattice material film (50) by heating described precursor; Described first precursor is coated on the described substrate, so that form first coating; Handle described first coating, so that form the described film of layered superlattice material; And the manufacturing of finishing described integrated circuit, so that comprise the layered superlattice material film of at least a portion in described integrated circuit: described method is characterised in that:
Second precursor is provided, and this second precursor comprises the metal part of effective dose, is used for forming non-ferroelectric material (51) by heating described second precursor;
Described second precursor is coated on the described substrate, so that form second coating; And
Described first coating of described processing comprises to described first coating and applies ultraviolet radiation; And
Handle described second coating; Thereby forming the described film of layered superlattice material on the described substrate and on layered superlattice material, forming described non-ferroelectric material ultrathin membrane;
Described finish to handle comprise the manufacturing of finishing described integrated circuit so that on the layered superlattice material of described integrated circuit, comprise the described non-ferroelectric material ultrathin membrane of at least a portion.
2. method according to claim 1, it is characterized in that: the described step of handling described first coating comprises: first baking procedure, this first baking procedure is included in described first coating of baking under the temperature that is no more than 300 ℃, duration is no more than 60 minutes, makes the substrate of described coating be subjected to power density at 0.1mW/cm simultaneously
2And 10mW/cm
2Between the radiation of UV ray radiation source, the duration is between 1 minute to 5 minutes.
3. method according to claim 2 is characterized in that: described first baking procedure carries out in air.
4. method according to claim 2 is characterized in that: the described step of handling described first coating comprises second baking procedure.
5. method according to claim 4 is characterized in that: described second baking procedure is included under the temperature that is no more than 300 ℃ and toasts, and the duration is no more than 60 minutes.
6. method according to claim 1 is characterized in that: the described step of handling described first coating comprises rapid thermal annealing.
7. method according to claim 1 is characterized in that: the described step of handling described second coating comprises rapid thermal annealing.
8. according to claim 6 or 7 described methods, it is characterized in that: described rapid thermal annealing carries out being no more than under 800 ℃ the temperature, and the duration is no more than 600 seconds.
9. method according to claim 8 is characterized in that: described rapid thermal annealing carries out under the temperature between 690 ℃ and 710 ℃, and the duration is between 30 seconds and 300 seconds.
10. according to claim 6 or 7 described methods, it is characterized in that: described rapid thermal annealing carries out in oxygen.
11. method according to claim 1 is characterized in that: described second precursor comprises the MOD precursor.
12. method according to claim 1 is characterized in that: layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate hydrochlorate.
13. method according to claim 12 is characterized in that: described non-ferroelectric material comprises the bismuth tantalates.
14. method according to claim 1 is characterized in that: the power density of described UV ray radiation source is 0.73mW/cm
2
15. method according to claim 1 is characterized in that: the wavelength of described UV ray radiation source is between 200nm to 300nm.
16. method according to claim 1 is characterized in that: the wavelength of described UV ray radiation source is 254nm.
17. according to claim 1 or 13 described methods, it is characterized in that: the thickness of described ultrathin membrane is less than 40nm.
18. method according to claim 17 is characterized in that: the thickness of described ultrathin membrane is between 5nm and 20nm.
19. a ferroelectric memory element comprises:
Substrate (28,29);
Be formed at the ferroelectric layered superlattice material film (50) on the described substrate, layered superlattice material comprises first metal and is different from second metal of described first metal;
Be formed at the non-ferroelectric dielectric material ultrathin membrane (51) on the described ferroelectric layered superlattice material, described non-ferroelectric material comprises described first and second metals; And
Be formed at the electrode on the described ultrathin membrane.
20. ferroelectric memory element according to claim 19 is characterized in that: layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate hydrochlorate, and described ultrathin membrane comprises the bismuth tantalates.
21. according to claim 19 or 20 described ferroelectric memory elements, it is characterized in that: the thickness of described ultrathin membrane is less than 40nm.
22. according to claim 19 or 20 described ferroelectric memory elements, it is characterized in that: the thickness of described ultrathin membrane is between 5nm and 20nm.
Applications Claiming Priority (6)
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|---|---|---|---|
| US27446501P | 2001-03-09 | 2001-03-09 | |
| US60/274,465 | 2001-03-09 | ||
| US28512301P | 2001-04-20 | 2001-04-20 | |
| US60/285,123 | 2001-04-20 | ||
| PCT/US2001/045392 WO2002073669A2 (en) | 2000-10-31 | 2001-10-30 | Method of making layered superlattice material with improved microstructure |
| USPCT/US01/45392 | 2001-10-30 |
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| US5423285A (en) * | 1991-02-25 | 1995-06-13 | Olympus Optical Co., Ltd. | Process for fabricating materials for ferroelectric, high dielectric constant, and integrated circuit applications |
| US5648114A (en) * | 1991-12-13 | 1997-07-15 | Symetrix Corporation | Chemical vapor deposition process for fabricating layered superlattice materials |
| US5955754A (en) * | 1992-10-23 | 1999-09-21 | Symetrix Corporation | Integrated circuits having mixed layered superlattice materials and precursor solutions for use in a process of making the same |
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