CN1619326A - Testing method of peripheral interconnecting wire - Google Patents
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- CN1619326A CN1619326A CN 200310115355 CN200310115355A CN1619326A CN 1619326 A CN1619326 A CN 1619326A CN 200310115355 CN200310115355 CN 200310115355 CN 200310115355 A CN200310115355 A CN 200310115355A CN 1619326 A CN1619326 A CN 1619326A
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Abstract
The testing method of peripheral interconnection line includes the following steps: fixing an address, adopting a group of all '1' data and a group of all '0' data to test dull type failure of FLASH data wire, fixing address, using '10' triangular data matrix to test data wire; then selecting and using a group of distrinct addresses, sing walking 1 data matrix to test data wire, so that, can detect all the short-circuit troubles, the address adopts walking 1 matrix, data adopts walking 0 matrix, then address adopts walking 0 matrix and data also adopts walking 0 matrix, so that it can detect dull failure and short-circuit trouble of address wire.
Description
Technical field
The present invention relates to the measuring technology of electronics or the communications field, specifically refer to a kind of method of testing of peripheral interconnection line.
Background technology
Boundary scan technique is to put forward in 1985, it has improved controllability and the observability of device by being present in boundary scan cell between device input and output pin and the kernel circuitry, can test device and peripheral circuit thereof by boundary scan technique. Set up the JTAG tissue in 1986, JTAG in 1988 have proposed the boundary-scan architecture of standard, title is Boundary-Scan Architecture Standard Proposal, Version 2.0, and ideal is to be applied to the perfect standardized technique of the cover of one on chip, printed board and the holonomic system. Nineteen ninety, IEEE has been duly admitted the JTAG standard, after replenishing and revising, and called after IEEE 1149.1-90.
Since IEEE 1149.1 standards issues, boundary scan technique is widely used in circuit board testing, FLASH in the plate programming etc. FLASH device itself is not with border scanning (BS, Boundary Scan) structure in fact, but FLASH around generally have the BS device, thereby the BS device around can utilizing is realized FLASH and is loaded. That utilizes that boundary scan technique carries out FLASH neither needs equipment occupying volume outside in plate programming, does not also need product to increase extra hardware, and it only need to be linked to be a scan chain with the BS device of being correlated with, and boundary scan interface extracted gets final product. Can control boundary scan chain by this interface, and then control line, data wire and the address wire of control FALSH finish the operations such as read-write of FLASH, as shown in Figure 1.
Before to the FLASH programming, should guarantee the FLASH chips welding and be connected correctly. But present common practices is exactly not do test, directly loads, if exist like this object-line fault will cause loading unsuccessfully. Find to load unsuccessfully if carry out data check at loaded, then just carry out the peripheral interconnecting test of FLASH, so relatively lose time. Need only several seconds because do once peripheral interconnecting test, load and a few minutes to arrive dozens of minutes and be a FLASH. So be necessary to carrying out first peripheral interconnection line test (and FLASH internal element test spended time relatively before the LASH programming, be generally several times of FLASH programming time, so FLASH loads before and is not suitable for carrying out the test of FLASH internal element, only load in the unsuccessfully later fault diagnosis at FLASH, just might test to search disabling unit by the FLASH internal element).
But generally there is the incomplete or inaccurate shortcoming of fault location of test in existing method of testing. Doing test before the FLASH programming, is a kind of fairly simple implementation method, is exactly the staggered data writing " 01...0101 " of fixed address and " 10...1010 ", the while read check, and whether the test data line exists fault; Then selected address " 01...0101 " writes two different data with " 10...1010 ", read check then, and whether the test address line exists fault; Control line is not done independent test, because the test of the fault of control line by the data line address line can detect.
Said method is very simple, also can test the short trouble of fixed logic fault and part circuit, but has most of short trouble to detect, and it also can't distinguish data wire fault and address alignment fault.
Summary of the invention
The present invention proposes a kind of method of testing of peripheral interconnection line, and described method not only can detect the fault of all object-lines, and can accurately locate fault.
For achieving the above object, the invention provides following technical scheme:
A kind of method of testing of peripheral interconnection line comprises the following steps:
1) with the dull fault of the data test data wire of a group complete " 0 " and complete " 1 ", if measured value is identical with desired value, then carries out the following step; If measured value is not identical with desired value, then dull fault occurs in the data wire of different position, carries out carrying out the following step after fault gets rid of again;
2) fix an address, with " 10 " triangle data matrix test data line, if measured value is identical with desired value, then carry out the following step; If measured value is not identical with desired value, then determine the short trouble position, carry out carrying out again the following step after fault gets rid of;
3) select one group of different address, with walking " 1 " data matrix test data line, if measured value is identical with desired value, then carry out the following step; If measured value is not identical with desired value, then determine the short trouble position, carry out carrying out again the following step after fault gets rid of;
4) address wire adopts walking " 1 " matrix, and data wire adopts walking " 0 " matrix, and the fault of test address line if measured value is identical with desired value, is then carried out the following step; If measured value is not identical with desired value, determine that then the appropriate address line is fixed logic 0 or 1-dominance short trouble fault, carry out carrying out again the following step after fault gets rid of;
5) address wire adopts walking " 0 " matrix, and data wire adopts walking " 0 " matrix, the fault of test address line, if measured value is identical with desired value, then test finishes; If measured value is not identical with desired value, determine that then the appropriate address line is fixed logic 1 fault or 0-dominance short trouble, carry out fault and get rid of, finish test.
Described step 1) in, if the measured value of a certain data wire is complete " 0 ", reports that then 0 open fault has occured to be fixed as this data wire; If the measured value of a certain data wire is complete " 1 ", report that then 1 open fault has occured to be fixed as this data wire.
Described step 2) and step 3) in, if there are a plurality of row, its vector equates that its value reports then that for the result of the logic OR computing of the desired value of these several row 1-dominance short trouble has occured many data wires of respective column; If there are a plurality of row, its vector equates that its value reports then that for the result of the logic and operation of the desired value of these several row 0-dominance short trouble has occured many data wires of respective column.
Described step 4) in, make mistakes if read the data of all zeros address, current test address equates with the value of all zeros address, then may be fixed logic 0 fault, and abort situation is the address wire of the corresponding numeral in current test address " 1 "; If it is unequal to read the data of the data of all zeros address and current address, but the data that exist other a plurality of address to read back equate with it, then be 1-dominance short trouble, the address wire short circuit of the different address bit of these several addresses of correspondence.
Described step 5) in, make mistakes if read the data of all ones address, current test address equates with the value of all ones address, then may be fixed logic 1 fault, and abort situation is the address wire of the corresponding digital " 0 " in current test address; If it is unequal to read the data of the data of all ones address and current address, but the data that exist other a plurality of address to read back equate with it, then be 0-dominance short trouble, the address wire short circuit of the different address bit of these several addresses of correspondence.
Described step 2) also can adopt " 01 " triangle data matrix to test.
Described step 4) and step 5) in address wire adopt walking " 1 " matrix to test after can adopting first walking " 0 " matrix.
The present invention is according to the characteristics of FLASH device itself, a kind of complete FLASH peripheral interconnection line method of testing has been proposed, this method of testing not only can detect all stuck-at faults and the bridge joint short trouble of peripheral interconnection line, and can carry out accurate fault location, report fault occurrence positions and fault type can also be distinguished 1-dominance short trouble and 0-dominance short trouble. This testing scheme can guarantee that before FLASH loads the peripheral annexation of FLASH is normal, had ensured the validity that FLASH loads, and had avoided the unnecessary time.
Description of drawings
Fig. 1 utilizes boundary scan technique to realize that FLASH is in the system architecture of plate programming.
Fig. 2 is that the present invention is to the test flow chart of FLASH data wire.
Fig. 3 is that the present invention is to the test flow chart of FLASH address wire.
The specific embodiment
Method of testing of the present invention can be divided into three large operating procedures. Characteristics according to the FLASH device, needing to carry out erase operation before the write operation each time, and the device characteristics of FLASH is that data are 1 after wiping, then data 1 can only be rewritten as data 0, data 0 can not be rewritten as data 1, so whole process such as the following table of the peripheral interconnecting test of FLASH:
| Testing procedure | Operation | The address | Data | Note |
| The first step | Wipe | Some | A is any fixed address in this piece, compares in reading and judges. Test data is one group complete " 1 " and one group complete " 0 ". | |
| Read | A | 1...111 | ||
| Write | A | 0...000 | ||
| Read | A | 0...000 | ||
| Second step a second step b | Wipe | Some | A is any fixed address in this piece, compares in reading and judges. The characteristics of test data matrix are the form of lower triangle of the upper trigonometric sum " 0 " of " 1 ", and the diagonal data are 0 (at this called after " 10 " triangular matrices). Second step a tests end, if discovery fault, the then fault diagnosis of advanced row data wire. Fix an address test data line, the fault of address wire does not affect the test result of data wire. Because FLASH itself, can only write " 0 ", can not write " 1 ", so second step b step must select a different set of address to carry out, A wherein0、 A 1、...、A nBe exactly any group address selected in this piece, require the address different. Test data is that walking 1 matrix (diagonal is " 1 ", and all the other are the matrix of " 0 ") second step b tests end, if discovery fault, the then fault diagnosis of advanced row data wire. | |
| Write | A | 1...110 | ||
| Read | A | 1...110 | ||
| Write | A | 1...100 | ||
| Read | A | 1...100 | ||
| ...... | ...... | ...... | ||
| ...... | ...... | ...... | ||
| Write | A | 1...000 | ||
| Read | A | 1...000 | ||
| Wipe | Some | |||
| Write | A 0 | 0...001 | ||
| Write | A 1 | 0...010 | ||
| ...... | ...... | ...... | ||
| Write | A n | 1...000 | ||
| Read | A0 | 0...001 | ||
| Read | A 1 | 0...010 | ||
| ...... | ...... | ...... | ||
| Read | A n | 1...000 |
| The 3rd step a | Wipe | Address 0...000,0...001,0...010 ..., residing of 1...000 | Address wire is used walking " 1 " algorithm, and namely the diagonal of address matrix is " 1 ", and all the other are " 0 ", increase in addition one group of complete " 0 " address. The test data matrix is walking " 0 " data matrix (namely the diagonal data is " 0 ", and remainder data is the matrix of " 1 "), increases in addition one group of complete " 1 " data. If finish to find fault at the 3rd step a, carry out first fault diagnosis, location fixed logic 0 fault and 1-dominance short trouble. | |
| Write | 0...001 | 1...110 | ||
| Write | 0...010 | 1...101 | ||
| ...... | ...... | ...... | ||
| Write | 1...000 | 0...111 | ||
| Read | 0...000 | 1...111 | ||
| Read | 0...001 | 1...110 | ||
| Read | 0...010 | 1...101 | ||
| ...... | ...... | ...... | ||
| Read | 1...000 | 0...111 | ||
| The 3rd step b | Wipe | Address 1...110,1...101 ..., 0...111, the residing Block of 1...111 | Address wire is used walking " 0 " algorithm, and namely the diagonal of address matrix is " 0 ", and all the other are " 1 ", increase in addition one group of complete " 1 " address. The test data matrix is that the diagonal data are " 0 ", and remainder data is walking " 0 " data matrix of " 1 ", increases in addition one group of complete " 1 " data. If finish to find fault at the 3rd step b, carry out first fault diagnosis, location fixed logic 1 fault and 0-dominance short trouble. | |
| Write | 1...110 | 1...110 | ||
| Write | 1...101 | 1...101 | ||
| ...... | ...... | ...... | ||
| Write | 0...111 | 0...111 | ||
| Read | 1...111 | 1...111 | ||
| Read | 1...110 | 1...110 | ||
| Read | 1...101 | 1...101 | ||
| ...... | ...... | ...... | ||
| Read | 0...111 | 0...111 | ||
First step test is used for the test data line and whether has open fault and fixed logic fault, and the second step test is used for the test data line and whether has short trouble, and the 3rd pacing tries out the test address line whether to have open circuit or short trouble. Finish to carry out the data wire fault diagnosis in the second step test, finish to carry out the address alignment fault diagnosis in the 3rd pacing examination.
The fault diagnosis of first step test is fairly simple, wiping after a certain, certain fixed address in this piece should be able to read complete 1, if do not read complete 1, just illustrate that there is the fault (being fixed as 0 fault) of S-A-0 in data wire, numerical value is that 0 data wire is exactly the fault wire position that S-A-0 occurs. Then write full 0 in this address and read full 0, do not read full 0 if write full 0, just illustrate that there is the fault (being fixed as 1 fault) of S-A-1 in data wire, numerical value is that 1 data wire is exactly the fault wire position that S-A-1 occurs.
The second step test need to judge that the below is an example of second step test result to the linear position data of short trouble and the short trouble of what type, wherein comprises result (the tentation data line b of fault diagnosis3b
2b
1b
0, test vector r0r
1...r
6)：
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| Desired value | b 2Open circuit S-A-0 | b 2And b1Open circuit S-A-0 | b 2And b1Short circuit 0-dominance | b 2And b1Open circuit S-A-1 | b 2And b1Short circuit 1-dominance | b 3And b0Open circuit S-A-0 b2And b1Short circuit 0-dominance | |
| b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | |
| r 0 | 1110 | 1010 | 1000 | 1110 | 1110 | 1110 | 0110 |
| r 1 | 1100 | 1000 | 1000 | 1000 | 1110 | 1110 | 0000 |
| r 2 | 1000 | 1000 | 1000 | 1000 | 1110 | 1000 | 0000 |
| r 3 | 0001 | 0001 | 0001 | 0001 | 0111 | 0001 | 0000 |
| r 4 | 0010 | 0010 | 0000 | 0000 | 0110 | 0110 | 0000 |
| r 5 | 0100 | 0000 | 0000 | 0000 | 0110 | 0110 | 0000 |
| r 6 | 1000 | 1000 | 1000 | 1000 | 1110 | 1000 | 0000 |
To the open fault of data wire and the diagnostic process of short trouble, as shown in Figure 2, as follows with the pseudo-program language representation:
BEGIN
Each row V of the actual test response matrix V of FORi
IF V
iRespective column T with the Expected Response matrix TiInconsistent
There is fault in report;
IF V
iEach component be fixed as 1
Report that 1 open fault has occured to be fixed as i bar data wire;
ELSE IF V
iEach component be fixed as 0
Report that 0 open fault has occured to be fixed as i bar data wire;
There are a plurality of row in ELSE IF, and its vector equates that its value is the result of the logic OR computing of the Expected Response of these several row
1-dominance short trouble occurs in many data wires of report respective column
There are a plurality of row in ELSE IF, and its vector equates that its value is the result of the logic and operation of the Expected Response of these several row
0-dominance short trouble occurs in many data wires of report respective column
ELSE
The report fault type can't be judged, reports simultaneously which data lines is fault occur on
END IF
END IF
END FOR
There is not fault in IF
Fault is not found in the test of report data line;
END。
After guaranteeing that data wire does not have fault, can carry out the third-largest pacing examination, address wire to be tested, following table is an example of the third-largest pacing test result, and comprises the result of fault diagnosis:
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| Address a3a 2a 1a 0 | Desired value | The a2 S-A-0 that opens a way | A2 and a1 open circuit S-A-0 | A2 and a1 short circuit 0-dominance | A2 and a1 open circuit S-A-1 | A2 and a1 short circuit 1-dominance | A3 and a0 open circuit S-A-0 a2 and a1 short circuit 0-dominance |
| 0001 | 1110 | 1110 | 1110 | 1110 | 1110 | 1110 | 0000 |
| 0010 | 1101 | 1101 | 1001 | 1001 | 1001 | 1001 | 0000 |
| 0100 | 1011 | 1011 | 1001 | 1001 | 1001 | 1001 | 0000 |
| 1000 | 0111 | 0111 | 0111 | 0111 | 0111 | 0111 | 0000 |
| 0000 | 1111 | 1011 | 1001 | 1001 | 1001 | 1111 | 0000 |
| 1110 | 1110 | 1110 | 1110 | 1110 | 1110 | 1110 | 0110 |
| 1101 | 1101 | 1101 | 1001 | 1001 | 1001 | 1001 | 1001 |
| 1011 | 1011 | 1011 | 1001 | 1001 | 1001 | 1001 | 1001 |
| 0111 | 0111 | 0111 | 0111 | 0111 | 0111 | 0111 | 0110 |
| 1111 | 1111 | 1011 | 1001 | 1111 | 1001 | 1001 | 0110 |
In the upper table, with the data of underscore, the expression readback data is wrong in the cell. Data representation readback data without underscore is normal. Wherein black increases the weight of the data representation misdata useful to fault location.
To the testing and diagnosing flow process of address wire open fault and short trouble, as shown in Figure 3, as follows with the pseudo-program language representation:
BEGIN
Analyze first the test response of walking 1
It is in full accord that IF reads the data of data and expectation
Report address wire walking 1 test of heuristics is not found fault;
ELSE
FOR analyzes each address except all zeros address
IF reads the data of all zeros address and makes mistakes, and the value of this address and all zeros address equates
Record, may be fixed logic 0 fault, abort situation is the address wire of the corresponding numeral in this address " 1 "
The data that ELSE IF reads all zeros address are unequal with the data of reading the current address, but the data that exist other a plurality of address to read back equate with it
Recording, is 1 dominance short trouble, the address wire short circuit of the different address bit of corresponding these several addresses
The data of ELSE IF all zeros address are made mistakes or to read data value and the desired value of current address inconsistent
The report fault type can't be judged, reports simultaneously which address is fault occur on.
ELSE
Fault is not found in this address
END FOR
Analyze first again the test response of walking 0
It is in full accord that IF reads the data of data and expectation
Report address wire walking 0 test of heuristics is not found fault;
ELSE
FOR analyzes each address except all ones address
IF reads the data of all ones address and makes mistakes, and equal with the value of this address
Record, may be fixed logic 1 fault, abort situation is the address wire of the corresponding digital " 0 " in this address
The data that ELSE IF reads all ones address are unequal with the data of reading the current address, but the data that exist other a plurality of address to read back equate with it
Recording, is 0 dominance short trouble, the address wire short circuit of the different address bit of corresponding these several addresses
The data of ELSE IF all ones address are made mistakes or to read data value and the desired value of current address inconsistent
The report fault type can't be judged, reports simultaneously which address is fault occur on.
ELSE
Fault is not found in this address
END FOR
At last diagnostic result is carried out analysis-by-synthesis
There is the address wire of fault in FOR
This address wire of IF is judged as 0-dominance short trouble or 1-dominance short trouble
Conclude that then this address wire is 0-dominance short trouble or 1-dominance short trouble
This address wire of ELSE IF is judged as fixed logic 0 fault or fixed logic 1 fault
Conclude that then this address wire is fixed logic 0 fault or fixed logic 1 fault
This address wire of ELSE IF is judged as fixed logic 0 fault or fixed logic 1 fault
Conclude that then this address wire is the fixed logic fault
ELSE
This address wire exist can't the failure judgement type fault
END FOR
END
Suppose that the address wire number is d, the data wire number is n, and then one always need to carry out the operation that 4* (n+d)+3 reads or writes to memory cell, also needs in addition erase operation four times. The inventive method all is 100% to the fault coverage of fixed logic fault (Stuck-at fault), stuck-open fault (Stuck-open fault) and bridge joint short trouble (Short fault), and can carry out accurately fault diagnosis, distinguish dissimilar short troubles, any test leakage situation can not occur.
In addition in the peripheral interconnecting test of FLASH, if there is fault in control line, whole mistakes of read-write operation then are so also can be diagnosed according to test result; If the fault effects of data wire or address wire writing of FLASH operational order word (Command Code), then the test result of FLASH occurs very large unusually, also can analyze out at an easy rate. So these faults are not done independent test, all can in data wire and the test of address wire ground, obtain detecting.
Claims (10)
1, a kind of method of testing of peripheral interconnection line is characterized in that, the method comprises the following steps:
1), with the dull fault of the data test data wire of a group complete " 0 " and complete " 1 ", if measured value is identical with desired value, then carry out the following step; If measured value is not identical with desired value, then dull fault occurs in the data wire of different position, carries out carrying out the following step after fault gets rid of again;
2), fix an address, with " 10 " triangle data matrix test data line, if measured value is identical with desired value, then carry out the following step; If measured value is not identical with desired value, then determine the short trouble position, carry out carrying out again the following step after fault gets rid of;
3), select one group of different address, with walking " 1 " data matrix test data line, if measured value is identical with desired value, then carry out the following step; If measured value is not identical with desired value, then determine the short trouble position, carry out carrying out again the following step after fault gets rid of;
4), address wire adopts walking " 1 " matrix, data wire adopts walking " 0 " matrix, the fault of test address line if measured value is identical with desired value, is then carried out the following step; If measured value is not identical with desired value, determine that then the appropriate address line is fixed logic 0 or 1-dominance short trouble, carry out carrying out again the following step after fault gets rid of;
5), address wire adopts walking " 0 " matrix, data wire adopts walking " 0 " matrix, the fault of test address line, if measured value is identical with desired value, then test end; If measured value is not identical with desired value, determine that then the appropriate address line is fixed logic 1 fault or 0-dominance short trouble, carry out fault and get rid of, finish test.
2, the method for testing of peripheral interconnection line as claimed in claim 1 is characterized in that: described step 1), if the measured value of a certain data wire is complete " 0 ", report that then 0 open fault has occured to be fixed as this data wire; If the measured value of a certain data wire is complete " 1 ", report that then 1 open fault has occured to be fixed as this data wire.
3, the method for testing of peripheral interconnection line as claimed in claim 1 or 2, it is characterized in that: described step 2) and step 3) in, if there are a plurality of row, its vector equates, its value reports then that for the result of the logic OR computing of the desired value of these several row 1-dominance short trouble has occured many data wires of respective column; If there are a plurality of row, its vector equates that its value reports then that for the result of the logic and operation of the desired value of these several row 0-dominance short trouble has occured many data wires of respective column.
4, the method for testing of peripheral interconnection line as claimed in claim 3, it is characterized in that: described step 4), if reading the data of all zeros address makes mistakes, current test address equates with the value of all zeros address, then may be fixed logic 0 fault, abort situation is the address wire of the corresponding numeral in current test address " 1 "; If it is unequal to read the data of the data of all zeros address and current address, but the data that exist other a plurality of address to read back equate with it, then be 1-dominance short trouble, the address wire short circuit of the different address bit of these several addresses of correspondence.
5, such as the method for testing of claim 1 or 4 described peripheral interconnection line, it is characterized in that: described step 5), if reading the data of all ones address makes mistakes, current test address equates with the value of all ones address, then may be fixed logic 1 fault, abort situation is the address wire of the corresponding digital " 0 " in current test address; If it is unequal to read the data of the data of all ones address and current address, but the data that exist other a plurality of address to read back equate with it, then be 0-dominance short trouble, the address wire short circuit of the different address bit of these several addresses of correspondence.
6, a kind of method of testing of peripheral interconnection line is characterized in that, the method comprises the following steps:
1) with the dull fault of the data test data wire of a group complete " 0 " and complete " 1 ", if measured value is identical with desired value, then carries out the following step; If measured value is not identical with desired value, then dull fault occurs in the data wire of different position, carries out carrying out the following step after fault gets rid of again;
2) fix an address, with " 01 " triangle data matrix test data line, if measured value is identical with desired value, then carry out the following step; If measured value is not identical with desired value, then determine the short trouble position, carry out carrying out again the following step after fault gets rid of;
3) select one group of different address, with walking " 1 " data matrix test data line, if measured value is identical with desired value, then carry out the following step; If measured value is not identical with desired value, then determine the short trouble position, carry out carrying out again the following step after fault gets rid of;
4) address wire adopts walking " 1 " matrix, and data wire adopts walking " 0 " matrix, and the fault of test address line if measured value is identical with desired value, is then carried out the following step; If measured value is not identical with desired value, determine that then the appropriate address line is fixed logic 0 or 1-dominance short trouble, carry out carrying out again the following step after fault gets rid of;
5) address wire adopts walking " 0 " matrix, and data wire adopts walking " 0 " matrix, the fault of test address line, if measured value is identical with desired value, then test finishes; If measured value is not identical with desired value, determine that then the appropriate address line is fixed logic 1 fault or 0-dominance short trouble, carry out fault and get rid of, finish test.
7, a kind of method of testing of peripheral interconnection line is characterized in that, the method comprises the following steps:
1) with the dull fault of the data test data wire of a group complete " 0 " and complete " 1 ", if measured value is identical with desired value, then carries out the following step; If measured value is not identical with desired value, then dull fault occurs in the data wire of different position, carries out carrying out the following step after fault gets rid of again;
2) fix an address, with " 01 " or " 10 " triangle data matrix test data line, if measured value is identical with desired value, then carry out the following step; If measured value is not identical with desired value, then determine the short trouble position, carry out carrying out again the following step after fault gets rid of;
3) select one group of different address, with walking " 1 " data matrix test data line, if measured value is identical with desired value, then carry out the following step; If measured value is not identical with desired value, then determine the short trouble position, carry out carrying out again the following step after fault gets rid of;
4) address wire adopts walking " 0 " matrix, and data wire adopts walking " 0 " matrix, and the fault of test address line if measured value is identical with desired value, is then carried out the following step; If measured value is not identical with desired value, determine that then the appropriate address line is fixed logic 1 fault or 0-dominance short trouble, carry out fault and get rid of, carry out again the following step;
5) address wire adopts walking " 1 " matrix, and data wire adopts walking " 0 " matrix, the fault of test address line, if measured value is identical with desired value, then test finishes; If measured value is not identical with desired value, determine that then the appropriate address line is fixed logic 0 or 1-dominance short trouble, carry out fault and get rid of, finish test.
8, the method for testing of peripheral interconnection line as claimed in claim 7, it is characterized in that: described step 2) and step 3) in, if there are a plurality of row, its vector equates, its value reports then that for the result of the logic OR computing of the desired value of these several row 1-dominance short trouble has occured many data wires of respective column; If there are a plurality of row, its vector equates that its value reports then that for the result of the logic and operation of the desired value of these several row 0-dominance short trouble has occured many data wires of respective column.
9, the method for testing of peripheral interconnection line as claimed in claim 7, it is characterized in that: described step 4), if reading the data of all zeros address makes mistakes, current test address equates with the value of all zeros address, then may be fixed logic 0 fault, abort situation is the address wire of the corresponding numeral in current test address " 1 "; If it is unequal to read the data of the data of all zeros address and current address, but the data that exist other a plurality of address to read back equate with it, then be 1-dominance short trouble, the address wire short circuit of the different address bit of these several addresses of correspondence.
10, the method for testing of peripheral interconnection line as claimed in claim 7, it is characterized in that: described step 5), if reading the data of all ones address makes mistakes, current test address equates with the value of all ones address, then may be fixed logic 1 fault, abort situation is the address wire of the corresponding digital " 0 " in current test address; If it is unequal to read the data of the data of all ones address and current address, but the data that exist other a plurality of address to read back equate with it, then be 0-dominance short trouble, the address wire short circuit of the different address bit of these several addresses of correspondence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101153557A CN100348992C (en) | 2003-11-19 | 2003-11-19 | Testing method of peripheral interconnecting wire |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101153557A CN100348992C (en) | 2003-11-19 | 2003-11-19 | Testing method of peripheral interconnecting wire |
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| CN1619326A true CN1619326A (en) | 2005-05-25 |
| CN100348992C CN100348992C (en) | 2007-11-14 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105788649A (en) * | 2014-12-23 | 2016-07-20 | 华为数字技术（苏州）有限公司 | Preprocessing method and apparatus for flash memory |
| CN108447524A (en) * | 2018-03-21 | 2018-08-24 | 清能德创电气技术（北京）有限公司 | A method of for detecting external memory interface failure |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5412260A (en) * | 1991-05-03 | 1995-05-02 | Lattice Semiconductor Corporation | Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device |
| US5809036A (en) * | 1993-11-29 | 1998-09-15 | Motorola, Inc. | Boundary-scan testable system and method |
| US5751737A (en) * | 1997-02-26 | 1998-05-12 | Hewlett-Packard Company | Boundary scan testing device |
| US6324663B1 (en) * | 1998-10-22 | 2001-11-27 | Vlsi Technology, Inc. | System and method to test internal PCI agents |
| GB2370364B (en) * | 2000-12-22 | 2004-06-30 | Advanced Risc Mach Ltd | Testing integrated circuits |
| US6738939B2 (en) * | 2001-05-21 | 2004-05-18 | Intel Corporation | Method and apparatus for fault tolerant and flexible test signature generator |
| CN1435695A (en) * | 2002-02-01 | 2003-08-13 | 华为技术有限公司 | Method for testing circuit board interconnction line based on boundary scanning device |
| CN1253794C (en) * | 2002-04-23 | 2006-04-26 | 华为技术有限公司 | Logic cluster fault testing method for non-boundary scanning device |
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2003
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105788649A (en) * | 2014-12-23 | 2016-07-20 | 华为数字技术（苏州）有限公司 | Preprocessing method and apparatus for flash memory |
| CN105788649B (en) * | 2014-12-23 | 2019-06-14 | 华为数字技术（苏州）有限公司 | A kind of preprocess method and device of flash memory |
| CN108447524A (en) * | 2018-03-21 | 2018-08-24 | 清能德创电气技术（北京）有限公司 | A method of for detecting external memory interface failure |
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| CN100348992C (en) | 2007-11-14 |
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