CN1614891A - Gate controlling circuit for raising transistor with nigh voltage input - Google Patents
Gate controlling circuit for raising transistor with nigh voltage input Download PDFInfo
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- CN1614891A CN1614891A CN 200310108419 CN200310108419A CN1614891A CN 1614891 A CN1614891 A CN 1614891A CN 200310108419 CN200310108419 CN 200310108419 CN 200310108419 A CN200310108419 A CN 200310108419A CN 1614891 A CN1614891 A CN 1614891A
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Abstract
In the circuit, the gate end (G) of voltage-pulling transistor is connected with gate control circuit. The source end (S) of voltage-pulling transistor is connected with the potential of power. The drain electrode (D) of voltage-pulling transistor is connected with node of welding-sheet, and the substrate of voltage-pulling is connected with a N-well. When the high voltage signal is applied, the gate control circuit is used to control the gate bias voltage of the voltage-pulling transistor.
Description
Technical field
The present invention refers to a kind of gate control circuit that is used for the pulled transistor of high voltage input especially about a kind of gate control circuit that is used for pulled transistor.
Background technology
Fig. 1 has schematically shown a known pulled transistor circuit, in this circuit, source terminal (S) and its substrate (B) of PMOS pulled transistor (MPU) 1 link together, be connected to power supply potential Vdd then, the gate terminal of transistor MPU 1 (G) is connected to Vss, and the drain electrode end of transistor MPU 1 (D) is connected to the drain electrode end (D) of nmos pass transistor MN1, the substrate of transistor MN1 (B) is connected to Vss, the gate terminal of transistor MN1 (G) is connected to power supply potential (Vdd), and the source terminal of transistor MN1 (S) is connected to weld pad (PAD).In the circuit of Fig. 1, because the gate terminal of nmos pass transistor MN1 (G) is connected to power supply potential (Vdd), so under normal condition, the current potential of weld pad node will be the source voltage of transistor MN1, therefore, weld pad voltage can be up to Vdd-Vtn.If this weld pad node is one of them input signal on the system circuit board, then can produce following problem.
(1) little noise tolerance limit:, then can reduce weld pad voltage according to this on power plane if noise is arranged.If weld pad voltage is the input critical voltage that is lower than on other wafers, then may the generation systems fault.
(2) leakage current: because weld pad voltage does not fully arrive power supply potential, so have leakage current in other wafers, this is because input signal can not make the PMOS transistor in other wafers end fully.
Therefore, in the circuit of Fig. 1, weld pad voltage can not fully rise and arrive the power supply potential current potential, so can cause the system failure because of little noise tolerance limit.
Fig. 2 has schematically shown another known pulled transistor circuit, in this circuit, the source terminal (S) that draws high PMOS transistor MPU 2 is connected to power supply potential (Vdd), the gate terminal of transistor MPU 2 (G) is connected to Vss, the substrate of pulled transistor MPU 2 (B) is connected to a N well, and the drain electrode end of pulled transistor MPU 2 (D) is connected to weld pad.
In the circuit of Fig. 2, between weld pad and the voltage difference that is used to draw high between the gate terminal (G) of pulled transistor MPU 2 of resistor can be also higher than gate oxide breakdown voltage and TDDB (time variable dielectric collapse) specification voltage.Therefore, in the circuit of Fig. 2, reliability issues can take place, for example TDDB.
In sum, when the high voltage signal is applied in weld pad,, then can produce reliability issues such as TDDB if people can not control the gate bias voltage of pulled transistor, and owing to less noise tolerance limit causes the system failure.
Summary of the invention:
The objective of the invention is to overcome the problem such as little noise tolerance limit, leakage current and TDDB of known pulled transistor circuit and a kind of gate control circuit that is used to draw high the pulled transistor that resistor uses is provided, so that give the weld pad node with the Vdd current potential, and enough noise tolerance limits, remove reliability issues substantially.
According to the present invention, a kind of circuit that is used for the gate control circuit of pulled transistor that comprises is provided, wherein, the gate terminal of pulled transistor (G) is connected to the gate control circuit, the source terminal of pulled transistor (S) is connected to power supply potential, the drain electrode end of pulled transistor (D) is connected to the weld pad node, and the substrate of pulled transistor (B) is connected to a N well, this circuit is characterised in that, when the high voltage signal was applied in, this gate control circuit was used to control the gate bias voltage of pulled transistor.
According to the present invention, a kind of gate control circuit that is used for pulled transistor is provided, it comprises two n passage MOSFETs and a p passage MOSFET.
According to the present invention, the gate control circuit that provides another kind to be used for pulled transistor, it uses multistage power supply.
According to the present invention, the gate control circuit that provides another kind to be used for pulled transistor, it comprises two nmos pass transistors and connects to constitute diode.
According to the present invention, the gate control circuit that provides another kind to be used for pulled transistor, its nmos pass transistor that comprises series connection more than two connects to constitute diode.
According to the present invention, the gate control circuit that provides another kind to be used for pulled transistor, it comprises two PMOS transistors and connects to constitute diode.
According to the present invention, the gate control circuit that provides another kind to be used for pulled transistor, its PMOS transistor that comprises series connection more than two connects to constitute diode.
According to the present invention, the gate control circuit that provides another kind to be used for pulled transistor, it comprises two passive resistors to form a voltage divider.
According to the present invention, the gate control circuit that provides another kind to be used for pulled transistor, it comprises two diodes to form a voltage divider.
According to the present invention, the gate control circuit that provides another kind to be used for pulled transistor, its cascade arrangement that comprises two groups of above diodes is as voltage divider.
According to the present invention, the gate control circuit that provides another kind to be used for pulled transistor, it comprises a nmos pass transistor and a PMOS transistor to constitute a bias circuit.
According to the present invention, the gate control circuit that provides another kind to be used for pulled transistor, it comprises plural nmos pass transistor and plural PMOS transistor to constitute bias circuit.
According to the present invention, the gate control circuit that provides another kind to be used for pulled transistor, it comprises a nmos pass transistor and a PMOS transistor to constitute an inverter.
Description of drawings
For advantage, feature and other purposes that can further understand the present invention, attachedly now be described in more detail in down with graphic.
Fig. 1 has schematically shown the circuit diagram of a known pulled transistor circuit.
Fig. 2 has schematically shown the circuit diagram of another known pulled transistor circuit.
Fig. 3 has schematically shown the circuit diagram according to representative circuit of the present invention.
The gate control circuit that Fig. 4 has schematically shown Fig. 3 is the circuit diagram of an embodiment wherein.
Fig. 5 has schematically shown the circuit diagram of foundation another representative circuit of the present invention of using multistage power supply.
Fig. 6 has shown the schematic circuit diagram according to gate control circuit of the present invention.
Fig. 7 has shown the schematic circuit diagram according to another gate control circuit of the present invention.
Fig. 8 has shown the schematic circuit diagram according to another gate control circuit of the present invention.
Fig. 9 has shown the schematic circuit diagram according to another gate control circuit of the present invention.
Figure 10 has shown the schematic circuit diagram according to another gate control circuit of the present invention.
Figure 11 has shown the schematic circuit diagram according to another gate control circuit of the present invention.
Figure 12 has shown the schematic circuit diagram according to another gate control circuit of the present invention.
Figure 13 has shown the schematic circuit diagram according to another gate control circuit of the present invention.
Figure 14 has shown the schematic circuit diagram according to another gate control circuit of the present invention.
Figure 15 has shown the schematic circuit diagram according to another gate control circuit of the present invention.
Embodiment
Now will illustrate according to preferred embodiment of the present invention with reference to accompanying drawing hereinafter.
Fig. 3 has shown according to the schematic circuit diagram that is used for the gate control circuit of pulled transistor that comprises of the present invention, in this circuit, the gate terminal of pulled transistor MPU 3 (G) is connected to gate control circuit 31, the source terminal of transistor MPU 3 (S) is connected to power supply potential (Vdd), the drain electrode end of transistor MPU 3 (D) is connected to weld pad (PAD) node, and the substrate of transistor MPU 3 (B) is connected to a N well.Being operating as when the high voltage signal is applied in of the circuit of Fig. 3, gate control circuit 31 is the gate bias voltages that are used for controlling pulled transistor MPU 3, that is to say, control the gate voltage of pulled transistor MPU 3 by gate control circuit 31, and the well bias voltage Be Controlled of transistor MPU 3 is to remove the leakage current between weld pad and the power supply potential Vdd.
The gate control circuit that Fig. 4 has shown Fig. 3 is the illustrative circuitry of an embodiment wherein, in this circuit, gate control circuit 41 is made of two n passage MOSFETs MN2 and MN3 and a p passage MOSFET MP1, wherein, the gate terminal of transistor MN2 and MN3 (G) is connected to Vdd (power supply), the drain electrode end of transistor MN2 (D) is connected to the gate terminal (G) of pulled transistor MPU 4, the drain electrode end (D) of the source terminal of transistor MN2 (S) and transistor MN3 links together, the source terminal of transistor MN3 (S) is connected to earthing potential (GND), and the substrate of transistor MN2 and MN3 (B) also is connected to GND.Moreover, the gate terminal of transistor MP1 (G) is connected to Vdd, the source terminal of transistor MP1 (S) or drain electrode end (D) are connected to gate terminal (G) or the PAD node of pulled transistor MPU 4 respectively, look closely the voltage of PAD and decide, and the change in voltage scope of PAD is to lie prostrate Vdd+ α from zero, and the substrate of transistor MP1 (B) is connected to a N well.That is to say, when PAD voltage during less than Vdd+Vtp (Vtp is the conducting voltage of transistor MP1), transistor MP1 will end, so the gate terminal of pulled transistor MPU 4 (G) voltage is zero, and when PAD voltage during greater than Vdd+Vtp and less than Vdd+Vtp+ α, transistor MP1 will conducting, so the gate terminal of pulled transistor MPU 4 (G) voltage equals PAD voltage.In addition, the source terminal of transistor MPU 4 (S) is connected to power supply potential, and the drain electrode end of transistor MPU 4 (D) is connected to the weld pad node, and the substrate of transistor MPU 4 (B) is connected to a N well.
With reference to Fig. 4, because transistor MN2 and MN3 are the very little transistor of ratio of width and length compared to transistor MP1, so under normal state, transistor MP1 closes, at this moment, the gate voltage of transistor MPU 4 is via nmos pass transistor MN2 and MN3 and be connected to ground connection.But, if be applied in the PAD node than the also high voltage of Vdd+Vthp (Vthp is the critical voltage of transistor MP1), then the gate voltage of transistor MPU 4 will rise and arrives PAD voltage, and people can give suitable size of the gate voltage of transistor MPU 4 and suitable bias voltage.This circuit has been arranged, under normal state, PAD voltage can be drawn high fully, if and higher voltage is applied in weld pad, then the gate voltage of transistor MPU 4 will be situated between between PAD voltage and ground connection, therefore, the voltage difference between the gate voltage of PAD node and transistor MPU 4 is less than the gate oxide breakdown voltage.Though PAD voltage is higher than the restriction of reliability specification, because the gate voltage of transistor MPU 4 system equals the voltage potential of PAD node, so there is not reliability issues to take place.
Fig. 5 is another representative circuit of the present invention, its use multistage (multi-1evel) power supply, and in this case, wherein the power supply of one-level is connected directly to the gate terminal (G) of pulled transistor.In the circuit of Fig. 5, the gate terminal of pulled transistor MPU 5 (G) is connected to VGC (it has the voltage potential between power supply and the ground connection), the source terminal of transistor MPU 5 (S) is connected to Vdd, the drain electrode end of transistor MPU 5 (D) is connected to the PAD node, and the substrate of transistor MPU 5 (B) is connected to the N well.
Under normal state, because the gate terminal of pulled transistor MPU 5 (G) is connected to VGC, so PAD voltage can be drawn high fully via drawing high PMOS transistor MPU 5, and because the voltage difference between the gate voltage of PAD node and transistor MPU 5 is less than the gate oxide breakdown voltage, so there is not reliability issues to take place.
The embodiment of foundation gate control circuit of the present invention is described to Figure 15 below with reference to Fig. 6.
Fig. 6 has schematically shown according to gate control circuit of the present invention, wherein, uses two nmos pass transistors to constitute diode and connects.In the circuit of Fig. 6, gate control circuit 61 comprises two n passage MOSFETsMN4 and MN5, in this circuit, the gate terminal of nmos pass transistor MN5 (G) is connected with its drain electrode end (D), and then be connected to Vdd, the gate terminal of nmos pass transistor MN4 (G) is connected to its drain electrode end (D), and the source terminal (S) of the drain electrode end of transistor MN4 (D) and transistor MN5 is connected, and then be connected to the gate terminal (G) of pulled transistor MPU 6, the source terminal of transistor MN4 (S) is connected to GND, and the substrate of transistor MN4 and MN5 (B) also is connected to GND.In addition, the source terminal of pulled transistor MPU 6 (S) is connected to power supply potential (Vdd), and the drain electrode end of transistor MPU 6 (D) is connected to the PAD node, and the substrate of transistor MPU 6 (B) is connected to a N well.
At this moment, the gate voltage that draws high PMOS transistor MPU 6 is between power supply and ground connection.With the explanation of Fig. 5 in the same manner, PAD voltage can be pulled up to power supply potential fully, and because be less than the gate oxide breakdown voltage at gate voltage and the voltage difference between PAD voltage of transistor MPU 6, so there is not the reliability issues generation.
Fig. 7 has schematically shown according to another gate control circuit of the present invention, wherein, uses the nmos pass transistor of series connection more than two to constitute the diode connection.In the circuit of Fig. 7, gate control circuit 71 comprises four n passage MOSFETs MN6, MN7, MN8, and MN9, in this circuit, transistor MN6 and MN7 form one group of diode and connect, and the gate terminal of transistor MN7 (G) and its drain electrode end (D) link together, and then are connected to Vdd, the gate terminal of transistor MN6 (G) and its drain electrode end (D) link together, and then are connected to the source terminal (S) of transistor MN7.Simultaneously, transistor MN8 and MN9 form another group diode and connect, and the gate terminal of transistor MN9 (G) is connected to its drain electrode end (D), the gate terminal of transistor MN8 (G) and its drain electrode end (D) link together, and then be connected to the source terminal (S) of transistor MN9, and the source terminal of transistor MN8 (S) is connected to GND.In addition, the drain electrode end (D) of the source terminal of transistor MN6 (S) and transistor MN9 is connected, and then is connected to the gate terminal (G) of pulled transistor MPU 7, and transistor MN6, MN7, and MN8, and the substrate (B) of MN9 is connected to GND together.
Moreover the source terminal of pulled transistor MPU 7 (S) is connected to power supply potential (Vdd), and the drain electrode end of transistor MPU 7 (D) is connected to PAD, and the substrate of transistor MPU 7 (B) is connected to a N well.The operation of the circuit of Fig. 7 is identical with the operation of the circuit of Fig. 6, is between power supply and ground connection so draw high the gate voltage of PMOS transistor MPU 7.Similarly, PAD voltage can be pulled up to power supply potential fully, and because be less than the gate oxide breakdown voltage at gate voltage and the voltage difference between PAD voltage of transistor MPU 7, so there is not the reliability issues generation.
Fig. 8 has schematically shown according to another gate control circuit of the present invention, wherein, uses the PMOS transistor to constitute diode and connects.In the circuit of Fig. 8, gate control circuit 81 comprises two p passage MOSFETsMP2 and MP3, in this circuit, the gate terminal of transistor MP3 (G) is connected to its drain electrode end (D), and the source terminal of transistor MP3 (S) is connected to Vdd, the gate terminal of transistor MP2 (G) is connected to its drain electrode end (D), and the drain electrode end (D) of the source terminal of transistor MP2 (S) and transistor MP3 is connected, and then be connected to the gate terminal (G) of pulled transistor MPU 8, the drain electrode end of transistor MP2 (D) is connected to GND, and the substrate of transistor MP2 and MP3 (B) also is connected to Vdd together.
In addition, the source terminal of pulled transistor MPU 8 (S) is connected to power supply potential (Vdd), and the drain electrode end of transistor MPU 8 (D) is connected to PAD, and the substrate of transistor MPU 8 (B) is connected to a N well.The operation of the circuit of Fig. 8 is identical with the operation of the circuit of Fig. 6, is between power supply and ground connection so draw high the gate voltage of PMOS transistor MPU 8.Similarly, PAD voltage can be pulled up to power supply potential fully, and because be less than the gate oxide breakdown voltage at gate voltage and the voltage difference between PAD voltage of transistor MPU 8, so there is not the reliability issues generation.
Fig. 9 illustrates to show according to another gate control circuit of the present invention, wherein, uses the PMOS transistor of series connection more than two to constitute the diode connection.In the circuit of Fig. 9, gate control circuit 91 comprises four p passage MOSFETs MP4, MP5, MP6, and MP7 are in this circuit, transistor MP4 and MP5 form one group of diode and connect, and the gate terminal of transistor MP4 and MP5 (G) is connected to its drain electrode end (D) respectively, and the source terminal of transistor MP5 (S) is connected to Vdd, and the source terminal of transistor MP4 (S) is connected to the drain electrode end (D) of transistor MP5.Simultaneously, transistor MP6 and MP7 form another group diode and connect, and the gate terminal of transistor MP6 and MP7 (G) is connected to its drain electrode end (D) respectively, and the source terminal of transistor MP6 (S) is connected to the drain electrode end (D) of transistor MP7, and the drain electrode end of transistor MP6 (D) is connected to GND.In addition, the source terminal (S) of the drain electrode end of transistor MP4 (D) and transistor MP7 is connected, and then is connected to the gate terminal (G) of pulled transistor MPU 9, and transistor MP4, MP5, and MP6, and the substrate (B) of MP7 is connected to Vdd together.
Moreover the source terminal of pulled transistor MPU 9 (S) is connected to power supply potential (Vdd), and the drain electrode end of transistor MPU 9 (D) is connected to PAD, and the substrate of transistor MPU 9 (B) is connected to a N well.The operation of the circuit of Fig. 9 is identical with the operation of the circuit of Fig. 6, is between power supply and ground connection so draw high the gate voltage of PMOS transistor MPU 9.Similarly, PAD voltage can be pulled up to power supply potential fully, and because be less than the gate oxide breakdown voltage at gate voltage and the voltage difference between PAD voltage of transistor MPU 9, so there is not the reliability issues generation.
Figure 10 has schematically shown according to another gate control circuit of the present invention, wherein, has used two passive resistors as voltage divider.In the circuit of Figure 10, gate control circuit 101 comprises two resistor R 1 and R2, wherein, first end of resistor R 1 is connected to Vdd, second end of resistor R 1 is connected with first end of resistor R 2, and then be connected to the gate terminal (G) of pulled transistor MPU 10, and second end of resistor R 2 is connected to GND.
In addition, the source terminal of pulled transistor MPU 10 (S) is connected to power supply potential (Vdd), and the drain electrode end of transistor MPU 10 (D) is connected to PAD, and the substrate of transistor MPU 10 (B) is connected to a N well.The operation of the circuit of Figure 10 is identical with the operation of the circuit of Fig. 6, is between power supply and ground connection so draw high the gate voltage of PMOS transistor MPU 10.Similarly, PAD voltage can be pulled up to power supply potential fully, and because be less than the gate oxide breakdown voltage at gate voltage and the voltage difference between PAD voltage of transistor MPU 10, so there is not the reliability issues generation.
Figure 11 has schematically shown according to another gate control circuit of the present invention, wherein, has used two diodes as voltage divider.In the circuit of Figure 11, gate control circuit 111 comprises two diode D1 and D2, wherein, the anode tap of diode D1 is connected to Vdd, the cathode terminal of diode D1 is connected with the anode tap of diode D2, and then be connected to the gate terminal (G) that draws high PMOS transistor MPU 11, and the cathode terminal of diode D2 is connected to GND.
In addition, the source terminal of pulled transistor MPU 11 (S) is connected to power supply potential (Vdd), and the drain electrode end of transistor MPU 11 (D) is connected to PAD, and the substrate of transistor MPU 11 (B) is connected to a N well.The operation of the circuit of Figure 11 is identical with the operation of the circuit of Fig. 6, is between power supply and ground connection so draw high the gate voltage of PMOS transistor MPU 11.Similarly, PAD voltage can be pulled up to power supply potential fully, and because at the gate voltage of transistor MPU 11 and the voltage difference between PAD voltage less than the gate oxide breakdown voltage, so there is not the reliability issues generation.
Figure 12 has shown schematically that according to another gate control circuit of the present invention wherein, the cascade arrangement of using two groups of above diodes is as voltage divider.In the circuit of Figure 12, gate control circuit 121 comprises four diode D3, D4, D5, and D6, in this circuit, diode D1 and D2 form first group of diode cascade arrangement, and diode D3 and D4 form second group of diode cascade arrangement, and the anode tap of first group of cascade arrangement diode is connected to Vdd, and the cathode terminal of first group of cascade arrangement diode is connected with the anode tap of second group of cascade arrangement diode, and then be connected to the gate terminal (G) that draws high PMOS transistor MPU 12, and the cathode terminal of second group of cascade arrangement diode is connected to GND.
In addition, the source terminal of pulled transistor MPU 12 (S) is connected to power supply potential (Vdd), and the drain electrode end of transistor MPU 12 (D) is connected to PAD, and the substrate of transistor MPU 12 (B) is connected to a N well.The operation of the circuit of Figure 12 is identical with the operation of the circuit of Fig. 6, is between power supply and ground connection so draw high the gate voltage of PMOS transistor MPU 12.Similarly, PAD voltage can be pulled up to power supply potential fully, and because at the gate voltage of transistor MPU 12 and the voltage difference between PAD voltage less than the gate oxide breakdown voltage, so there is not the reliability issues generation.
Figure 13 has schematically shown according to another gate control circuit of the present invention, wherein, has used a nmos pass transistor and a PMOS transistor to constitute bias circuit.In the circuit of Figure 13, gate control circuit 131 comprises a PMOS transistor MP8 and is connected to form diode with a nmos pass transistor MN10, in this circuit, the gate terminal (G) of PMOS transistor MP8 and the gate terminal (G) of nmos pass transistor MN10 are connected, and then be connected to the gate terminal (G) that draws high PMOS transistor MPU 13, source terminal (S) and its substrate (B) of PMOS transistor MP8 link together, and then be connected to Vdd, the drain electrode end (D) of PMOS transistor MP8 and the drain electrode end (D) of nmos pass transistor MN10 are connected, and then be connected to the gate terminal (G) that draws high PMOS transistor MPU 13, and the source terminal of nmos pass transistor MN10 (S) and its substrate (B) link together, and then are connected to GND.
In addition, the source terminal of pulled transistor MPU 13 (S) is connected to power supply potential (Vdd), and the drain electrode end of transistor MPU 13 (D) is connected to PAD, and the substrate of transistor MPU 13 (B) is connected to a N well.The operation of the circuit of Figure 13 is identical with the operation of the circuit of Fig. 6, is between power supply and ground connection so draw high the gate voltage of PMOS transistor MPU 13.Similarly, PAD voltage can be pulled up to power supply potential fully, and because be less than the gate oxide breakdown voltage at gate voltage and the voltage difference between PAD voltage of transistor MPU 13, so there is not the reliability issues generation.
Figure 14 has schematically shown according to another gate control circuit of the present invention, wherein, has used plural nmos pass transistor and plural PMOS transistor to constitute bias circuit.In the circuit of Figure 14, gate control circuit 141 comprises two PMOS transistor MP9 and MP10 and two nmos pass transistor MN11 and MN12, in this circuit, PMOS transistor MP9 and MP10 form first group of cascade arrangement, and the source terminal (S) of the substrate of transistor MP9 and MP10 (B) and transistor MP9 links together, and then being connected to Vdd, the gate terminal of transistor MP9 (G) is connected to its drain electrode end (D), and then is connected with the source terminal (S) of transistor MP10.Simultaneously, nmos pass transistor MN11 and MN12 form second group of cascade arrangement, and the source terminal (S) of the substrate of transistor MN11 and MN12 (B) and transistor MN11 links together, and then be connected to GND, the gate terminal of transistor MN12 (G) is connected to its drain electrode end (D), and then is connected with source terminal (S) drain electrode end (D) of transistor MN11.Moreover, the gate terminal (G) of the gate terminal (G) of the transistor MP10 of first group of cascade arrangement and the transistor MN11 of second group of cascade arrangement is connected, and then be connected to the gate terminal (G) that draws high PMOS transistor MPU 14, the drain electrode end (D) of the drain electrode end (D) of the transistor MP10 of first group of cascade arrangement and the transistor MN11 of second group of cascade arrangement is connected, and then is connected to the gate terminal (G) that draws high PMOS transistor MPU 14.
In addition, the source terminal of pulled transistor MPU 14 (S) is connected to power supply potential (Vdd), and the drain electrode end of transistor MPU 14 (D) is connected to PAD, and the substrate of transistor MPU 14 (B) is connected to a N well.The operation of the circuit of Figure 14 is identical with the operation of the circuit of Fig. 6, is between power supply and ground connection so draw high the gate voltage of PMOS transistor MPU 14.Similarly, PAD voltage can be pulled up to power supply potential fully, and because be less than the gate oxide breakdown voltage at gate voltage and the voltage difference between PAD voltage of transistor MPU 14, so there is not the reliability issues generation.
Figure 15 has schematically shown according to another gate control circuit of the present invention, wherein, has used a nmos pass transistor and a PMOS transistor to constitute bias circuit.In the circuit of Figure 15, gate control circuit 151 comprises a PMOS transistor MP11 and a nmos pass transistor MN13, to form an inverter, in this circuit, the drain electrode end of transistor MP11 and MN13 (D) is connected to the gate terminal (G) that draws high resistor transistor MPU 15, the gate terminal of transistor MP11 and MN13 (G) is connected to Res_en, the source terminal of transistor MP11 (S) is connected to the drain electrode end (D) that draws high resistor transistor MPU 15, the source terminal of transistor MN13 (S) is connected to VGC, and the VGC employed wherein a kind of power supply that is native system and must be lower than the Vdd current potential, and the substrate of transistor MN13 (B) is connected to GND.
In addition, the source terminal of pulled transistor MPU 15 (S) is connected to power supply potential (Vdd), and the drain electrode end of transistor MPU 15 (D) is connected to PAD, and the substrate of transistor MPU 15 (B) is connected to a N well.
The operation of the circuit of Figure 15 is as follows, if Res_en is input as logic " height ", the gate terminal (G) that then draws high resistor transistor MPU 15 is connected to VGC, its have power supply and ground connection between voltage potential, and the operation of the circuit of the operation of this circuit and Fig. 6 is identical, ties up between power supply and the ground connection so draw high the gate voltage of PMOS transistor MPU 15.Similarly, PAD voltage can be pulled up to power supply potential fully, and because be less than the gate oxide breakdown voltage at gate voltage and the voltage difference between PAD voltage of transistor MPU 15, so there is not the reliability issues generation.If Res_en is input as logic " low ", then the gate terminal of pulled transistor MPU 15 (G) is connected to power supply (Vdd), and therefore, this pulled transistor MPU 15 is failure to actuate.
Therefore, control the gate voltage of pulled transistor by the gate bias control circuit, the foundation gate control circuit that is used for pulled transistor of the present invention can solve the problems such as little noise tolerance limit, leakage current and TDDB of known pulled transistor circuit, removes reliability issues substantially.
So by the detailed description of aforementioned gate control circuit embodiment of the present invention as can be known, the invention provides a kind of gate control circuit that is used for pulled transistor of novelty, can improve the shortcoming of known pulled transistor circuit effectively.
Claims (13)
1, a kind of circuit that is used for the gate control circuit of pulled transistor that comprises, wherein, the gate terminal (G) of pulled transistor (MPU) is connected to the gate control circuit, the source terminal of pulled transistor (S) is connected to power supply potential (Vdd), the drain electrode end of pulled transistor (D) is connected to weld pad (PAD) node, and the substrate of pulled transistor (B) is connected to a N well, this circuit is characterised in that, when the high voltage signal was applied in, this gate control circuit was the gate bias voltage that is used for controlling pulled transistor.
2, circuit as claimed in claim 1 is characterized in that, the gate control circuit comprises:
Two n passage MOSFETs MN2 and MN3, wherein, the gate terminal of transistor MN2 and MN3 (G) is connected to power supply (Vdd), the drain electrode end of transistor MN2 (D) is connected to the gate terminal (G) of pulled transistor, the source terminal of transistor MN2 (S) is connected to the drain electrode end (D) of transistor MN3, the source terminal of transistor MN3 (S) is connected to earthing potential (GND), and the substrate of transistor MN2 and MN3 (B) also is connected to GND;
One p passage MOSFET MP1, wherein, the gate terminal of transistor MP1 (G) is connected to Vdd, and the source terminal of transistor MP1 (S) or drain electrode end (D) are connected to the gate terminal (G) or the PAD node of pulled transistor respectively, and the substrate of transistor MP1 (B) is connected to a N well.
3, circuit as claimed in claim 1 is characterized in that,
The gate terminal of pulled transistor (G) is connected to VGC, and the source terminal of pulled transistor (S) is connected to Vdd, and the drain electrode end of pulled transistor (D) is connected to the PAD node, and the substrate of pulled transistor (B) is connected to the N well.
4, circuit as claimed in claim 1 is characterized in that, the gate control circuit comprises:
Two n passage MOSFETs MN4 and MN5, connect to form one group of diode, wherein, the gate terminal of transistor MN5 (G) is connected to its drain electrode end (D), and the drain electrode end of transistor MN5 (D) is connected to Vdd, the gate terminal of transistor MN4 (G) is connected to its drain electrode end (D), and the source terminal (S) of the drain electrode end of transistor MN4 (D) and transistor MN5 is connected, and then be connected to the gate terminal (G) of pulled transistor, the source terminal of transistor MN4 (S) is connected to GND, and the substrate of transistor MN4 and MN5 (B) also is connected to GND.
5, circuit as claimed in claim 1 is characterized in that, the gate control circuit comprises:
Four n passage MOSFETs MN6, MN7, MN8, and MN9, connect to form two groups of diodes, wherein, transistor MN6 and MN7 form first group of diode and connect, and wherein, the gate terminal of transistor MN7 (G) is connected to its drain electrode end (D), and the drain electrode end of transistor MN7 (D) is connected to Vdd, and the gate terminal of transistor MN6 (G) is connected to its drain electrode end (D), and the drain electrode end of transistor MN6 (D) is connected to the source terminal (S) of transistor MN7; Transistor MN8 and MN9 form second group of diode and connect, and wherein, the gate terminal of transistor MN9 (G) is connected to its drain electrode end (D), the gate terminal of transistor MN8 (G) is connected to its drain electrode end (D), and the drain electrode end of transistor MN8 (D) is connected to the source terminal (S) of transistor MN9, the source terminal of transistor MN8 (S) is connected to GND
And wherein, the drain electrode end (D) of the source terminal of transistor MN6 (S) and transistor MN9 is connected, and then is connected to the gate terminal (G) of pulled transistor, and transistor MN6, MN7, and MN8, and the substrate (B) of MN9 is connected to GND together.
6, circuit as claimed in claim 1 is characterized in that, the gate control circuit comprises:
Two p passage MOSFETs MP2 and MP3, connect to form one group of diode, wherein, the gate terminal of transistor MP3 (G) is connected to its drain electrode end (D), and the source terminal of transistor MP3 (S) is connected to Vdd, the gate terminal of transistor MP2 (G) is connected to its drain electrode end (D), and the drain electrode end (D) of the source terminal of transistor MP2 (S) and transistor MP3 is connected, and then be connected to the gate terminal (G) of pulled transistor, the drain electrode end of transistor MP2 (D) is connected to GND, and the substrate of transistor MP2 and MP3 (B) also is connected to Vdd together.
7, circuit as claimed in claim 1 is characterized in that, the gate control circuit comprises:
Four p passage MOSFETs MP4, MP5, MP6, and MP7, connect to form two groups of diodes, wherein, transistor MP4 and MP5 form first group of diode and connect, and wherein, the gate terminal of transistor MP5 (G) is connected to its drain electrode end (D), and the source terminal of transistor MP5 (S) is connected to Vdd, and the gate terminal of transistor MP4 (G) is connected to its drain electrode end (D), and the source terminal of transistor MP4 (S) is connected to the drain electrode end (D) of transistor MP5; Transistor MP6 and MP7 form second group of diode and connect, and wherein, the gate terminal of transistor MP7 (G) is connected to its drain electrode end (D), the gate terminal of transistor MP6 (G) is connected to its drain electrode end (D), and the source terminal of transistor MP6 (S) is connected to the drain electrode end (D) of transistor MP7, the drain electrode end of transistor MP6 (D) is connected to GND
And wherein, the source terminal (S) of the drain electrode end of transistor MP4 (D) and transistor MP7 is connected, and then is connected to the gate terminal (G) of pulled transistor, and transistor MP4, MP5, and MP6, and the substrate (B) of MP7 is connected to Vdd together.
8, circuit as claimed in claim 1 is characterized in that, the gate control circuit comprises:
Two resistor R 1 and R2 are to form a voltage divider, wherein, first end of resistor R 1 is connected to Vdd, second end of resistor R 1 is connected with first end of resistor R 2, and then is connected to the gate terminal (G) of pulled transistor, and second end of resistor R 2 is connected to GND.
9, circuit as claimed in claim 1 is characterized in that, the gate control circuit comprises:
Two diode D1 and D2, to form a voltage divider, wherein, the anode tap of the first diode D1 is connected to Vdd, the cathode terminal of the first diode D1 is connected with the anode tap of the second diode D2, and then be connected to and draw high the transistorized gate terminal of PMOS (G), and the cathode terminal of the second diode D2 is connected to GND.
10, circuit as claimed in claim 1 is characterized in that, the gate control circuit comprises:
4 diode D3, D4, D5, and D6, to form two groups of cascade arrangements, wherein, diode D3 and D4 form first group of cascade arrangement, and diode D5 and D6 form second group of cascade arrangement, and wherein, the anode tap of first group of cascade arrangement diode is connected to Vdd, and the cathode terminal of first group of cascade arrangement diode is connected with the anode tap of second group of cascade arrangement diode, and then be connected to and draw high the transistorized gate terminal of PMOS (G), and the cathode terminal of second group of cascade arrangement diode is connected to GND.
11, circuit as claimed in claim 1 is characterized in that, the gate control circuit comprises:
An one PMOS transistor MP8 and a nmos pass transistor MN10, connect to form one group of diode, wherein, the gate terminal (G) of PMOS transistor MP8 and the gate terminal (G) of nmos pass transistor MN10 are connected, and then be connected to and draw high the transistorized gate terminal of PMOS (G), source terminal (S) and its substrate (B) of PMOS transistor MP8 link together, and then be connected to Vdd, the drain electrode end (D) of PMOS transistor MP8 and the drain electrode end (D) of nmos pass transistor MN10 are connected, and then be connected to and draw high the transistorized gate terminal of PMOS (G), and the source terminal of nmos pass transistor MN10 (S) and its substrate (B) link together, and then are connected to GND.
12, circuit as claimed in claim 1 is characterized in that, the gate control circuit comprises:
Two PMOS transistor MP9 and MP10 and bi-NMOS transistor MN11 and MN12, to form two groups of cascade arrangements, wherein, PMOS transistor MP9 and MP10 form first group of cascade arrangement, and wherein, the source terminal (S) of the substrate of transistor MP9 and MP10 (B) and transistor MP9 links together, and then is connected to Vdd, the gate terminal of transistor MP9 (G) is connected to its drain electrode end (D), and then is connected with the source terminal (S) of transistor MP10; Nmos pass transistor MN11 and MN12 form second group of cascade arrangement, and wherein, the source terminal (S) of the substrate of transistor MN11 and MN12 (B) and transistor MN11 links together, and then be connected to GND, the gate terminal of transistor MN12 (G) is connected to its drain electrode end (D), and then be connected with the source terminal (S) of transistor MN11
And wherein, the gate terminal (G) of the gate terminal (G) of the transistor MP10 of first group of cascade arrangement and the transistor MN11 of second group of cascade arrangement is connected, and then be connected to and draw high the transistorized gate terminal of PMOS (G), the drain electrode end (D) of the drain electrode end (D) of the transistor MP10 of first group of cascade arrangement and the transistor MN11 of second group of cascade arrangement is connected, and then is connected to and draws high the transistorized gate terminal of PMOS (G).
13, circuit as claimed in claim 1 is characterized in that, the gate control circuit comprises:
An one PMOS transistor MP11 and a nmos pass transistor MN13, to form an inverter, wherein, the drain electrode end of transistor MP11 and MN13 (D) is connected to and draws high the transistorized gate terminal of resistor (G), the gate terminal of transistor MP11 and MN13 (G) is connected to Res_en, the source terminal of transistor MP11 (S) is connected to and draws high the transistorized source terminal of resistor (S), and the source terminal of transistor MN13 (S) is connected to VGC, and the substrate of transistor MN13 (B) is connected to GND.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101084190A CN1293703C (en) | 2003-11-05 | 2003-11-05 | Gate controlling circuit for raising transistor with nigh voltage input |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101084190A CN1293703C (en) | 2003-11-05 | 2003-11-05 | Gate controlling circuit for raising transistor with nigh voltage input |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610079822 Division CN1921314A (en) | 2003-11-05 | 2003-11-05 | Grid electrode control circuit of up-draw transistor for high-voltage input |
| CNB2006100798214A Division CN100452654C (en) | 2003-11-05 | 2003-11-05 | Grid electrode control circuit of up-draw transistor for high-voltage input |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1614891A true CN1614891A (en) | 2005-05-11 |
| CN1293703C CN1293703C (en) | 2007-01-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101084190A Expired - Lifetime CN1293703C (en) | 2003-11-05 | 2003-11-05 | Gate controlling circuit for raising transistor with nigh voltage input |
Country Status (1)
| Country | Link |
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| CN (1) | CN1293703C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100547928C (en) * | 2006-12-14 | 2009-10-07 | 威盛电子股份有限公司 | Drawing upwardly device |
| CN102487278A (en) * | 2010-12-01 | 2012-06-06 | 晨星软件研发(深圳)有限公司 | Low-leakage output/input circuit and related device |
| US11146088B2 (en) | 2019-06-27 | 2021-10-12 | Acer Incorporated | Power control circuit and power control method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5381061A (en) * | 1993-03-02 | 1995-01-10 | National Semiconductor Corporation | Overvoltage tolerant output buffer circuit |
| JP3400294B2 (en) * | 1997-04-25 | 2003-04-28 | 富士通株式会社 | Pull-up circuit and semiconductor device |
| US6545506B1 (en) * | 1999-03-12 | 2003-04-08 | Silable, Inc. | CMOS output driver that can tolerant a high input voltage |
-
2003
- 2003-11-05 CN CNB2003101084190A patent/CN1293703C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100547928C (en) * | 2006-12-14 | 2009-10-07 | 威盛电子股份有限公司 | Drawing upwardly device |
| CN102487278A (en) * | 2010-12-01 | 2012-06-06 | 晨星软件研发(深圳)有限公司 | Low-leakage output/input circuit and related device |
| CN102487278B (en) * | 2010-12-01 | 2017-08-04 | 晨星软件研发(深圳)有限公司 | The output/input circuit and relevant apparatus of Low dark curient |
| US11146088B2 (en) | 2019-06-27 | 2021-10-12 | Acer Incorporated | Power control circuit and power control method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1293703C (en) | 2007-01-03 |
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