CN1614436A - Method and device for inspecting circuit board - Google Patents
Method and device for inspecting circuit board Download PDFInfo
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Abstract
A method for detecting circuit board includes using microprocessor to record state, variation time and state variation frequency of each potential variation at each test point in waiting period for power on test as well as to record the same items in the same condition for power fail test of qualified circuit board; recording above times of detected circuit board by microprocessor and determining whether the detected circuit board is on specification or not by comparing the two.
Description
Technical field
The present invention relates to electric detective technology, specifically to the detection method of circuit board.
Background technology
Electron trade to the board production checkout procedure in, for whether the decision circuitry plate is qualified, one several test point of process inspection circuit board need be set in the precedence (to mistiming accuracy requirement successively and not really high) that powers on, logic level (high and low level two states) when cutting off the power supply and logic level change afterwards and each point change.This procedure often shows the state of measured point with a plurality of pilot lamp, by the state variation of eye-observation lamp, and each lamp change order (being sequential).This method by eye-observation is easy to occur subjective erroneous judgement.
Summary of the invention
The technical problem to be solved in the present invention is by the whole process of microprocessor monitors, and the result whether final output is qualified is to avoid artificial misjudgment phenomenon.
Realize the technical scheme of above-mentioned purpose: a kind of method of testing circuit plate comprises the steps:
1) determines test point;
2) the reference signal access point of low level signaling point as microprocessor appears when selecting one to occur high level, outage immediately on the circuit board when circuit board powers on immediately;
3) described each test point of step 1) on the qualified circuit board is inserted each pin of microprocessor (P1) and with step 2) described signaling point inserts microprocessor as reference signal, following detection data by each test point on the qualified circuit board of microprocessor records: state, time and state variation number of times when changing after the variation of current potential each time of each test point within the test wait time that powers on, state, time and state variation number of times when changing after the variation of current potential each time of each test point within the power down test wait time;
4) described each test point of step 1) on the circuit board to be detected is inserted each pin of microprocessor (P1) and with step 2) described signaling point inserts microprocessor as reference signal, following detection data by described each test point of step 1) on the microprocessor records circuit board to be detected: step 3) state after the variation of current potential each time of each test point within the described test wait time that powers on, time during variation and state variation number of times, step 3) state after the variation of current potential each time of each test point within the described power down test wait time, time during variation and state variation number of times;
5) in the process that step 4) is carried out, the circuit board detecting data to be detected with microprocessor records compare with the corresponding detection of the qualified circuit board data of step 3) record simultaneously;
6) if the comparative result of step 5) is unequal, then provide error message; Otherwise, continue execution in step 4), treat that step 5) is finished, provide qualified information.
Adopt technique scheme, beneficial technical effects of the present invention is: by with the state of each measured point of the automatic testing circuit plate of microprocessor, change and send detection information, avoid occurring the subjective misjudgment phenomenon that produces.The pick-up unit of making according to the present invention is with low cost, the detection efficiency height, and economic benefit is obvious.
Description of drawings
Fig. 1 is a kind of test mode of learning process flow diagram of method of testing circuit plate.
Fig. 2 is a kind of test pattern process flow diagram of method of testing circuit plate.
Fig. 3 (a) and (b), (c) are respectively a kind of examples of " tables of data " structure of powering on.
Fig. 4 is circuit theory diagrams of realizing the method for testing circuit plate.
Fig. 5 is the pin state variation sequential chart of corresponding diagram 3.
Embodiment
In conjunction with Fig. 1-4, a kind of method of testing circuit plate comprises the steps:
1) determines 8 of test points;
2) the reference signal access point of low level signaling point as microprocessor appears when selecting one to occur high level, outage immediately on the circuit board when circuit board powers on immediately;
3) described each test point of step 1) on the qualified circuit board being inserted each pin of microprocessor (P10-P17), with step 2) described signaling point inserts microprocessor INT0 as reference signal (NORM);
4) " the pin state variation number of times " storage space that powers on is clear 0, and power on " pin changes the back state ", " time when pin changes " each byte of storage unit are put 0FFH;
5) the reference signal rising edge then, open timer, get the variable condition data (shown in Fig. 3 (a)) of the test point current potential of pin P1 detection, and be kept at storer first address space, also be saved in the storer second address space correspondence " pin state when powering on " storage unit;
6) detect whether exceed given powering on 5 seconds learning test stand-by period,, then change step 10, otherwise continuation is carried out in proper order if overtime;
7) get pin P1 data, judge whether to equate, carry out if equate then to return previous step, otherwise continuation is carried out in proper order with first address space storage data;
8) find out the state variation pin according to the position of not waiting, and this pin correspondence " pin state variation number of times " internal storage location that powers on added 1 (shown in Fig. 3 (c)), betray disconnected whether exceeding 2 times, if exceed 2 times, then provide error message, otherwise, pin data is transferred to the first address space unit (shown in Fig. 3 (c)), order is carried out;
9) and at storer first address space (changing) note power on " pin changes the back state ", " time when pin changes " (shown in Fig. 3 (a) and (b)) of this pin, change step 6) according to this pin current state change frequency and which pin;
" pin changes the back state ", " time when pin changes " and " tables of data " such as " pin state variation number of times " of 10) first address space being stored are saved in storer second address space " tables of data " storage unit, and sending out powers on learns to finish information;
11) clear 0 to power down " pin state variation number of times " storage space, power down " pin changes the back state ", " time when pin changes " each byte of storage unit are put 0FFH;
12) when the reference signal negative edge then, open timer, get the variable condition data of the test point current potential that pin (P1) detects, and be saved in " pin state during power down " storage unit of storer first address space and the storer second address space correspondence respectively;
13) detect whether exceed 5 seconds given power down learning test stand-by period,, then change step 17, otherwise continuation is carried out in proper order if overtime;
14) get pin P1 data, judge whether to equate, carry out if equate then to return previous step, otherwise continuation is carried out in proper order with first address space storage data;
15) find out the state variation pin according to the position of not waiting, and corresponding power down " the pin state variation number of times " internal storage location of this pin added 1, whether the disconnected pin state variation number of times of betraing exceeds 2 times, if exceed 2 times, then provide error message, side is not transferred to the first address space unit with pin data, and continuation is carried out in proper order;
16) note power down " pin changes the back state ", " time when pin changes " of this pin at storer first address space (changing), change step 13) according to this pin current state change frequency and which pin;
" pin changes the back state ", " time when pin changes " and " tables of data " such as " pin state variation number of times " of 17) first address space being stored are saved in storer second address space " tables of data " storage unit, send out power down and learn to finish information;
18) with circuit board to be detected set by step 1) described each test point inserts each pin of microprocessor (P10-P17), and set by step 2) described signaling point inserts microprocessor INT0 as reference signal (NORM);
19) clear 0 to " the pin state variation number of times " storage space that powers on, power on " pin changes the back state ", " time when pin changes " each byte of storage unit are put 0FFH;
20) when the reference signal rising edge then, open timer, get pin (P1) data, and be kept at storer first address space, and more whether corresponding with storer second address space " pin state when powering on " data are equal, if unequal, then send error message, otherwise order is carried out;
21) detect whether exceed the 5 seconds given test wait time that powers on,, then send error message, otherwise continuation is carried out in proper order if overtime;
22) get pin P1 data, judge whether to equate, carry out if equate then to return previous step, otherwise continuation is carried out in proper order with first address space storage data;
23) find out the state variation pin according to the position of not waiting, and this pin correspondence " pin state variation number of times " internal storage location that powers on added 1, whether the disconnected pin state variation number of times of betraing exceeds 2 times, if exceed 2 times, then provide error message, otherwise, pin data is transferred to the first address space unit, order is carried out;
24) note powering on " pin changes the back state ", " time when pin changes " of this pin at storer first address space (changing) according to this pin current state change frequency and which pin;
25) " pin changes the back state ", " time during the pin variation " and " pin state variation number of times " with the storage of storer first address space contrasted with " pin changes the back state " that be saved in storer second address space, " time when pin changes " and " pin state variation number of times ", if it is unequal, then change step 17), otherwise, send out information qualified, order is carried out next step;
26) clear 0 to power down " pin state variation number of times " storage space, power down " pin changes the back state ", " time when pin changes " each byte of storage unit are put 0FFH;
27) when the reference signal negative edge then, open timer, get the variable condition data of the test point current potential of pin (P1) detection, be saved in storer first address space, and whether " pin state during power down " memory cell data that relatively storer first address space is corresponding with storer second address space equates, if unequal, then send error message, otherwise continuation is carried out in proper order;
28) detect whether exceed 5 seconds given power down test wait time,, then change step 14, otherwise continuation is carried out in proper order if overtime;
29) get pin (P1) data, judge whether to equate, carry out if equate then to return previous step, otherwise continuation is carried out in proper order with first address space storage data;
30) find out the state variation pin according to the position of not waiting, and corresponding power down " the pin state variation number of times " internal storage location of this pin added 1, whether the disconnected pin state variation number of times of betraing exceeds 2 times, if exceed 2 times, then provide error message, otherwise, pin data is transferred to the first address space unit, order is carried out;
31) note power down " pin changes the back state ", " time when pin changes " of this pin at storer first address space (changing) according to this pin current state change frequency and which pin;
" pin changes the back state ", " time when pin changes " and " pin state variation number of times " that " pin changes the back state " of 32) first address space being stored, " time when pin changes " and " pin state variation number of times " and storer second address space are stored contrast, if it is unequal, then change step 24), otherwise, send out information qualified.
" tables of data " storage organization when drawn in Fig. 5 pin P1.0-1.7 state variation sequential chart of when powering on Fig. 3 (a) and (b), (c), following electricity is identical with it.
In practice; in order to carry out power down protection; storer first address space adopts internal storage; it is external storage that storer second address space adopts; can be on external storage with the detection data-storing of each test point on the qualified circuit board; the preferred eeprom memory of external storage, with the detection data storage of each test point on the circuit board to be detected on internal storage.
The device of testing circuit plate as shown in Figure 4, comprises microprocessor, external storage IC2, pilot lamp (D1, D2) and mode key SW1.IC1 is a microprocessor, and the vibration external circuits provides clock for microprocessor, and the reset circuit of microprocessor resets for the powered on moment low level, and then 5V charges to C3 by R2, and the RESET pin of IC1 becomes high level.The eeprom memory that IC2 does not lose for the power down data of using the read-write of I2C bus protocol, the SCL pin is a clock bus, the SDA pin is a data bus, receive microprocessor P0.1 pin and P0.0 pin respectively, finish read-write by these two pin, be used to preserve tables of data (seeing accompanying drawing 3) here storer.Display circuit part D1 is the pattern pilot lamp, and D2 constitutes two emitter followers and drives D1, D2 pilot lamp respectively for busy pilot lamp, Q3, Q4.Measured signal importation IN0～IN7 is monitored logic level input pin, and NORM is the reference signal input pin, and the sequential of IN0～IN7 is with respect to the NORM reference signal.Mode key SW1 13 pin of IC1 when pressing closure obtain low level, unclamp then to obtain high level.The Q1 of phonation circuit, Q2, Q3 complex pipe constitute emitter follower, drive loudspeaker SP1 and send prompting sound.
The course of work: each test point of circuit-under-test plate is input to any pin of P1.0～P1.7 (test point can not above 8) of microprocessor IC1, is selecting one to occur high level immediately when circuit board powers on, occur low level signaling point meets microprocessor IC1 as the reference signal access point of microprocessor input pin IN0 when cutting off the power supply immediately on the circuit board.Enter mode of learning by mode key, qualified circuit board powered on note the logic state that is input to microprocessor P1.0～P1.7 pin at that time at storer second address space in a flash, shown in Fig. 3 (a), busy simultaneously pilot lamp bright (deepening automatically after waiting for for 5 learning times in second), next time when storer second address space is noted the state after each pin level of P1.0～P1.7 changes and changed (changing once record once) in 5 seconds is shown in Fig. 3 (b)., sends certain pin level change frequency bomp sound (so this device restriction is used for circuit-under-test plate maximum occasions of 2 times that all are no more than that power on that 5 seconds build-in test level points no longer change and each pin change frequency powers on, cuts off the power supply) if surpassing 2 times.If do not send bomp sound after 5 seconds busy pilot lamp go out and send the study that the powers on prompting sound that finishes.This moment can be to tested qualified circuit board outage, and power down is noted the power down logic state that is input to microprocessor P1.0～P1.7 pin at that time at storer second address space in a flash, and busy simultaneously pilot lamp is bright.Next the time when storer second address space is noted the state after each pin level of P1.0～P1.7 changes and changed in 5 seconds,, at this moment should relearn if certain pin level change frequency surpasses 2 times then sends bomp sound.If do not send bomp sound after 5 seconds busy pilot lamp go out and send the power down study prompting sound that finishes, next return test pattern automatically.Similar process under the test pattern, just data are recorded in internal memory, and the data that are recorded in storer second address space during again with study compare.Power on and note the logic state that powers on that is input to microprocessor P1.0～P1.7 pin at that time at internal memory in a flash, the data that are recorded in storer second address space during with study compare, if do not wait then send bomp sound, equal then time when internal memory is noted the state after each pin level of P1.0～P1.7 changes and changed (sending bomp sound) next if certain pin level changes more than 2 times, the corresponding data table of record more once when having the pin variation once just to learn with storer second address space, send the test passes prompting sound that powers in case data are identical, if later data were also inequality then send bomp sound in 5 seconds.If hear that the test passes prompting sound that powers on just can be to the outage of circuit-under-test plate, the state and the change procedure thereof of each pin are identical with last electrical testing during the test outage.
Must be pointed out that the indefiniteness that the foregoing description is only made the present invention illustrates.But person of skill in the art will appreciate that, do not departing under aim of the present invention and the scope, can make various modifications, replacement and change the present invention.As: the foregoing description is set at (this is the most frequently used situation) 2 times with pin state variation number of times, and the test wait time set is 5 seconds.When qualified circuit board and above-mentioned setting are inconsistent, can set flexibly as required.These modifications, replacement and change still belong to protection scope of the present invention.
Claims (10)
1, a kind of method of testing circuit plate comprises the steps:
1) determines test point;
2) the reference signal access point of low level signaling point as microprocessor appears when selecting one to occur high level, outage immediately on the circuit board when circuit board powers on immediately;
3) described each test point of step 1) on the qualified circuit board is inserted each pin of microprocessor (P1) and with step 2) described signaling point inserts microprocessor as reference signal, following detection data by each test point on the qualified circuit board of microprocessor records: state, time and state variation number of times when changing after the variation of current potential each time of each test point within the test wait time that powers on, state, time and state variation number of times when changing after the variation of current potential each time of each test point within the power down test wait time;
4) described each test point of step 1) on the circuit board to be detected is inserted each pin of microprocessor (P1) and with step 2) described signaling point inserts microprocessor as reference signal, following detection data by described each test point of step 1) on the microprocessor records circuit board to be detected: step 3) state after the variation of current potential each time of each test point within the described test wait time that powers on, time during variation and state variation number of times, step 3) state after the variation of current potential each time of each test point within the described power down test wait time, time during variation and state variation number of times;
5) in the process that step 4) is carried out, the circuit board detecting data to be detected with microprocessor records compare with the corresponding detection of the qualified circuit board data of step 3) record simultaneously;
6) if the comparative result of step 5) is unequal, then provide error message; Otherwise, continue execution in step 4), treat that step 5) is finished, provide qualified information.
2, according to the method for the described testing circuit plate of claim 1, it is characterized in that:
The detection data procedures that described step 3) writes down each test point on the qualified circuit board comprises:
1) clear 0 to " the pin state variation number of times " storage space that powers on, power on " pin changes the back state ", " time when pin changes " each byte of storage unit are put 0FFH;
2) when the reference signal rising edge then, open timer, get the variable condition data of the test point current potential that pin (P1) detects, and be kept at storer first address space, also be saved in the storer second address space correspondence " pin state when powering on " storage unit;
3) detect whether exceed given powering on the learning test stand-by period,, then change step 7, otherwise continuation is carried out in proper order if overtime;
4) get pin (P1) data, judge whether to equate, carry out if equate then to return previous step, otherwise continuation is carried out in proper order with first address space storage data;
5) find out the state variation pin according to what does not wait, and this pin correspondence " pin state variation number of times " internal storage location that powers on is added 1, and pin data is transferred to the first address space unit;
6) and at storer first address space (changing) note powering on " pin changes the back state ", " time when pin changes " of this pin, change step 3) according to this pin current state change frequency and which pin;
" pin changes the back state ", " time when pin changes " and " tables of data " such as " pin state variation number of times " of 7) first address space being stored are saved in storer second address space " tables of data " storage unit, and sending out powers on learns to finish information;
8) clear 0 to power down " pin state variation number of times " storage space, power down " pin changes the back state ", " time when pin changes " each byte of storage unit are put 0FFH;
9) when the reference signal negative edge then, open timer, get the variable condition data of the test point current potential that pin (P1) detects, and be saved in " pin state during power down " storage unit of storer first address space and the storer second address space correspondence respectively;
10) detect whether exceed the given power down learning test stand-by period,, then change step 14, otherwise continuation is carried out in proper order if overtime;
11) get pin (P1) data, judge whether to equate, carry out if equate then to return previous step, otherwise continuation is carried out in proper order with first address space storage data;
12) find out the state variation pin according to the position of not waiting, and corresponding power down " the pin state variation number of times " internal storage location of this pin is added 1, and pin data is transferred to the first address space unit;
13) note power down " pin changes the back state ", " time when pin changes " of this pin at storer first address space (changing), change step 10) according to this pin current state change frequency and which pin;
" pin changes the back state ", " time when pin changes " and " tables of data " such as " pin state variation number of times " of 14) first address space being stored are saved in storer second address space " tables of data " storage unit, send out power down and learn to finish information;
The detection data procedures that step 4) writes down each test point on the circuit board to be detected in the described claim 1 comprises:
15) clear 0 to " the pin state variation number of times " storage space that powers on, power on " pin changes the back state ", " time when pin changes " each byte of storage unit are put 0FFH;
16) when the reference signal rising edge then, open timer, get pin (P1) data, and be kept at storer first address space, and more whether corresponding with storer second address space " pin state when powering on " data are equal, if unequal, then send error message, otherwise order is carried out;
17) detect whether exceed given powering on the test wait time,, then send error message, otherwise continuation is carried out in proper order if overtime;
18) get pin (P1) data, judge whether to equate, carry out if equate then to return previous step, otherwise continuation is carried out in proper order with first address space storage data;
19) find out the state variation pin according to what does not wait, and this pin correspondence " pin state variation number of times " internal storage location that powers on is added 1, and pin data is transferred to the first address space unit
20) note powering on " pin changes the back state ", " time when pin changes " of this pin at storer first address space (changing) according to this pin current state change frequency and which pin;
21) " pin changes the back state ", " time during the pin variation " and " pin state variation number of times " with the storage of storer first address space contrasted with " pin changes the back state " that be saved in storer second address space, " time when pin changes " and " pin state variation number of times ", if it is unequal, then change step 17), otherwise, send out information qualified, order is carried out next step;
22) clear 0 to power down " pin state variation number of times " storage space, power down " pin changes the back state ", " time when pin changes " each byte of storage unit are put 0FFH;
23) when the reference signal negative edge then, open timer, get the variable condition data of the test point current potential of pin (P1) detection, be saved in storer first address space, and whether " pin state during power down " memory cell data that relatively storer first address space is corresponding with storer second address space equates, if unequal, then send error message, otherwise continuation is carried out in proper order;
24) detect whether exceed the given power down test wait time,, then change step 14, otherwise continuation is carried out in proper order if overtime;
25) get pin (P1) data, judge whether to equate, carry out if equate then to return previous step, otherwise continuation is carried out in proper order with first address space storage data;
26) find out the state variation pin according to the position of not waiting, and corresponding power down " the pin state variation number of times " internal storage location of this pin is added 1, and pin data is transferred to the first address space unit;
27) note power down " pin changes the back state ", " time when pin changes " of this pin at storer first address space (changing) according to this pin current state change frequency and which pin;
" pin changes the back state ", " time when pin changes " and " pin state variation number of times " that " pin changes the back state " of 28) first address space being stored, " time when pin changes " and " pin state variation number of times " and storer second address space are stored contrast, if it is unequal, then change step 24), otherwise, send out information qualified.
3, according to the method for the described testing circuit plate of claim 1, it is characterized in that: with the detection data-storing of each test point on the qualified circuit board on external storage, with the detection data storage of each test point on the circuit board to be detected on internal storage.
4, according to the method for the described testing circuit plate of claim 2, it is characterized in that: described storer first address space is an internal storage, and described storer second address space is an external storage.
5, according to the method for claim 2 or 4 described testing circuit plates, it is characterized in that: pin state variation number of times higher limit is set, when pin state variation number of times surpasses the higher limit of setting, sends error message.
6, according to the method for the described testing circuit plate of claim 5, it is characterized in that: it is 2 times that pin state variation number of times higher limit is set.
7, according to the method for any described testing circuit plate of claim 1-4, it is characterized in that: it is 5 seconds that the power down test wait time is set.
8, according to the method for claim 3 or 4 described testing circuit plates, it is characterized in that: described storer is an eeprom memory.
9, a kind of device of testing circuit plate, it is characterized in that: comprise microprocessor, storer, loudspeaker and mode key, high level appears when the reference signal of microprocessor powers on from circuit board immediately, low level signaling point appears during outage immediately, insert the input port of microprocessor from the detection signal of each test point on the circuit board, state after the variation of current potential each time of each test point within the test wait time that powers on that microprocessor is used for detecting from qualified circuit board, time during variation and state variation number of times and state after the variation of current potential each time of each test point within the power down test wait time, time during variation and state variation number of times deposit storer in; And will be within the described test wait time that powers on that circuit board to be detected detects after the variation of current potential each time of each test point state, the time when changing and state variation number of times and within the described power down test wait time after the variation of current potential each time of each test point state, the time when changing and state variation number of times compare with the data that deposit storer in, comparative result is exported to loudspeaker, mode key connects microprocessor and is used to control its duty.
10, according to the device of the described testing circuit plate of claim 9, it is characterized in that: also be connected to relay indicating light on the described microprocessor.
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| CNB2003101109215A CN100383542C (en) | 2003-11-07 | 2003-11-07 | Method and device for inspecting circuit board |
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| CNB2003101109215A CN100383542C (en) | 2003-11-07 | 2003-11-07 | Method and device for inspecting circuit board |
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| CN100383542C CN100383542C (en) | 2008-04-23 |
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| CN101937222A (en) * | 2010-08-17 | 2011-01-05 | 北京交通大学 | Board level testing system |
| CN102486629A (en) * | 2010-12-01 | 2012-06-06 | 北京广利核系统工程有限公司 | Method for testing periodic running time of hardware board card |
| CN103529824A (en) * | 2013-10-21 | 2014-01-22 | 广东威创视讯科技股份有限公司 | Stability test method and system |
| CN108089073A (en) * | 2016-11-22 | 2018-05-29 | 技嘉科技股份有限公司 | Measuring fixture and the method for switching test system state |
| CN109144528A (en) * | 2018-07-27 | 2019-01-04 | 深圳市浦洛电子科技有限公司 | A kind of method and system of automatic detection pin identification SPI Flash concrete model |
| CN113945822A (en) * | 2021-09-14 | 2022-01-18 | 深圳矽递科技股份有限公司 | Pin testing device and pin testing method |
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| SE515553C2 (en) * | 1996-06-28 | 2001-08-27 | Ericsson Telefon Ab L M | PCB Test |
| CN2284963Y (en) * | 1996-11-12 | 1998-06-24 | 满都拉 | Portable multi-functional and expandable digital circuit tester |
| CN2385344Y (en) * | 1998-11-16 | 2000-06-28 | 力捷电脑股份有限公司 | Device for testing circuit board function |
-
2003
- 2003-11-07 CN CNB2003101109215A patent/CN100383542C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937222A (en) * | 2010-08-17 | 2011-01-05 | 北京交通大学 | Board level testing system |
| CN102486629A (en) * | 2010-12-01 | 2012-06-06 | 北京广利核系统工程有限公司 | Method for testing periodic running time of hardware board card |
| CN103529824A (en) * | 2013-10-21 | 2014-01-22 | 广东威创视讯科技股份有限公司 | Stability test method and system |
| CN103529824B (en) * | 2013-10-21 | 2016-04-27 | 广东威创视讯科技股份有限公司 | Stability test method and system |
| CN108089073A (en) * | 2016-11-22 | 2018-05-29 | 技嘉科技股份有限公司 | Measuring fixture and the method for switching test system state |
| CN108089073B (en) * | 2016-11-22 | 2020-03-10 | 技嘉科技股份有限公司 | Measuring tool and method for switching state of device to be measured |
| CN109144528A (en) * | 2018-07-27 | 2019-01-04 | 深圳市浦洛电子科技有限公司 | A kind of method and system of automatic detection pin identification SPI Flash concrete model |
| CN109144528B (en) * | 2018-07-27 | 2021-06-08 | 深圳市浦洛电子科技有限公司 | Method and system for automatically detecting pins and identifying specific type of SPI Flash |
| CN113945822A (en) * | 2021-09-14 | 2022-01-18 | 深圳矽递科技股份有限公司 | Pin testing device and pin testing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100383542C (en) | 2008-04-23 |
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