CN1610139A - Micro refrigerator and producing method thereof - Google Patents
Micro refrigerator and producing method thereof Download PDFInfo
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- CN1610139A CN1610139A CN 200410065714 CN200410065714A CN1610139A CN 1610139 A CN1610139 A CN 1610139A CN 200410065714 CN200410065714 CN 200410065714 CN 200410065714 A CN200410065714 A CN 200410065714A CN 1610139 A CN1610139 A CN 1610139A
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Abstract
The micro refrigerator is used in raising the temperature control of laser device and computer CPU, improving the work efficiency of chip and prolonging their service life. The refrigerator is one multilayer structure including the high temperature area, metal layer, P-type semiconductor, N-type semiconductor, upper metal layer and low temperature area successively from bottom to top. It is prepared with superlattice material Si and Ge and the preparing process includes combined chemical plating process and oxide isolating process to form several stages of micro refrigerator, forming plasma reinforced chemical vapor deposited SiO2 film as protecting layer and chemical copper plating to form metal film in the bonding surfaces between P-type and N-type semiconductors.
Description
Technical field
The present invention is a kind of temperature control that is used for improving to Laser Devices, computer CPU, improves the heat radiation of chip internal, thereby improves the operating efficiency of device chip, and the technology that increases the service life belongs to advanced and makes and technical field of automation,
Background technology
At present, thermoelectric material can constitute solid-state refrigerator and electric organ.Take away unnecessary heat and solid-state thermoelectric generator and refrigerator are Peltier (Peltier) effects of utilizing electronics, what it mainly faced is the thermoelectric conversion efficiency problem.The performance index general stores material matter coefficient ZT of thermoelectric cooling device is described, and its mathematic(al) representation is: ZT=S
2σ T/k, wherein T is an absolute temperature, and S is Seebeck (Seebeck) coefficient of material, and σ is a conductivity, and k is a conductive coefficient.
The thermoelectric material of practice mostly is figure's material on the current industrial, and for conventional figure's thermoelectric device, the minimum thickness of hot cell is generally in several millimeter.At present, figure's thermoelectric coolor generally adopts Bi
2Te
3Or be the thermoelectric material of base with it.But figure Bi
2Te
3Or the processing technology of its alloy and IC (IntegratedCircuit) technology are incompatible.Select and the IC process compatible, the microstructure thermoelectric material that has higher thermoelectric qualitative index simultaneously again is the key of design high-performance thermoelectric device.
For micro-refrigerator spare, the thin thickness of hot cell reach 1～10 μ m, thick about 100 μ m.Because microdevice adopts thin-film technique, the contact heat resistance at interface, contact resistance become the key factor that influences device performance, and the selection of material is also influential to device performance simultaneously.The main challenge that this class micro-refrigerator faces be thermoelectric material selection with and the manufacturing process problem.In order to improve the workability ability of microdevice, some miniature processing technologys are proposed in succession, there are electrochemical deposition, plating and sputter to realize the metal film forming.Electrochemical deposition form P type and N type thermocouple to the time, thermocouple can be controlled at tens micrometer ranges neatly to the height of leg, this technology shortcoming is to guarantee the consistent uniformity of film quality and the purity of material, has restricted the operating efficiency of device from face.Electroplating technology with film deposits V family and VI compounds of group film, and it is right to form thermocouple, and this technology is that with the difference of electrochemical deposition process the hot cell of P type and N type is deposited on the different substrates, thereby causes follow-up bonding technology very difficult.And adopt the sputter filming technology on the SOI substrate, to form the thermocouple unit of the BiTe alloy of P type, N type, and the stability of device is better, as refrigerator, can form the temperature difference about 10K, and size of devices can be controlled at 100 μ m
2∽ 1mm
2But the thickness of the strict control of this arts demand thermoelectric unit is in the process of each substrate bonding, if the thickness difference of unit will cause device isolation, formation is opened circuit, secondly, also require the accurate location of hot cell and metal electrode position, to reduce contact resistance.On the other hand, because used material is V family and VI compounds of group film, the thermoelectric qualitative index ZT of system can not break through the limit of figure's material, thereby has limited the operating efficiency of device.
Summary of the invention
Technology contents: for the material that overcomes existing thermoelectric cooling module and the deficiency of processing technology, the invention provides a kind of multistage micro-refrigerator and preparation method thereof, this refrigerator has improved the reliability of system works, improves the operating efficiency of device, for manufacturing process brings great convenience.
Technical scheme: this refrigerator is a sandwich construction, orlop is a high-temperature area, on high-temperature area, be respectively equipped with two metal levels, a metal level is provided with P type semiconductor therein, on another piece metal level, be provided with N type semiconductor, be provided with at P type semiconductor with above the N type semiconductor integral body on metal level, be low-temperature region on last metal level.
The concrete structure of this refrigerator is divided into upper and lower two parts; The orlop of lower part is the Si substrate of P type semiconductor, being provided with resilient coating in the Si of P type semiconductor substrate is the layer that undopes of P type semiconductor, separately first heavily doped layer that is provided with P type semiconductor on the layer that undopes of P type semiconductor, on first heavily doped layer of P type semiconductor, be provided with the superlattice layer of P type semiconductor, on the superlattice layer of P type semiconductor, be provided with second heavily doped layer of P type semiconductor, on second heavily doped layer of P type semiconductor, be provided with the lightly-doped layer of P type semiconductor; The superiors of upper part are the Si substrate of N type semiconductor, have the layer that undopes of N type semiconductor in the Si of N type semiconductor substrate, separately first heavily doped layer that is provided with N type semiconductor under the layer that undopes of N type semiconductor, have the superlattice layer of N type semiconductor at first heavily doped layer of N type semiconductor, have second heavily doped layer of N type semiconductor at the superlattice layer of N type semiconductor, have the lightly-doped layer of N type semiconductor at second heavily doped layer of N type semiconductor; This upper and lower two parts intersection matches, and is filled with the metallic film that chemical plating forms in the anastomosis.The element thickness of this refrigerator is in 1～10 mu m range.
The present invention adopts the silicon and germanium super crystal lattice material in III-V family semi-conducting material or the IV family semi-conducting material, and combining with oxide isolation with chemical plating process with fruit in season forms multistage micro-refrigerator.With plasma reinforced chemical vapour deposition (PECVD) silica membrane protective layer; silicon dioxide can isolate P-N to electric current, realize the single type of flow of electric current, thereby avoid the short circuit problem of thermoelectric unit in intergrade; improve the reliability of system works, realized array refrigeration.With chemical plating process thermoelectric unit is realized the metal film forming, can realize the consistent uniformity of film metal and the purity of material, thereby reduce the contact distributed resistance, improve the operating efficiency of device, chemical plating process system film does not need the thickness of strict control thermoelectric unit simultaneously, promptly the thickness of thermoelectric unit can be different in the process of bonding, also need not require the accurate location of hot cell and metal electrode position in order to reduce contact resistance.This brings great convenience for manufacturing process.
The concrete preparation method of the present invention is:
The first step: pre-treatment is carried out in substrate:
Second step: with MBE (molecular beam epitaxy) or MOCVD (metal oxide chemical vapor deposition) method branch
The superlattice film of growing P-type and N type on two silicon base does not have on superlattice film
Cover layer has resilient coating below superlattice film, the bottom is a silicon base;
The semiconductor structure table
| Remarks | |
| Cover layer | Lightly-doped layer |
| Heavily doped layer (identical) with the superlattice layer doping content | |
| Superlattice layer | |
| Resilient coating | Heavily doped layer (identical) with the superlattice layer doping content |
| Layer (playing insulating effect) undopes | |
| Silicon base | Low-resistance |
The 3rd step a: etching: on grow good P type, N type semiconductor, it is carried out etching, etching respectively
To first heavily doped layer of P type, N type semiconductor (be about to lightly-doped layer, second heavily doped layer and
Superlattice layer etches away);
Secondarily etched: as to make the photoresist protective layer, use reactive ion etching, etch into P type, N type semiconductor
Resilient coating (be about to first heavily doped layer etch away), remove residual photoresist then;
The 4th step: plasma reinforced chemical vapour deposition (PECVD) silica membrane is as protective layer;
The 5th step: fall unnecessary silicon dioxide with plasma bombardment, only stay the silicon dioxide on the superlattice sidewall:
The 6th step: make photoresist layer, soon P type, the bottom surface of N type semiconductor, side faces at both ends are done the photoresist protection
Layer;
The 7th step: with P type and N type semiconductor bonding;
The 8th step: adopt chemical plating process to plate a thin film metal layer, make bonding face contact between P type and the N type semiconductor
Closely, coating film uniformity;
The 9th step: stripping photoresist.
Beneficial effect: the microstructure material provides space widely for improving factor of merit ZT, can realize a cooling, improve the cooling effectiveness of unit are, and adopt the thermoelectric device of the silicon and germanium super crystal lattice material manufacturing in III-V family or the IV family metal material and the processing technology compatibility of microprocessor.Make protective layer with silicon dioxide, can isolate P-N to electric current, realize the single type of flow of electric current, thereby avoid the short circuit problem of thermoelectric unit in intergrade, improved the reliability of system works, realize array refrigeration.Adopt the formed metal film high conformity of chemical plating process, the all-in resistance of not only connecting obviously is better than other metal film-forming process, distributed resistance also is better than other technology, can solve the difficult problem of contact resistance, simultaneously, can utilize the alternative of chemical plating process film forming, realize the selective film forming of metal, help improving the job stability of multistage thermoelectric unit.
Multi-stage solid stage thermoelectric material refrigerator of the present invention is to utilize the Po Er of electronics to paste (Peltier) effect to take away unnecessary heat, improves freezing capacity, thickness that need not strict control thermoelectric unit, and promptly the thickness of thermoelectric unit can be different in bonding process.Adopt chemical plating process, make metal and semi-conductive contact problems obtain good solution, improved the consistency of metallic film covering and reduced contact resistance.
Description of drawings
Fig. 1: refrigerator schematic diagram, Peltier (Peltier) effect schematic diagram.Among the figure: 1. high-temperature area, 2. metal level, the 3.P N-type semiconductor N is 4. gone up metal level, 5. low-temperature region, 6.N N-type semiconductor N.
Fig. 2-1～Fig. 2-11 is in the preparation process of the present invention, the schematic diagram of each step,
Fig. 2-1: silicon base growth superlattice structure schematic diagram,
Fig. 2-2: through the intention of the structural diagrams after etching,
Fig. 2-3: through the intention of the structural diagrams after secondarily etched,
Fig. 2-4: plasma reinforced chemical vapour deposition (PECVD) silicon dioxide layer of protection schematic diagram,
Fig. 2-5, Fig. 2-6: the silica membrane schematic diagram that plasma bombardment is unnecessary,
Fig. 2-7, Fig. 2-8: make the photoresist layer schematic diagram,
Fig. 2-9:P, N type semiconductor bonding schematic diagram,
Fig. 2-10: multistage thermoelectric unit is carried out the chemical plating process schematic diagram,
Fig. 2-11: the stripping photoresist schematic diagram,
Among the figure: the Si substrate of 7.P N-type semiconductor N, 8.P the layer that undopes of N-type semiconductor N, 9.P first heavily doped layer of N-type semiconductor N, 10.P the superlattice layer of N-type semiconductor N, 11.P second heavily doped layer of N-type semiconductor N, 12.P the lightly-doped layer of N-type semiconductor N, 13.P the silica membrane on the N-type semiconductor N, 14.N the Si substrate of N-type semiconductor N, 15.N the layer that undopes of N-type semiconductor N, first heavily doped layer of 16.N N-type semiconductor N, the superlattice layer of 17.N N-type semiconductor N, 18.N the silica membrane on the N-type semiconductor N, 19.N second heavily doped layer of N-type semiconductor N, the lightly-doped layer of 20.N N-type semiconductor N, the photoresist layer on the 21.N N-type semiconductor N, 22.P the photoresist layer on the N-type semiconductor N, the metallic film that 23. chemical platings form.
Embodiment
The present invention adopts the chemical plating metal film-forming process to combine with oxide isolation and forms multistage micro-refrigerator.This refrigerator is a sandwich construction, orlop is a high-temperature area 1, on high-temperature area 1, be respectively equipped with two metal levels 2, a metal level 2 is provided with P type semiconductor 3 therein, on another piece metal level 2, be provided with N type semiconductor 6, be provided with at P type semiconductor 3 with above the N type semiconductor 6 integral body on metal level 4, on last metal level 4, be provided with a low-temperature region 5.
The concrete structure of this refrigerator is divided into upper and lower two parts; The orlop of lower part is the Si substrate 7 of P type semiconductor, being provided with resilient coating in the Si of P type semiconductor substrate 7 is the layer 8 that undopes of P type semiconductor, separately first heavily doped layer 9 that is provided with P type semiconductor on the layer 8 that undopes of P type semiconductor, on first heavily doped layer 9 of P type semiconductor, be provided with the superlattice layer 10 of P type semiconductor, on the superlattice layer 10 of P type semiconductor, be provided with second heavily doped layer 11 of P type semiconductor, on second heavily doped layer 11 of P type semiconductor, be provided with the lightly-doped layer 12 of P type semiconductor; The superiors of upper part are the Si substrate 14 of N type semiconductor, have the layer 15 that undopes of N type semiconductor in the Si of N type semiconductor substrate 14,15 times first heavily doped layer 16 that is provided with N type semiconductor separately of layer that undope at N type semiconductor, have the superlattice layer 17 of N type semiconductor at first heavily doped layer 16 of N type semiconductor, have second heavily doped layer 19 of N type semiconductor at the superlattice layer 17 of N type semiconductor, have the lightly-doped layer 20 of N type semiconductor at second heavily doped layer 19 of N type semiconductor; This upper and lower two parts intersection matches, and is filled with the metallic film 23 that chemical plating forms in the anastomosis.The element thickness of this refrigerator is in 1～10 mu m range.
Adopt the silicon and germanium super crystal lattice material in III-V family's semi-conducting material or the IV family semi-conducting material, combining with silica membrane technology with chemical-copper-plating process forms multistage micro-refrigerator.Adopt the plasma reinforced chemical vapour deposition silica membrane to make protective layer, with chemical-copper-plating process to realization metal film forming between the bonding face (first heavily doped layer, the lightly-doped layer of the lightly-doped layer of P type semiconductor, first heavily doped layer and N type semiconductor) of P, N type semiconductor.
Concrete preparation method is:
The first step: the silicon base 7 of P type semiconductor, the silicon base 14 of N type semiconductor are carried out preliminary treatment: earlier with hydrofluoric acid (HF) pickling, and then use the deionized water ultrasonic waves for cleaning,
Second step: with on the silicon base 7 of P type semiconductor, the grow superlattice layer 10 (Si of .P N-type semiconductor N of MBE (molecular beam epitaxy) method
0.7Ge
0.3/ Si), this superlattice layer film thickness has 3000 nanometers, in this superlattice film, at growth Si
0.7Ge
0.3In the time of layer it is mixed, doping content is 6.47 * 10
19Cm
-3, and when growth Si layer, it is not mixed, in the one-period of superlattice film, Si
0.7Ge
0.3Thickness be 5 nanometers, the thickness of Si is 10 nanometers.
Above superlattice film one deck Si
0.9Ge
0.1Film, i.e. second heavily doped layer 11 of P type semiconductor, the thickness of this layer film is 250 nanometers, its doping content is 6.47 * 10
19Cm
-3, also have a Si above the layer at this
0.9Ge
0.1Film, i.e. the lightly-doped layer 12 of P type semiconductor, the thickness of this layer film is 250 nanometers, its doping content is more than or equal to 1 * 10
20Cm
-3Below superlattice film a Si
0.9Ge
0.1Layer, i.e. first heavily doped layer 9 of P type semiconductor, the thickness of this layer film is 1000 nanometers, doping content is 6.47 * 10
19Cm
-3, the following Si in addition of this layer
0.9Ge
0.1Layer, i.e. the resilient coating 8 of P type semiconductor, this layer thickness has 1000 nanometers.In all mixed, the doped chemical that we select was a sodium, promptly was that the P type mixes.
Process N type semiconductor with the MBE method in another your substrate equally, its doped chemical is a neodymium, and doping content sees Table, and its size is mixed identical with the P type.
The superlattice structure of P type describes table in detail
| Material | Describe in detail | Remarks |
| SiG layer (12) | Si 0.9Ge 0.1: doping content 〉=1 * 10 20cm -3 | Thickness: 300nm |
| SiG layer (11) | Si 0.9Ge 0.1: doping content 6.47 * 10 19cm -3, thickness 10nm | Thickness 250nm |
| P type superlattice layer (10) | Si 0.7Ge 0.3: doping content 6.47 * 10 19cm -3, thickness 5nm | 200 cycles, gross thickness 3000nm |
| Si: undope thickness 10nm | ||
| SiGe layer (9) | Si 0.9Ge 0.1: doping content 6.47 * 10 19cm -3 | Thickness 1000nm |
| SiGe layer (8) | Si 0.9Ge 0.1: undope | Thickness 1000nm |
| Si substrate (7) | Low-resistance | Low-resistance |
The superlattice structure of N type describes table in detail
| Material | Describe in detail | Remarks |
| SiG layer (20) | Si 0.9Ge 0.1: doping content 〉=1 * 10 20cm -3 | Thickness: 300nm |
| SiG layer (19) | Si 0.9Ge 0.1: doping content 3.42 * 10 19cm -3, thickness 10nm | Thickness 250nm |
| N type superlattice layer (17) | Si 0.7Ge 0.3: doping content 3.42 * 10 19cm -3, thickness 5nm | 200 cycles, gross thickness 3000nm |
| Si: thickness 10nm undopes | ||
| SiG layer (16) | Si 0.9Ge 0.1: doping content 3.42 * 10 19cm -3 | Thickness 1000nm |
| SiG layer (15) | Si 0.9Ge 0.1: undope | Thickness 1000nm |
| Si substrate (14) | Low-resistance | Low-resistance |
The 3rd step: an etching, respectively grow good P type, N type semiconductor are carried out etching by definite shape, etch into the Si of bottom
0.9Ge
0.1Heavily doped layer, promptly first heavily doped layer 16 of first heavily doped layer 9 of P type semiconductor, N type semiconductor is about to top Si
0.9Ge
0.1Thin layer, promptly the lightly-doped layer 20 of second heavily doped layer 19 of the lightly-doped layer 12 of second heavily doped layer 11 of P type semiconductor, P type semiconductor, N type semiconductor, N type semiconductor with and following superlattice film layer be that the superlattice layer 10 of P type semiconductor, the superlattice layer 17 of N type semiconductor etch away.Whole etch thicknesses has 3500 nanometers.
Secondarily etched, make photoresist protective layer (with negative glue), thickness is not less than superlattice thickness, 120 ℃ of following post bakes 5 minutes.Reactive ion etching ends at the Si under the superlattice film
0.9Ge
0.1The non-impurity-doped layer is the non-impurity-doped layer 8 of P type semiconductor and the non-impurity-doped layer 15 of N type semiconductor, removes residual photoresist then.
The 4th step: plasma reinforced chemical vapour deposition (PECVD) silicon dioxide layer of protection, i.e. silica membrane 18 on silica membrane on the P type semiconductor 13, the N type semiconductor.Deposit thickness 3000 dusts.
The 5th step: plasma bombardment falls unnecessary silicon dioxide, only stays the silicon dioxide on the superlattice sidewall.
The 6th step: make the photoresist protective layer, i.e. photoresist layer 22 on photoresist layer on the N type semiconductor 21, the P type semiconductor (with negative glue).
The 7th step: with P type and N type semiconductor anode linkage, P type and N type semiconductor are bonded together under electrostatic field.
The 8th step: adopt between the bonding face of chemical-copper-plating process (first heavily doped layer 9 of the lightly-doped layer 12 of P type semiconductor, P type semiconductor respectively and the bonding face of 20 of the lightly-doped layers of first heavily doped layer 16 of N type semiconductor, N type semiconductor) to realize the metal film forming to P, N type semiconductor.
1, preliminary treatment: 1.) in water, use ultrasonic waves for cleaning 5 minutes; 2.) under the room temperature condition, in alcoholic solution, it is used ultrasonic waves for cleaning; 3.) putting it into the deionized water for ultrasonic ripple cleans; 4.) with 4% NaOH solution etching; 5.) put into the water ultrasonic waves for cleaning; 6.) invade in the photonasty solution ten minutes; 7.) washed with de-ionized water; 8.) invade in the catalytic activity solution five minutes; 9.) washed with de-ionized water.
2, electroless copper: in the plating bath: HCHO is a reducing agent, KNaC
4H
4O
54H
2O and ethylenediamine tetra-acetic acid (EDTA) are complexing agents.
The composition of table three photonasty solution and catalytic activity solution
| Chemicals | Concentration | |
| Photonasty solution | ??SnCl 2·H 2O | ??16g/l |
| ??HCl | ??30g/l | |
| Catalytic activity solution | ??PbCl 2 | ??PbCl 2 |
| ??HCl | ??HCl |
The copper-plated solution composition of the table Four Modernizations
| Chemicals | Concentration | Operating condition |
| ??CuSO 4·5H 2O | ????30g/l | PH:12.5 (NaOH adjusting) |
| ??KNaC 4H 4O 5·4H 2O | ????50g/l | |
| ??EDTA | ????10g/l | Bath temperature: 30～80 ℃ |
| ??HCHO(37％) | ????30g/l |
The 9th step: stripping photolithography glue-line, i.e. photoresist layer 22 on photoresist layer on the N type semiconductor 21 and the P type semiconductor.
In Fig. 1, when electric current flows to P type semiconductor 3 by metal level 4, the contact position will absorb heat, thereby produce low-temperature region 5.Equally, the contact position also will absorb heat when electric current flows to metal level 4 by N type semiconductor 6, thereby constantly absorb heat from surrounding environment with the end that metal links to each other, and make the temperature decline of surrounding environment constitute refrigerator.On the contrary, the temperature difference at thermoelectric material two ends will produce electric current, thereby form miniature current generator.
In Fig. 2-11, electric current flows to the metallic film 23 that chemical plating forms by first heavily doped layer 16 of N type semiconductor, flow to the lightly-doped layer 12 of P type semiconductor, flow to second heavily doped layer 11 of P type semiconductor, flow to the superlattice layer 10 of P type semiconductor, flow to first heavily doped layer 9 of P type semiconductor again.Because the resilient coating 8 of P type semiconductor insulate, so electric current flows to the metallic film 23 that chemical plating forms again, flow to the P type semiconductor material again, thereby the single direction that can realize electric current flows and can realize that electric current can absorb heat from surrounding environment continuously by N → P → N → P.... event, temperature around making descends, thereby constitutes the multi-stage solid stage refrigerator.
Claims (4)
1, a kind of micro-refrigerator, it is characterized in that this refrigerator is a sandwich construction, orlop is high-temperature area (1), on high-temperature area (1), be respectively equipped with two metal levels (2), a metal level (2) is provided with P type semiconductor (3) therein, being provided with N type semiconductor (6) on another piece metal level (2), at P type semiconductor (3) be provided with the last metal level (4) of an integral body above the N type semiconductor (6), is low-temperature region (5) on last metal level (4).
2, micro-refrigerator as claimed in claim 1 is characterized in that the concrete structure of this refrigerator is divided into upper and lower two parts; The orlop of lower part is the Si substrate (7) of P type semiconductor, being provided with resilient coating in the Si of P type semiconductor substrate (7) is the layer (8) that undopes of P type semiconductor, separately first heavily doped layer (9) that is provided with P type semiconductor on the layer (8) that undopes of P type semiconductor, on first heavily doped layer (9) of P type semiconductor, be provided with the superlattice layer (10) of P type semiconductor, on the superlattice layer (10) of P type semiconductor, be provided with second heavily doped layer (11) of P type semiconductor, on second heavily doped layer (11) of P type semiconductor, be provided with the lightly-doped layer (12) of P type semiconductor; The superiors of upper part are the Si substrate (14) of N type semiconductor, have the layer (15) that undopes of N type semiconductor in the Si of N type semiconductor substrate (14), separately first heavily doped layer (16) that is provided with N type semiconductor under the layer (15) that undopes of N type semiconductor, have the superlattice layer (17) of N type semiconductor at first heavily doped layer (16) of N type semiconductor, have second heavily doped layer (19) of N type semiconductor at the superlattice layer (17) of N type semiconductor, have the lightly-doped layer (20) of N type semiconductor at second heavily doped layer (19) of N type semiconductor; This upper and lower two parts intersection matches, and is filled with the metallic film (23) that chemical plating forms in the anastomosis.
3, micro-refrigerator as claimed in claim 1, the element thickness that it is characterized in that this refrigerator is in 1～10 mu m range.
4, a kind of preparation method of micro-refrigerator as claimed in claim 1, it is characterized in that adopting the silicon and germanium super crystal lattice material in III-V family semi-conducting material or the IV family semi-conducting material, adopt chemical plating process to combine simultaneously and form multistage micro-refrigerator with oxide isolation; Adopt plasma reinforced chemical vapour deposition silica membrane protective layer, to realizing the metal film forming between the bonding face of P, N type semiconductor, concrete preparation method is with chemical-copper-plating process:
The first step: pre-treatment is carried out in substrate;
Second step: with molecular beam epitaxy or the metal oxide chemical vapor deposition method superlattice film of growing P-type and N type on two silicon base respectively, cover layer is arranged on superlattice film, resilient coating is arranged below superlattice film, and the bottom is a silicon base;
The 3rd step a: etching: on grow good P type, N type semiconductor, it is carried out etching respectively, etch into first heavily doped layer of P type, N type semiconductor, being about to lightly-doped layer, second heavily doped layer and superlattice layer etches away: secondarily etched: as to make the photoresist protective layer, use reactive ion etching, etch into the resilient coating of P type, N type semiconductor, be about to first heavily doped layer and etch away, remove residual photoresist then;
The 4th step: the plasma reinforced chemical vapour deposition silica membrane is as protective layer;
The 5th step: fall unnecessary silicon dioxide with plasma bombardment, only stay the silicon dioxide on the superlattice sidewall;
The 6th step: make photoresist layer, soon P type, the bottom surface of N type semiconductor, side faces at both ends are made the photoresist protective layer;
The 7th step: with P type and N type semiconductor bonding;
The 8th step: adopt chemical plating process to plate a thin film metal layer, make between P type and the N type semiconductor bonding face contact closely, coating film uniformity;
The 9th step: stripping photoresist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410065714 CN1610139A (en) | 2004-11-15 | 2004-11-15 | Micro refrigerator and producing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410065714 CN1610139A (en) | 2004-11-15 | 2004-11-15 | Micro refrigerator and producing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1610139A true CN1610139A (en) | 2005-04-27 |
Family
ID=34764775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410065714 Pending CN1610139A (en) | 2004-11-15 | 2004-11-15 | Micro refrigerator and producing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1610139A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064146A (en) * | 2010-12-03 | 2011-05-18 | 北京大学 | Cooling structure of chip |
| CN102201531A (en) * | 2011-04-08 | 2011-09-28 | 王艺臻 | Solution for surface metallization pretreatment of semiconductor P/N type refrigerating sheet and application method of same |
| CN104637896A (en) * | 2014-12-24 | 2015-05-20 | 杭州大和热磁电子有限公司 | Novel multistage semiconductor refrigerating device |
| CN105355773A (en) * | 2015-11-11 | 2016-02-24 | 中国科学院上海微系统与信息技术研究所 | Thermoelectric energy collector and manufacturing method thereof |
| CN106059393A (en) * | 2016-07-21 | 2016-10-26 | 王赞 | Inverse piezoelectric thermal rectifier and method of improving thermal rectification efficiency |
-
2004
- 2004-11-15 CN CN 200410065714 patent/CN1610139A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064146A (en) * | 2010-12-03 | 2011-05-18 | 北京大学 | Cooling structure of chip |
| CN102201531A (en) * | 2011-04-08 | 2011-09-28 | 王艺臻 | Solution for surface metallization pretreatment of semiconductor P/N type refrigerating sheet and application method of same |
| CN104637896A (en) * | 2014-12-24 | 2015-05-20 | 杭州大和热磁电子有限公司 | Novel multistage semiconductor refrigerating device |
| CN104637896B (en) * | 2014-12-24 | 2017-06-23 | 杭州大和热磁电子有限公司 | A kind of new multistage semiconductor cooler |
| CN105355773A (en) * | 2015-11-11 | 2016-02-24 | 中国科学院上海微系统与信息技术研究所 | Thermoelectric energy collector and manufacturing method thereof |
| CN105355773B (en) * | 2015-11-11 | 2018-02-13 | 中国科学院上海微系统与信息技术研究所 | A kind of thermoelectric energy collector and preparation method thereof |
| CN106059393A (en) * | 2016-07-21 | 2016-10-26 | 王赞 | Inverse piezoelectric thermal rectifier and method of improving thermal rectification efficiency |
| CN106059393B (en) * | 2016-07-21 | 2018-07-06 | 河南工业大学 | A kind of hot rectifier of inverse piezoelectricity and the method for improving hot rectification efficiency |
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