CN1595379A - Memory unit shared by multiple data processing equipment and method thereof - Google Patents
Memory unit shared by multiple data processing equipment and method thereof Download PDFInfo
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- CN1595379A CN1595379A CN 03158458 CN03158458A CN1595379A CN 1595379 A CN1595379 A CN 1595379A CN 03158458 CN03158458 CN 03158458 CN 03158458 A CN03158458 A CN 03158458A CN 1595379 A CN1595379 A CN 1595379A
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Abstract
The invention relates to a memory storage shared by multiple data processing devices. It is composed of the first data processing device, which stores data to or reads data from the memory storage, and the second data processing device, which reads data from the memory storage. The memory storage is composed of the memory unit matrix module used to store data, the control module, the first data output/input module and the second data output module. The first data output/input module is controlled by the control module and selectively transfers the data from the first data processing equipment to the memory unit matrix module. On the other hand, the first data output/input module reads the data stored in the memory unit matrix module, and then transfers the read data to the first data processing equipment. The second data output module is controlled by the control module. And the read data is transferred to the corresponding second data processing equipment.
Description
Technical field
For shared storage arrangement and the method for a plurality of data processing equipments, particularly these a plurality of data processing equipments are to connect this storage arrangement with different data buss about a kind of in the present invention.
Background technology
See also Fig. 1, Fig. 1 is the functional block diagram of existing single port (single port) storage arrangement 8.Existing memory device 8, can be for one first data processing equipment (not being shown in Fig. 1) and the common use of one second data processing equipment (not being shown in Fig. 1), this first data processing equipment is to these storage arrangement 8 storage/reading of data, and this second data processing equipment is to these storage arrangement 8 reading of data.This storage arrangement 8 comprises a matrix of memory cells module 12, a control module 14 and one first data output/load module 16.
Matrix of memory cells module 12 is in order to storage data, wherein comprise several memory circuit cells 20, and this memory circuit cells 20 is arranged in the matrix of memory cells with M row and N row, and the different memory circuit cells 20 of expression such as the a11 among the figure, a12, a21, a22, a1M, a2M, aN1, aN2 and aNM are positioned at the address coordinate of matrix of memory cells module 12.
The first data output/load module 16 is by these control module 14 controls, input in the matrix of memory cells module 12 in order to the data that optionally will transmit from this first data processing equipment, or read the data that are stored in the matrix of memory cells module 12, and then with the data transmission that read to this first data processing equipment or this second data processing equipment.Because first data processing equipment is not shown in Fig. 1, therefore all transmission all are shown in the arrow tail of arrow line segment with identification with circle from the data and the signal of this first data processing equipment in Fig. 1.
At first, this first data output/load module 16 comprises one first data bus 22 (Data Bus), one second data bus 24, one the 5th data bus 26, one first column address decoder 28, one first row-address decoder 30 and one first line output input circuit 32.
First column address decoder 28 will be in order to will transmit the first column address coded signal, 36 decodings from first data processing equipment, and produce first column address signal 38 of a correspondence, first column address signal 38 via first column address bus 40 with N signal line by first column address decoder, 28 input store cell matrix modules 12, to calibrate the corresponding column address in the matrix of memory cells module 12.
First row-address decoder 30 will be in order to will transmit the first row address coded signal, 42 decodings from this first data processing equipment, and produce first row address signal 44 of a correspondence, first row address signal 44 is imported the first line output input circuit 32 via the first row address bus 46 with M signal line by first row-address decoder 30, to calibrate corresponding row address in the matrix of memory cells module 12.
This first column address signal 38 and this first row address signal 44 that the first line output input circuit 32 is decoded and produced according to this first column address decoder 28 and this first row-address decoder 30, transmission is imported the first line output input circuit 32 from the data of first data processing equipment via the 5th data bus 26, and by having first data bus, the 22 input store cell matrix modules 12 of M signal line, and with the memory circuit cells 20 of this data storing corresponding rank addresses in matrix of memory cells module 12.Perhaps, with the data that are stored in the matrix of memory cells module 12 on the memory circuit cells 20 of corresponding rank addresses, export by first data bus 22, and export the data commentaries on classics of these first data bus, 22 outputs to this first data processing equipment or second data processing equipment by this second data bus 24 with M signal line.
In addition, control module 14 can receive transmission from this first data processing equipment command-control signal 70, and then export the control signal 74 of a correspondence, this control signal 74 can be controlled this first data output/load module 16, makes it be in an input state or an output state.
Yet, along with the capacity of matrix of memory cells module 12 becomes big gradually, be responsible for transferring data to the 5th data bus 26 of matrix of memory cells module 12 by first data processing equipment, and the data of being responsible for to be stored in matrix of memory cells module 12, transfer to second data bus 24 of first data processing equipment or second data processing equipment, because the restriction in hardware circuit space, usually can't be designed to have the data bus of M signal line, generally all be designed to the restriction of the data bus that only has 8 or 16 signal line with adapted space.
The 5th data bus 26 of existing memory device 8 is in when action, is actually data are divided into input store cell matrix module 12 for several times.And second data bus 24 of existing memory device 8 is in when action, in fact also is that the data that will be stored in matrix of memory cells module 12 are divided into and export this first data processing equipment or this second data processing equipment for several times to.When the data volume of the second data processing equipment demand quite big, when perhaps the frequency of its Data Update is also quite high, for example control the display control chip of display frame, the pattern of existing memory device 8, can increase the working load of storage arrangement 8, cause storage arrangement 8 to become the bottleneck of whole data processing work, so the work efficiency that reduces or drag slow first data processing equipment or second data processing equipment.
Prior art is in order to solve the problem that work efficiency big because of data volume or that Data Update frequency height is caused reduces, be earlier the data of exporting to be temporary in the buffer zone (Buffer), allow second data processing equipment directly read the data of buffer zone, though the method can be dealt with problems, but, cost is also increased simultaneously because need to increase an extra element.In addition, also can use twoport (Dual port) storage arrangement to overcome this problem, existing double port memory device has two output/load modules independently separately, these two separately independently output/load module can move simultaneously and not interfere with each other, therefore can improve the work efficiency of storage arrangement, but the price of double port memory device is changed to height more than the single port memory device.
Therefore under the Consideration of cost, the storage arrangement and the method that provide a plurality of data processing equipments of a kind of confession shared is provided fundamental purpose of the present invention, to address the above problem.
Summary of the invention
The invention reside in provides a kind of shared storage arrangement of a plurality of data processing equipments, particularly these a plurality of data processing equipments of supplying with different data bus (Data Bus) connected storage device.Therefore, can make storage arrangement have different output speeds, with the service efficiency of increase storage arrangement, and the number of elements of minimizing data processing equipment.
According to of the present invention one best specific embodiment, the invention provides a kind of for one first data processing equipment and the common storage arrangement that uses of at least one second data processing equipment, it is characterized in that, first data processing equipment is to storage arrangement storage/reading of data, this second data processing equipment is that storage arrangement comprises to the storage arrangement reading of data: a matrix of memory cells module in order to storage data, a control module, one first data output/load module and at least one second data outputting module.The first data output/load module is to be controlled by control module, input in the matrix of memory cells module in order to the data that optionally will transmit from first data processing equipment, or read the data that are stored in the matrix of memory cells module, and then with data transmission to the first data processing equipment that is read.This second data outputting module is by control module control, in order to optionally reading the data that are stored in the matrix of memory cells module, and then with the data transmission that read to corresponding second data processing equipment.
Wherein this matrix of memory cells module comprises a plurality of memory circuit cells that are arranged in a matrix.
Wherein this first data output/load module comprises:
One first data bus;
One second data bus;
One first column address decoder is decoded in order to will transmit from one first column address coded signal of this first data processing equipment, and is produced first column address signal of a correspondence;
One first row-address decoder is decoded in order to will transmit from one first row address coded signal of this first data processing equipment, and is produced first row address signal of a correspondence; And
One first line output/input circuit, this first column address signal that this first line output/input circuit is produced according to this first column address decoder decoding, and this first row address signal of being produced of this first row-address decoder decoding, with the data of transmission from this first data processing equipment, input in this matrix of memory cells module by this first data bus, and with the memory circuit cells of this data storing corresponding rank addresses in this matrix of memory cells module, maybe will be stored in this matrix of memory cells module the data on the memory circuit cells of corresponding rank addresses, export by this first data bus, and export the data commentaries on classics of this first data bus output to this first data processing equipment by this second data bus.
Wherein each second data outputting module of this second data outputting module comprises:
One the 3rd data bus;
One the 4th data bus;
One secondary series address decoder is decoded in order to will transmit from the secondary series address coding signal of this corresponding second data processing equipment, and is produced the secondary series address signal of a correspondence;
One second row-address decoder is decoded in order to will transmit from the second row address coded signal of this corresponding second data processing equipment, and is produced second row address signal of a correspondence; And
One second line output circuit, this secondary series address signal that this second line output circuit is produced according to this secondary series address decoder decoding, and this second row address signal of being produced of this second row-address decoder decoding, with the data that are stored in this matrix of memory cells module on the memory circuit cells of corresponding rank addresses, export by the 3rd data bus, and export the data commentaries on classics of the 3rd data bus output to this corresponding second data processing equipment by the 4th data bus.
Wherein this control module receives the command-control signal of transmission from this first data processing equipment and/or this second data processing equipment, and then exports the control signal of one group of correspondence, and this control signal comprises:
One first control signal makes this first data output/load module be in an input state, one first output state, or is in one first halted state;
At least one second control signal makes this second data outputting module be in one second output state or one second halted state; And
Wherein, when this first data output/load module is in this input state or this first output state, this second data outputting module then is in this second halted state, when one second data outputting module wherein of this second data outputting module is in second output state, this first data output/load module then is in this first halted state, and except that this be in second output state this second data outputting module, all the other these second data outputting module then are in this second halted state.
Wherein this first column address decoder is to carry out into a functional module with the secondary series address decoder, this first column address decoder and secondary series address decoder respectively output first column address signal and secondary series address signal all belong to the output signal that this functional module is exported.
It is a kind of for one first data processing equipment and the common method of using a memory cell matrix module of at least one second data processing equipment that the present invention also provides, it is characterized in that, this first data processing equipment is to this memory cell matrix module storage/reading of data, this second data processing equipment is that this method comprises the following step to this memory cell matrix module reading of data:
Between this first data processing equipment and this memory cell matrix module, provide one first data output/load module, and controlling this first data output/load module optionally will transmit in the data of this first data processing equipment are imported this matrix of memory cells module, or read the data that are stored in this matrix of memory cells module, and then with the data transmission that read to this first data processing equipment; And
Between this second data processing equipment and this memory cell matrix module, provide at least one second data outputting module, and control this second data outputting module and optionally read the data that are stored in this matrix of memory cells module, so with the data transmission that read to corresponding this second data processing equipment.
Wherein this internal storage location matrix module is to be arranged in a matrix and to be formed by a plurality of memory circuit cells.
Wherein this first data output/load module is made up of one first data bus, one second data bus, one first column address decoder, one first row address decoder and first line output/input circuit;
This first column address decoder will be transmitted the one first column address coded signal decoding from this first data processing equipment, and produce first column address signal of a correspondence;
This first row address decoder will be transmitted the one first row address coded signal decoding from this first data processing equipment, and produce first row address signal of a correspondence;
This first column address signal that this first line output/input circuit is produced according to this first column address decoder decoding, and this first row address decoder is deciphered this first row address signal that is produced, with the data of transmission from this first data processing equipment, import this internal storage location matrix module by this first data bus, and with the memory circuit cells of this data storing corresponding rank addresses in this internal storage location matrix module, maybe will be stored in this internal storage location matrix module the data on the memory circuit cells of corresponding rank addresses, export by this first data bus, and export the data commentaries on classics of this first data bus output to this first data processing equipment by this second data bus.
Wherein each second data outputting module of this second data outputting module is made up of one the 3rd data bus, one the 4th data bus, a secondary series address decoder, one second row address decoder, one second line output circuit;
This secondary series address decoder will transmit the secondary series address coding signal decoding from this corresponding second data processing equipment, and produce the secondary series address signal of a correspondence;
This second row address decoder will be transmitted the second row address coded signal decoding from this corresponding second data processing equipment, and produce second row address signal of a correspondence;
This secondary series address signal that this second line output circuit is produced according to this secondary series address decoder decoding, and this second row address decoder is deciphered this second row address signal that is produced, with the data that are stored in this internal storage location matrix module on the memory circuit cells of corresponding rank addresses, export by the 3rd data bus, and export the data commentaries on classics of the 3rd data bus output to this corresponding second data processing equipment by the 4th data bus.
Therefore, storage arrangement provided by the invention, export more data and the second higher data processing equipment of Data Update frequency simultaneously at needs especially, for example control the display control chip of display frame, utilize in second data outputting module, the 4th data bus with abundant signal wire, can once export abundant data, export second data processing equipment to by the matrix of memory cells module rapidly in order to data, so not only can improve the work efficiency of storage arrangement, nor need buffer zone to come temporal data.
Description of drawings
Fig. 1 is the functional block diagram of existing storage arrangement
Fig. 2 is the functional block diagram of storage arrangement of the present invention
Fig. 3 is the first data output/load module of storage arrangement of Fig. 2 and the mode of operation synoptic diagram of second data outputting module
Fig. 4 is another specific embodiment of storage arrangement of the present invention
Fig. 5 is the first data output/load module of storage arrangement of Fig. 4 and the mode of operation synoptic diagram of second data outputting module
Fig. 6 is the method flow diagram of storage arrangement of the present invention
Wherein, description of reference numerals is as follows:
8,10,11: storage arrangement 12: the matrix of memory cells module
14,14a: control module
16: the first data output/load modules
18,18a, 18b, 18c: second data outputting module
20: memory circuit cells
24: the second data buss of 22: the first data buss
28: the first column address decoder of 26: the five data buss
32: the first line output input circuits of 30: the first row-address decoder
38: the first column address signals of 36: the first column address coded signals
42: the first row address coded signals of 40: the first column address bus
46: the first row address buses of 44: the first row address signals
48,48a, 48b, 48c: the 3rd data bus
50,50a, 50b, 50c: the 4th data bus
52: 54: the second row-address decoder of secondary series address decoder
60: secondary series address signal 62: the secondary series address bus
66: the second row address signals of 64: the second row address coded signals
68: the second row address buses
70,72,72a, 72b, 72c: command-control signal
74: the first control signals
76,76a, 76b, 76c: second control signal
78: 80: the first output states of input state
84: the second output states of 82: the first halted states
86: the second halted states
Embodiment
Can be further understood via the following detailed description and accompanying drawings about the advantages and spirit of the present invention.
The object of the present invention is to provide one, can to supply the shared storage arrangement of a plurality of data processing equipments, particularly these a plurality of data processing equipments be with different data bus (Data Bus) connected storage device.Therefore, can make storage arrangement have different output speeds, with the service efficiency of increase storage arrangement, and the number of elements of minimizing data processing equipment.
See also Fig. 2, Fig. 2 is the functional block diagram of storage arrangement 10 of the present invention, storage arrangement 10 of the present invention is can be for one first data processing equipment (not being shown in Fig. 2) and the common storage arrangement 10 that uses of one second data processing equipment (not being shown in Fig. 2), this first data processing equipment is to storage arrangement 10 storage/reading of data, and this second data processing equipment is to storage arrangement 10 reading of data.Storage arrangement 10 comprises, a matrix of memory cells module 12, a control module 14, one first data output/load module 16 and one second data outputting module 18.
Matrix of memory cells module 12 is in order to storage data, wherein comprise several memory circuit cells 20, and memory circuit cells 20 is arranged in the matrix of memory cells with M row and N row, and the a11 among the figure, a12, a21, a22, a1M, a2M, aN1, aN2 and aNM represent that different memory circuit cells 20 is positioned at the address coordinate of matrix of memory cells module 12.
The first data output/load module 16 is by control module 14 controls, input in the matrix of memory cells module 12 in order to the data that optionally will transmit from this first data processing equipment, or read the data that are stored in the matrix of memory cells module 12, and then with the data transmission that read to this first data processing equipment.Because first data processing equipment is not shown in Fig. 2, therefore all transmission all are shown in the arrow tail of arrow line segment with identification with circle from the data and the signal of this first data processing equipment in Fig. 2.
Second data outputting module 18 is by control module 14 control, in order to optionally reading the data that are stored in the matrix of memory cells module 12, and then with the data transmission that read to this second data processing equipment.Because second data processing equipment is not shown in Fig. 2, therefore all transmission all are shown in the arrow tail of arrow line segment with identification with rhombus from the data and the signal of this second data processing equipment in Fig. 2.
At first, the first data output/load module 16 comprises one first data bus 22 (Data Bus), one second data bus 24, one the 5th data bus 26, one first column address decoder 28, one first row-address decoder 30 and one first line output input circuit 32.
First column address decoder 28 is connected with matrix of memory cells module 12 via first column address bus 40 with N signal line, and will transmit the first column address coded signal 36 decoding from first data processing equipment, to produce first column address signal 38 of a correspondence.First column address signal 38 is via first column address bus, 40 input store cell matrix modules 12, to calibrate the corresponding column address in the matrix of memory cells module 12.
First row-address decoder 30 is connected with the first line output input circuit 32 via the first row address bus 46 with M signal line, and will transmit the first row address coded signal 42 decoding, and produce first row address signal 44 of a correspondence from first data processing equipment.First row address signal 44 is via the first row address bus, 46 inputs, the first line output input circuit 32, to calibrate corresponding row address in the matrix of memory cells module 12.
The first line output input circuit 32 is connected with matrix of memory cells module 12 via first data bus 22 with M signal line, and first control signal 74 according to 14 inputs of transmission automatic control molding piece, and first column address decoder 28 and first row-address decoder 30 first column address signal 38 and first row address signal 44 of decoding and producing, optionally will transmit from the data of first data processing equipment via the 5th data bus 26 inputs first line output input circuit 32, and by first data bus, 22 input store cell matrix modules 12, and with the memory circuit cells 20 of data storing corresponding rank addresses in matrix of memory cells module 12.Perhaps, optionally will be stored in the matrix of memory cells module 12 data on the memory circuit cells 20 of corresponding rank addresses, export by first data bus 22, and export the data commentaries on classics of first data bus, 22 outputs to this first data processing equipment by second data bus 24 with M signal line.
Secondly, second data outputting module 18 comprises one the 3rd data bus 48, one the 4th data bus 50, a secondary series address decoder 52, one second row-address decoder 54 and one second line output circuit 56.
Secondary series address decoder 52 is connected with matrix of memory cells module 12 via the secondary series address bus 62 with N signal line, and will transmit secondary series address coding signal 58 decoding from second data processing equipment, to produce the secondary series address signal 60 of a correspondence.Secondary series address signal 60 is via secondary series address bus 62 input store cell matrix modules 12, to calibrate the corresponding column address in the matrix of memory cells module 12.
Second row-address decoder 54 is connected with second line output circuit 56 via the second row address bus 68 with M signal line, and will transmit the second row address coded signal 64 decoding, and produce second row address signal 66 of a correspondence from second data processing equipment.Second row address signal 66 is via the second row address bus, 68 inputs, second line output circuit 56, to calibrate corresponding row address in the matrix of memory cells module 12.
Second line output circuit 56 is connected with matrix of memory cells module 12 via the 3rd data bus 48 with M signal line, and second control signal 76 according to 14 inputs of transmission automatic control molding piece, and secondary series address decoder 52 and second row-address decoder 54 the secondary series address signal 60 and second row address signal 66 of decoding and producing, optionally will be stored in the matrix of memory cells module 12 data on the memory circuit cells 20 of corresponding rank addresses, export by the 3rd data bus 48, and export the data commentaries on classics of the 3rd data bus 48 outputs to this second data processing equipment by the 4th data bus 50 with M signal line.
See also Fig. 2 and Fig. 3, Fig. 3 is the first data output/load module 16 and the mode of operation synoptic diagram of second data outputting module 18, wherein the transverse axis express time of the storage arrangement 10 of Fig. 2.As shown in FIG., first control signal 74 can be controlled the first data output/load module 16 and be in an input state 78, one first output state 80, or be in one first halted state 82.Second control signal 76 can be controlled second data outputting module 18 and be in one second output state 84 or one second halted state 86.Input state 78 is via the first data output/load module 16, with data input store cell matrix module 12.First output state 80 will be stored in matrix of memory cells module 12 with the first data output/load module 16 and export first data processing equipment to.Second output state 84 will be stored in matrix of memory cells module 12 with second data outputting module 18 and export second data processing equipment to.
Wherein, when the first data output/load module 16 is in the input state 78 or first output state 80,18 of second data outputting module are in second halted state 86, when second data outputting module 18 was in second output state 84,16 of the first data output/load modules were in first halted state 82.
This mode of operation is different from existing double port memory device, existing double port memory device has two output/load modules independently separately, these two separately independently output/load module can independently import simultaneously data separately to the double port memory device, or simultaneously separately independently by double port memory device output data, perhaps wherein output/load module input data arrive the double port memory device, simultaneously another output/load module is then by double port memory device output data, and these two independently can not interfere with each other between output/load module separately.
And storage arrangement 10 of the present invention, though have one first data output/load module 16 and one second data outputting module 18, but be with the difference of existing double port memory device, storage arrangement 10 of the present invention only has three kinds of modes of operation, comprises input state 78, first output state 80 and second output state 84.And the first data output/load module 16 and second data outputting module 18 can be according to first control signal 74 of control module 14 outputs and the control sequences of second control signal 76, in proper order enter input state 78 or first output state 80 or second output state 84.And when the first data output/load module 16 is in the input state 78 or first output state 80,18 of second data outputting module are in one second halted state 86, and when second data outputting module 18 was in second output state 84,16 of the first data output/load modules were in one first halted state 82.
In addition, first column address decoder 28 and secondary series address decoder 52 belong to the identical functions module, and first column address bus 40 and secondary series address bus 62 also belong to the identical functions module, therefore first column address decoder 28 and secondary series address decoder 52 respectively first column address signal 38 of output belong to the output signal that the identical function module is exported with secondary series address signal 60.
Along with the capacity of matrix of memory cells module 12 becomes big gradually, be responsible for transferring data to the 5th data bus 26 of matrix of memory cells module 12 by first data processing equipment, and the data of being responsible for to be stored in matrix of memory cells module 12, transfer to second data bus 24 of first data processing equipment, because the restriction in hardware circuit space, usually can't be designed to have the data bus of M signal line, generally all be designed to the restriction of the data bus that only has 8 or 16 signal line with adapted space.
Therefore, the 5th data bus 26 of existing memory device 8 is in when action, is actually data are divided into input store cell matrix module 12 for several times.And second data bus 24 of existing memory device 8 is in when action, in fact also is that the data that will be stored in matrix of memory cells module 12 are divided into and export this first data processing equipment or this second data processing equipment for several times to.And the data volume of working as output is bigger, or the frequency of Data Update is when quite high, the working load of storage arrangement 8 can more increase the weight of, therefore cause storage arrangement 8 to become the bottleneck of whole data processing work, the work efficiency that also reduces or drag slow first data processing equipment or second data processing equipment.
In order to overcome the problems referred to above, the present invention exports more data and the second higher data processing equipment of Data Update frequency simultaneously at needs especially, for example control the control chip of display frame, utilize second data outputting module 18, wherein the 4th data bus 50 is the data buss with abundant signal wire, can once export abundant data, export second data processing equipment to by matrix of memory cells module 12 rapidly in order to data, so not only can increase the work efficiency of storage arrangement 10, nor need this buffer zone to come temporal data.
As for increasing the data bus signal line, the required space of hardware circuit also needs the problem that thereupon increases, then can overcome via second data processing equipment and storage arrangement 10 are made in same integrated circuit.Therefore, first data processing equipment and second data processing equipment just can share same memory devices 10, and can make storage arrangement 10 have different output speeds, with the service efficiency of increase storage arrangement 10, and the number of elements of minimizing data processing equipment.
In other words, storage arrangement 10 of the present invention is that the data of utilizing one second data outputting module 18 will be stored in matrix of memory cells module 12 export second data processing equipment to, for example controls the display frame control chip of display frame.The then responsible matrix of memory cells module 12 of the first data output/load module 16 and first data processing equipment, CPU for example, between the two data input and output.And storage arrangement 10 of the present invention can also be integrated in the display frame control chip, carries out with the technology of SOC (system on a chip) (SoC, System on a Chip), not only can solve the above problems, and also can reduce manufacturing cost.
See also Fig. 4, Fig. 4 is another specific embodiment of storage arrangement 11 of the present invention.Storage arrangement 11 of the present invention is can be for one first data processing equipment (not being shown in Fig. 4) and the common storage arrangement 11 that uses of three second data processing equipments (not being shown in Fig. 4), this first data processing equipment is to storage arrangement 11 storage/reading of data, and this second data processing equipment is to storage arrangement 11 reading of data.Storage arrangement 11 comprises, a matrix of memory cells module 12, a control module 14a, one first data output/load module 16 and three second data outputting module 18a, 18b, 18c.
Wherein, control module 14a can receive command- control signal 70,72a, 72b, the 72c of transmission from this first data processing equipment and this second data processing equipment, and then exporting control signal 74,76a, 76b, the 76c of one group of correspondence, this group control signal 74,76a, 76b, 76c comprise one first control signal 74 and three second control signal 76a, 76b, 76c.
The first data output/load module 16 is controlled by control module 14a, input in the matrix of memory cells module 12 via first data bus 22 in order to the data that optionally will transmit from this first data processing equipment according to first control signal 74, or read the data that are stored in the matrix of memory cells module 12, and then the data that read are transferred to this first data processing equipment via second data bus 24 via first data bus 22.
The second data outputting module 18a, 18b, 18c are controlled by control module 14a, this second data outputting module 18a, 18b, 18c respectively according to etc. two control signal 76a, 76b, 76c, in order to optionally reading the data that are stored in the matrix of memory cells module 12, and then the data that read are transferred to corresponding second data processing equipment via the 4th data bus 50a, 50b, 50c via the 3rd data bus 48a, 48b, 48c.
See also Fig. 4 and Fig. 5, Fig. 5 is the mode of operation synoptic diagram of the first data output/load module 16 of storage arrangement 11 of Fig. 4 and the second data outputting module 18a, 18b, 18c, wherein transverse axis express time.As shown in FIG., first control signal 74 can be controlled the first data output/load module 16 and be in an input state 78, one first output state 80, or be in one first halted state 82.The second control signal 76a, 76b, 76c control the second data outputting module 18a respectively, 18b, 18c are in one second output state 84 or one second halted state 86 separately.Input state 78 is via the first data output/load module 16, with data input store cell matrix module 12.First output state 80 is meant that the first data output/load module 16 will be stored in matrix of memory cells module 12 and export first data processing equipment to.Second output state 84 is meant that this second data outputting module 18a, 18b, 18c will be stored in matrix of memory cells module 12 and export corresponding this two data processing equipment to.
Wherein, when the first data output/load module 16 was in the input state 78 or first output state 80, this second data outputting module 18a, 18b, 18c then were in second halted state 86.As this second data outputting module 18a, when 18b, 18c are in second output state 84,16 of the first data output/load modules are in first halted state 82, and except this was in the second data outputting module 18a, 18b, 18c of second output state 84, all the other this second data outputting module 18a, 18b, 18c then were in second halted state 86.
See also Fig. 6, Fig. 6 is the method flow diagram of storage arrangement 10 of the present invention.Below with detailed description be applied to Fig. 2 of the present invention for one first data processing equipment and the common method of using a matrix of memory cells module 12 of one second data processing equipment.The inventive method comprises the following step:
S88: control module 14 receives the command- control signal 70,72 of transmission from this first data processing equipment and this second data processing equipment, and then exports the control signal 74,76 of one group of correspondence.First control signal 74 of this group control signal 74,76 can make the first data output/load module 16 be in an input state 78, one first output state 80, or is in one first halted state 82.And second control signal 76 of this group control signal 74,76 can make second data outputting module 18 be in one second output state 84 or one second halted state 86.Wherein, when the first data output/load module 16 is in the input state 78 or first output state 80,18 of second data outputting module are in second halted state 86, when second data outputting module 18 was in second output state 84,16 of the first data output/load modules were in first halted state 82.
S90: when the first data output/load module 16 is in an input state 78, the first line output input circuit 32 can be according to first column address signal 38 and first row address signal 44, with transmission from the data input store cell matrix module 12 of first data processing equipment, and with the memory circuit cells 20 of data storing corresponding rank addresses in matrix of memory cells module 12.
S92: when the first data output/load module 16 is in one first output state 80, the first line output input circuit 32 can be according to first column address signal 38 and first row address signal 44, data with being stored in the matrix of memory cells module 12 on the memory circuit cells 20 of corresponding rank addresses export this first data processing equipment to.
S94: when second data outputting module 18 is in one second output state 84, second line output circuit 56 can be according to the secondary series address signal 60 and second row address signal 66, data with being stored in the matrix of memory cells module 12 on the memory circuit cells 20 of corresponding rank addresses export this second data processing equipment to.
Along with the capacity of matrix of memory cells module 12 becomes big gradually, be responsible for transferring data to the 5th data bus 26 of matrix of memory cells module 12 by first data processing equipment, and the data of being responsible for to be stored in matrix of memory cells module 12, transfer to second data bus 24 of first data processing equipment, because the restriction in hardware circuit space, usually can't be designed to have the data bus of M signal line, generally all be designed to the restriction of the data bus that only has 8 or 16 signal line with adapted space.
Therefore, the 5th data bus 26 of existing memory device 8 is in when action, is actually data are divided into input store cell matrix module 12 for several times.And second data bus 24 of existing memory device 8 is in when action, in fact also is that the data that will be stored in matrix of memory cells module 12 are divided into and export this first data processing equipment or this second data processing equipment for several times to.And the data volume of working as output is bigger, or the frequency of Data Update is when quite high, the working load of storage arrangement 8 can more increase the weight of, therefore cause storage arrangement 8 to become the bottleneck of whole data processing work, the work efficiency that also reduces or drag slow first data processing equipment or second data processing equipment.
In order to overcome above-mentioned problem, the present invention exports more data and the second higher data processing equipment of Data Update frequency simultaneously at needs especially, for example control the display frame control chip of display frame, utilize second data outputting module 18, wherein the 4th data bus 50 has the data bus of abundant signal wire, can once export abundant data, export second data processing equipment to by matrix of memory cells module 12 rapidly in order to data, so not only can increase the work efficiency of storage arrangement 10, nor need this buffer zone to come temporal data.
As for increasing the data bus signal line, the problem that the required space of hardware circuit also increases thereupon then can overcome via second data processing equipment and storage arrangement 10 are made in same integrated circuit.Therefore, first data processing equipment and second data processing equipment just can share same memory devices 10, and can make storage arrangement 10 have different output speeds, with the service efficiency of increase storage arrangement 10, and the number of elements of minimizing data processing equipment.
In other words, the data that storage arrangement 10 of the present invention utilizes one second data outputting module 18 will be stored in matrix of memory cells module 12 export second data processing equipment to, for example control the display frame control chip of display frame.The then responsible matrix of memory cells module 12 of the first data output/load module 16 and first data processing equipment, CPU for example, between the two data input and output.And storage arrangement 10 of the present invention can also be integrated in the display frame control chip, carries out with the technology of Soc (System on a Chip), not only can solve the above problems, and also can reduce manufacturing cost.
Via the detailed description of above preferred embodiment, hope can be known description feature of the present invention and spirit more, and is not to come scope of the present invention is limited with above disclosed preferred embodiment.On the contrary, its objective is that hope can contain in the claim of being arranged in of various changes and tool equivalence institute of the present invention desire protection.
Claims (10)
1. one kind for the common storage arrangement that uses of one first data processing equipment and at least one second data processing equipment, it is characterized in that, this first data processing equipment is to this storage arrangement storage/reading of data, this second data processing equipment is that this storage arrangement comprises to this storage arrangement reading of data:
One matrix of memory cells module, this matrix of memory cells module is in order to storage data;
One control module;
One first data output/load module, this first data output/load module is by this control module control, input in this matrix of memory cells module in order to the data that optionally will transmit from this first data processing equipment, or read the data that are stored in this matrix of memory cells module, and then with the data transmission that read to this first data processing equipment; And
At least one second data outputting module, this second data outputting module be by the control of this control module, in order to optionally reading the data that are stored in this matrix of memory cells module, and then with the data transmission that read to corresponding this second data processing equipment.
2. storage arrangement as claimed in claim 1 is characterized in that, wherein this matrix of memory cells module comprises a plurality of memory circuit cells that are arranged in a matrix.
3. storage arrangement as claimed in claim 2 is characterized in that, wherein this first data output/load module comprises:
One first data bus;
One second data bus;
One first column address decoder is decoded in order to will transmit from one first column address coded signal of this first data processing equipment, and is produced first column address signal of a correspondence;
One first row-address decoder is decoded in order to will transmit from one first row address coded signal of this first data processing equipment, and is produced first row address signal of a correspondence; And
One first line output/input circuit, this first column address signal that this first line output/input circuit is produced according to this first column address decoder decoding, and this first row address signal of being produced of this first row-address decoder decoding, with the data of transmission from this first data processing equipment, input in this matrix of memory cells module by this first data bus, and with the memory circuit cells of this data storing corresponding rank addresses in this matrix of memory cells module, maybe will be stored in this matrix of memory cells module the data on the memory circuit cells of corresponding rank addresses, export by this first data bus, and export the data commentaries on classics of this first data bus output to this first data processing equipment by this second data bus.
4. storage arrangement as claimed in claim 3 is characterized in that, wherein each second data outputting module of this second data outputting module comprises:
One the 3rd data bus;
One the 4th data bus;
One secondary series address decoder is decoded in order to will transmit from the secondary series address coding signal of this corresponding second data processing equipment, and is produced the secondary series address signal of a correspondence;
One second row-address decoder is decoded in order to will transmit from the second row address coded signal of this corresponding second data processing equipment, and is produced second row address signal of a correspondence; And
One second line output circuit, this secondary series address signal that this second line output circuit is produced according to this secondary series address decoder decoding, and this second row address signal of being produced of this second row-address decoder decoding, with the data that are stored in this matrix of memory cells module on the memory circuit cells of corresponding rank addresses, export by the 3rd data bus, and export the data commentaries on classics of the 3rd data bus output to this corresponding second data processing equipment by the 4th data bus.
5. storage arrangement as claimed in claim 4, it is characterized in that, wherein this control module receives the command-control signal of transmission from this first data processing equipment and/or this second data processing equipment, and then exports the control signal of one group of correspondence, and this control signal comprises:
One first control signal makes this first data output/load module be in an input state, one first output state, or is in one first halted state;
At least one second control signal makes this second data outputting module be in one second output state or one second halted state; And
Wherein, when this first data output/load module is in this input state or this first output state, this second data outputting module then is in this second halted state, when one second data outputting module wherein of this second data outputting module is in second output state, this first data output/load module then is in this first halted state, and except that this be in second output state this second data outputting module, all the other these second data outputting module then are in this second halted state.
6. storage arrangement as claimed in claim 5, it is characterized in that, wherein this first column address decoder is to carry out into a functional module with the secondary series address decoder, this first column address decoder and secondary series address decoder respectively output first column address signal and secondary series address signal all belong to the output signal that this functional module is exported.
7. one kind for the common method of using a memory cell matrix module of one first data processing equipment and at least one second data processing equipment, it is characterized in that, this first data processing equipment is to this memory cell matrix module storage/reading of data, this second data processing equipment is that this method comprises the following step to this memory cell matrix module reading of data:
Between this first data processing equipment and this memory cell matrix module, provide one first data output/load module, and controlling this first data output/load module optionally will transmit in the data of this first data processing equipment are imported this matrix of memory cells module, or read the data that are stored in this matrix of memory cells module, and then with the data transmission that read to this first data processing equipment; And
Between this second data processing equipment and this memory cell matrix module, provide at least one second data outputting module, and control this second data outputting module and optionally read the data that are stored in this matrix of memory cells module, so with the data transmission that read to corresponding this second data processing equipment.
8. method as claimed in claim 7 is characterized in that, wherein this internal storage location matrix module is to be arranged in a matrix and to be formed by a plurality of memory circuit cells.
9. method as claimed in claim 8, it is characterized in that wherein this first data output/load module is made up of one first data bus, one second data bus, one first column address decoder, one first row address decoder and first line output/input circuit;
This first column address decoder will be transmitted the one first column address coded signal decoding from this first data processing equipment, and produce first column address signal of a correspondence;
This first row address decoder will be transmitted the one first row address coded signal decoding from this first data processing equipment, and produce first row address signal of a correspondence;
This first column address signal that this first line output/input circuit is produced according to this first column address decoder decoding, and this first row address decoder is deciphered this first row address signal that is produced, with the data of transmission from this first data processing equipment, import this internal storage location matrix module by this first data bus, and with the memory circuit cells of this data storing corresponding rank addresses in this internal storage location matrix module, maybe will be stored in this internal storage location matrix module the data on the memory circuit cells of corresponding rank addresses, export by this first data bus, and export the data commentaries on classics of this first data bus output to this first data processing equipment by this second data bus.
10. method as claimed in claim 9, it is characterized in that wherein each second data outputting module of this second data outputting module is made up of one the 3rd data bus, one the 4th data bus, a secondary series address decoder, one second row address decoder, one second line output circuit;
This secondary series address decoder will transmit the secondary series address coding signal decoding from this corresponding second data processing equipment, and produce the secondary series address signal of a correspondence;
This second row address decoder will be transmitted the second row address coded signal decoding from this corresponding second data processing equipment, and produce second row address signal of a correspondence;
This secondary series address signal that this second line output circuit is produced according to this secondary series address decoder decoding, and this second row address decoder is deciphered this second row address signal that is produced, with the data that are stored in this internal storage location matrix module on the memory circuit cells of corresponding rank addresses, export by the 3rd data bus, and export the data commentaries on classics of the 3rd data bus output to this corresponding second data processing equipment by the 4th data bus.
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| CN107408076A (en) * | 2015-04-08 | 2017-11-28 | 国立大学法人奈良先端科学技术大学院大学 | Data processing equipment |
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| CN107408076A (en) * | 2015-04-08 | 2017-11-28 | 国立大学法人奈良先端科学技术大学院大学 | Data processing equipment |
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