CN1594067A - Low-temperature integrated wafer level airtight package process for MESM - Google Patents
Low-temperature integrated wafer level airtight package process for MESM Download PDFInfo
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- CN1594067A CN1594067A CN 03156716 CN03156716A CN1594067A CN 1594067 A CN1594067 A CN 1594067A CN 03156716 CN03156716 CN 03156716 CN 03156716 A CN03156716 A CN 03156716A CN 1594067 A CN1594067 A CN 1594067A
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Abstract
A low-temperature integrated wafer level airtight package process for MESM comprises following steps: 1. evaporation deposition of a layer of aluminium/chrome on the silicon base-plate; 2. casting a layer of photo resist on the aluminium/chrome layer and MEMS element, drying; 3. evaporation deposition of a layer of gold/chrome on the upper surface of the silicon base-plate and on the aluminium/chrome layer and photo resist; 4. coating a layer of resin adhesive around the gold/chrome; 5. plating a layer of nickel in the resin adhesive; 6. exposing aluminium/chrome layer; 7. forming sacrificial hole; 8. removing the photo resist; 9. sputter deposition of the gold/chrome layer in the position of former aluminium/chrome layer; 10. platting gold layer to seal the sacrificial hole. The invention has a good encapsulation quality, a reduced volume, a simple craft and a low cost.
Description
Technical field
Patent of the present invention relates to a kind of encapsulation technology of MEMS, the wafer level MEMS air-tight packaging technology that particularly a kind of low temperature is integrated.
Background technology
Along with the development of microtechnology, the increasingly stringent that requires for the air-tight packaging technology of MEMS (Micro-Electro-MechanicalSystems is hereinafter to be referred as MEMS) requires the air-tight packaging that size is littler, with better function, cost is lower.Also require to carry out Vacuum Package for micro-acceleration gauge, little humorous Vibration Meter, gyroscope, so that obtain higher quality.For wafer-level MEMS air-tight packaging technology, mainly contain two kinds of packaging technologies at present: the one, the film integrated technique.It deposited thin film on sacrifice layer before discharging in the MEMS micro-structural, remove sacrifice layer by technology etch pit on the film then, thereby finish the air-tight packaging of MEMS again with these fabrication holes of diaphragm seal.This technology has simple, the low cost and other advantages of operation, but the film of deposition has only 1～2 micron thickness at most, and this disk section and disk that is difficult in subsequently picks up to wait in the operation and guarantees to stand intact, down to causing the yield rate of encapsulation to reduce greatly.The 2nd, the bonding technology of substrate and cap.Wherein use maximum thermal bonding modes, can be divided into two kinds of whole heating and local heat.For the monoblock type heating, its high temperature can damage the circuit and the heat sensitivity material of MEMS inside.For local heat, it makes the bonding zone produce localized hyperthermia by the local heat of little heater wire, and other zone still is in low temperature, substrate and cap are bonded together, because there is very big thermograde in this method, thereby localized heat stress is very big, and this localized heat stress tends to cause the change of material property and the inefficacy of device.For head it off, size must be strengthened, this can make small product size big, and influence is installed and used.In addition, also have some other bonding mode such as electrostatic bonding, microwave bonding etc., required high voltage, the microwave of its bonding diminishes the MEMS circuit, thereby do not have the versatility of MEMS encapsulation.Because bonding technology needs cap, thereby cost is higher and the bonding zone of chip is very big, the waste that causes chip size to increase.Therefore, in the manufacturing of MEMS device, packaging process is one of key, also is the bottleneck during commercialization is promoted.
Content of the present invention
The objective of the invention is to propose a kind of wafer-level MEMS air-tight packaging technology of the low temperature based on little electroforming.The present invention compared with prior art has no thermal stress deformation, package quality height, yield rate height, volume reduces, technology is simple, cost is low advantage.
The objective of the invention is to realize by following technical scheme.Technology of the present invention may further comprise the steps:
Step (1), on silicon chip 1, evaporation deposition layer of aluminum/chromium layer is as sacrifice layer;
Step (2), on described aluminium/chromium layer, throw casting one deck photoresist, oven dry makes described photoresist attenuate then;
On the profile of step (3), the upper surface at described silicon chip 1, aluminium/chromium layer and photoresist, evaporation deposition one deck gold/chromium layer is as Seed Layer;
Step (4), around described gold/chromium layer, be coated with casting one deck resin glue as electroplating mould;
Step (5), in described resin glue, electroplate one deck nickel dam;
Step (6), peel the resin glue around the described nickel dam and the gold/chromium layer of part off, to expose described aluminium/chromium layer;
Step (7), peel described whole aluminium/chromium layer off; Form and sacrifice the hole;
Step (8), enter into inner chamber, described photoresist is removed with developer solution;
Step (9), in the position of original aluminium/chromium layer, promptly sacrifice place, hole, sputtering deposit gold/chromium layer;
Step (10), at place, the sacrifice hole of described gold/chromium layer, the electrogilding layer is to seal described sacrifice hole.
In described step (9), when having phosphorosilicate glass on the MEMS device, after the phosphorosilicate glass in peeling inner chamber off, sacrificing place, hole sputtering deposit gold/chromium layer again;
In the described step (1), the thickness of the aluminium of described evaporation deposition/chromium layer is that aluminium is the 140-160 nanometer, and chromium is the 25-35 nanometer.
In the described step (2), the thickness of described photoresist layer is the 16-20 micron.
In the described step (3), the thickness of described chromium/gold layer is the 50-500 nanometer.
In the described step (4), the thickness of described resin glue is the 28-33 micron.
In the described step (5), the thickness of described nickel dam is 35～40 microns.
In the described step (9), the thickness of described gold/chromium layer is golden thickness range 150～500 nanometers,
Chromium thickness range 20～50 nanometers.
In the described step (10), 5～50 microns of described golden layer thickness scopes.
The present invention is directed to all deficiencies that present wafer-level MEMS air-tight packaging technology exists, yielding as heated sealant, airtight quality is low, package dimension is big, complex process, shortcoming that cost is high, from method for packing, innovated, adopt the low temperature method for packing of non-heating, the inventive method is based on the wafer-level MEMS air-tight packaging technology of the low temperature of little electroforming.Owing to adopt the corrosion of coating method, make when encapsulation and need not heat, avoided both having improved airtight quality because of thermal deformation influences product quality, reduced packed size simultaneously again.Metal-back by little electroforming tens even thousands of micron thickness on sacrifice layer comes the MEMS chip is carried out air-tight packaging; the present invention has overcome in the film integrated technique; the shortcoming of the weak rapid wear of containment vessel, the present invention has the reliable protection shell, has improved yield rate.Each procedure of processing of the present invention is routine techniques, has the simple and low cost and other advantages of technology.For micro-acceleration gauge, little humorous Vibration Meter, gyroscope, can carry out Vacuum Package in conjunction with the present invention, to obtain higher quality factor.The inventive method can greatly promote the MEMS Development of Packaging Technology and promote the commercialization of MEMS encapsulation technology to promote.
In sum, the present invention compared with prior art has no thermal stress deformation, package quality height, yield rate height, volume reduces, technology is simple, cost is low advantage.
Description of drawings
Fig. 1-10 is an artwork of the present invention.
Code name among the figure
1 silicon chip, 2 chromium/aluminium lamination (sacrifice layer) 3 photoresists (PR)
4 gold medals/chromium layer (Seed Layer) 5 resin glues 6 nickel dams
7 gold medals/chromium layer 8 gold medal layer 9 are sacrificed the hole
10 inner chambers, 11 phosphorosilicate glass PSG, 12 MEMS devices
Embodiment:
The wafer-level MEMS air-tight packaging technology that low temperature of the present invention is integrated is after carrying out MEMS device 12 on the silicon chip 1, encapsulates.Described encapsulation may further comprise the steps:
Step (1), as Fig. 1, evaporation deposition layer of aluminum/chromium layer 2 (aluminium lamination is last, chromium layer down) is to the silicon chip of thermal oxide growth silica.Wherein, aluminium lamination is thick to be 150 nanometers, and the chromium bed thickness is 30 nanometers.Aluminium lamination so that after eroding aluminium in the operation of back, forms the passage of corrosive liquid turnover as sacrifice layer, and the effect of chromium layer is the protection aluminium lamination in order to avoid be subjected to the corrosion of developer solution in the back step operation.
Step (2), as Fig. 2, throw the photoresist 3 of casting one deck 18 micron thickness in the above, the photoresist that present embodiment adopts is the AZ9260 photoresist, dries by the fire 2 hours then to eliminate aqueous vapor in the glue to be thinned to 6～8 microns thickness.
Step (3), as Fig. 3, evaporation deposition one bed thickness is that the gold/chromium layer 4 (chromium layer down) of 100 nanometers is as Seed Layer, so that later metal nickel dam 6 can be electroplated in the above.
Step (4), as Fig. 4, around Seed Layer is gold/chromium layer 4, be coated with the mould of the resin glue 5 of casting one deck 28 micron thickness as electronickelling.
Step (5), as Fig. 5, in above-mentioned mould, electroplate the nickel dam 6 of one deck 35 micron thickness.
Step (6), as Fig. 6, peel chromium/gold layers 4 of resin glue 5 around the nickel dam and part off, so that expose aluminium/chromium layer 2.
Step (7), as Fig. 7, peel whole aluminium/chromium layer 2 off, form to sacrifice hole 9.
Step (8), as Fig. 8, developer solution enters into inner chamber photoresist 3 is removed.
Step (9), as Fig. 9, erode phosphorosilicate glass 11, so that discharge the cantilever beam of MEMS device 12.And promptly sacrifice 9 places, hole in the position of original aluminium/chromium layer 2, sputtering deposit gold/chromium layer 7 (chromium layer down), wherein, gold layer 200 nanometer, chromium layer 30 nanometer.
Step (10), as Figure 10, again at 9 places, sacrifice hole of gold/chromium layer 7, plating thick is 25 microns a gold layer 8, sacrifices hole 9 so that seal.
Claims (9)
1, the integrated wafer-level MEMS air-tight packaging technology of a kind of low temperature is characterized in that: may further comprise the steps:
Step (1), on silicon chip (1), evaporation deposition layer of aluminum/chromium layer (2);
Step (2), at described aluminium/chromium layer (2) and above the MEMS device (12), throw casting one deck photoresist (3), oven dry makes described photoresist (3) attenuate then;
On step (3), the upper surface in described silicon chip (1), aluminium/chromium layer (2) and the photoresist (3), evaporation deposition one deck gold/chromium layer (4) is as Seed Layer;
Step (4), around described gold/chromium layer (4), be coated with casting one deck resin glue (5) as electroplating mould;
Step (5), in described resin glue (5), electroplate one deck nickel dam (6);
Step (6), peel off described nickel dam (6) on every side resin glue (5) and the part gold/chromium layer (4), to expose described aluminium/chromium layer (2);
Step (7), peel described whole aluminium/chromium (2) layer off; Form and sacrifice hole (9);
Step (8), enter into inner chamber (10), described photoresist (3) is removed with developer solution;
Step (9), in the position of original aluminium/chromium (2) layer, promptly sacrifice hole (9) and locate sputtering deposit gold/chromium layer (7);
Step (10), the sacrifice hole (9) on described gold/chromium layer (7) are located, and electrogilding layer (8) is to seal described sacrifice hole (9).
2, the integrated wafer-level MEMS air-tight packaging technology of low temperature according to claim 1 and 2 is characterized in that:
In the described step (9), when MEMS device (12) was gone up with phosphorosilicate glass (11), the phosphorosilicate glass (11) in peeling inner chamber (10) off was located sputtering deposit gold/chromium layer (7) in sacrifice hole (9) afterwards again;
3, the integrated wafer-level MEMS air-tight packaging technology of low temperature according to claim 1 and 2 is characterized in that:
In the described step (1), the thickness of the aluminium of described evaporation deposition/chromium layer (2) is that aluminium is the 140-160 nanometer, and chromium is the 25-35 nanometer.
4, the integrated wafer-level MEMS air-tight packaging technology of low temperature according to claim 1 and 2 is characterized in that:
In the described step (2), the thickness of described photoresist layer (3) is the 16-20 micron.
5, the integrated wafer-level MEMS air-tight packaging technology of low temperature according to claim 1 and 2 is characterized in that:
In the described step (3), the thickness of described chromium/gold layer (4) is the 50-500 nanometer.
6, the integrated wafer-level MEMS air-tight packaging technology of low temperature according to claim 1 and 2 is characterized in that:
In the described step (4), the thickness of described resin glue (5) is the 28-33 micron.
7, the integrated wafer-level MEMS air-tight packaging technology of low temperature according to claim 1 and 2 is characterized in that:
In the described step (5), the thickness of described nickel dam (6) is 35～40 microns.
8, the integrated wafer-level MEMS air-tight packaging technology of low temperature according to claim 1 and 2 is characterized in that:
In the described step (9), the thickness of described gold/chromium layer (7) is golden thickness range 150～500 nanometers, chromium thickness range 20～50 nanometers.Micron.
9, the integrated wafer-level MEMS air-tight packaging technology of low temperature according to claim 1 and 2 is characterized in that:
In the described step (10), 5～50 microns of described gold layer (8) thickness ranges.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03156716 CN1594067A (en) | 2003-09-08 | 2003-09-08 | Low-temperature integrated wafer level airtight package process for MESM |
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| CN 03156716 CN1594067A (en) | 2003-09-08 | 2003-09-08 | Low-temperature integrated wafer level airtight package process for MESM |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100445195C (en) * | 2006-01-13 | 2008-12-24 | 中国科学院上海微系统与信息技术研究所 | Low temperature airtightness packaging method for wafer level micro machinery device and photoelectric device |
| CN100564243C (en) * | 2006-01-13 | 2009-12-02 | 中国科学院上海微系统与信息技术研究所 | A kind of preparation method of low-temperature wafer-level mini-sized gas container |
| CN101291873B (en) * | 2005-12-06 | 2011-06-15 | 工程吸气公司 | Process for manufacturing micromechanical devices containing a getter material |
| CN102963864A (en) * | 2012-12-11 | 2013-03-13 | 北京大学 | Method for sealing wafer-level micro-cavity based on BCB (benzocyclobutene) glue |
-
2003
- 2003-09-08 CN CN 03156716 patent/CN1594067A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101291873B (en) * | 2005-12-06 | 2011-06-15 | 工程吸气公司 | Process for manufacturing micromechanical devices containing a getter material |
| CN100445195C (en) * | 2006-01-13 | 2008-12-24 | 中国科学院上海微系统与信息技术研究所 | Low temperature airtightness packaging method for wafer level micro machinery device and photoelectric device |
| CN100564243C (en) * | 2006-01-13 | 2009-12-02 | 中国科学院上海微系统与信息技术研究所 | A kind of preparation method of low-temperature wafer-level mini-sized gas container |
| CN102963864A (en) * | 2012-12-11 | 2013-03-13 | 北京大学 | Method for sealing wafer-level micro-cavity based on BCB (benzocyclobutene) glue |
| CN102963864B (en) * | 2012-12-11 | 2015-05-20 | 北京大学 | Method for sealing wafer-level micro-cavity based on BCB (benzocyclobutene) glue |
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