CN1591818A - Method for making double inserted open structure - Google Patents
Method for making double inserted open structure Download PDFInfo
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- CN1591818A CN1591818A CN 03156045 CN03156045A CN1591818A CN 1591818 A CN1591818 A CN 1591818A CN 03156045 CN03156045 CN 03156045 CN 03156045 A CN03156045 A CN 03156045A CN 1591818 A CN1591818 A CN 1591818A
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- contact hole
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Abstract
The method for making double-mosaic opening structure includes the following steps: providing a semiconductor base with dielectric layer; making a first photoresist layer with contact hole opening pattern on said dielectric layer; making a sacrificial layer on said first photoresist layer and filling it into the above-mentioned contact hole opening pattern; making a second photoresist layer with internal line-connected opening pattern on the sacrificial layer, and making second photoresist layer expose the sacrificial layer positioned in upper portion of contact hole opening pattern; using second photoresist layer as cover curtain and etching sacrificial layer, and transferring the internal line-connected opening pattern into sacrificial layer; using second photoresist layer as cover curtain, successively etching first photoresist layer and dielectric layer, transferring the internal line-connected opening pattern into dielectric layer, etching said dielectric layer along the contact hole opening pattern so as to form a contact hole opening in dielectric layer.
Description
Technical field
The invention relates to a kind of method of making the semiconductor conducting element, particularly relevant for a kind of manufacture method of dual damascene formula hatch frame.
Background technology
Along with the increase of component density in the integrated circuit, the volume of element is more and more littler, the width of line is also more and more narrow, and is therefore also increasing for the demand of good circuit connection.Simultaneously, fast development along with the integrated circuit manufacturing, the back segment manufacturing enters deep-sub-micrometer element field, back segment is made (back-end-of-line, BEOL) more and more come into one's own, they have integrated more and more dual damascene (dual-damascene) intraconnections technology that contain the inlaying inner connecting line of contact hole embolism more, engage operation to carry out advanced metal interconnecting.Yet the RC that metal interconnecting caused postpones to have a strong impact on the speed of element operation.Improve material that method that RC postpones can adopt low-k (low-k dielectricmaterials) as the insulating barrier between the multiple layer metal intraconnections,, increase metal interconnecting density so as to reducing the parasitic capacitance size between the metal level; Another feasible method is to select the metal material of high conductivity for use.
Be enough to be applied on many elements even traditional intraconnections connects, yet integrated circuit for very high-density, it is unexpected high that the resistance of the per unit length of thin and long lead still can become, and makes the performance of circuit link component of high conductivity be restricted.
Aluminium can be used as desirable metal interconnecting on short and wide conductive characteristic, yet its resistance will be too high in the application of thin and long lead.In addition, tungsten is the Chang Zuowei metal interconnecting also, but on manufacturing technology, fills in the little dielectric layer contact hole tungsten but very difficult.
Early stage IC makes that to be reluctant to adopt copper be because the diffusion coefficient of copper is very high as the metal connecting line, its with can be diffused into base material very soon, the problem on generation deep layer energy rank after silicon or silicon dioxide contacts.Easily oxidation of copper itself in addition, easy at low temperatures and other material reaction, and copper lacks effective dry-etching technology, the development of these reason limit copper metals.But along with material and improvement of Manufacturing Technology, various diffusion barrier layers constantly are studied, and the success of inserted metallization process and chemomechanical copper grinding technology is solved these problems.
Based on above-mentioned restriction, known inserted metallization manufacturing is to use little shadow of twice and etch process, and to make the inserted metal interconnecting that contains the contact hole embolism, step is comparatively complicated, and between little shadow of twice and etch process, have the residual problem of photoresistance, cause manufacturing cost to increase.
Figure 1A, Figure 1B, Fig. 1 C, Fig. 1 D and Fig. 1 E have shown the manufacture method of known embedded intraconnection wire: shown in Figure 1A, the one semiconductor-based end 10 that is formed with the first metal layer 11, be provided, form one first dielectric layer 12 on the above-mentioned semiconductor-based end 10, form an etching stopping layer 13 afterwards on first dielectric layer 12.
Shown in Figure 1B, form one second dielectric layer 14 on etching stopping layer 13, form first photoresist layer 15 of tool contact hole patterns of openings then, and serve as cover curtain with first photoresist layer 15, second dielectric layer 14 of etching in regular turn, etching stopping layer 13 and first dielectric layer 12 are to form contact hole opening 16.
Shown in Fig. 1 C, then form second photoresist layer 17 of tool intraconnections patterns of openings, and serve as cover curtain with second photoresist layer 17, etching second dielectric layer 14 forms intraconnections opening 18 and dual damascene formula hatch frame 19.
Shown in Fig. 1 D and Fig. 1 E, form second metal level 20 on dielectric layer 14 and insert established contact hole opening 19 and intraconnections opening 18.With 20 planarizations of second metal level, the metal level that has more is polished, expose second dielectric layer 14, the dual damascene intraconnections of wanting with formation 21 that contains the contact hole embolism.
In above-mentioned conventional process, because contact hole opening and intraconnections are opened in the different etching steps and form, therefore need extra etching stopping layer, this etching stopping layer is that the material by high-dielectric coefficient is constituted, be formed between the dielectric layer, can cause the parasitic capacitance of inner layer dielectric layer to increase, and then make the RC of element when running postpone to increase.
United States Patent (USP) discloses the method that three kinds of formation contain the dual damascene formula metal interconnecting of contact hole embolism No. 6498092, is respectively: the etching of first contact hole opening, the etching of first intraconnections opening and contact hole opening and intraconnections opening be etching method simultaneously.Yet these three kinds of methods all need be used etching stopping layer, can't avoid the increase of parasitic capacitance between inner layer dielectric layer fully, and make the RC of element when running postpone to increase.
United States Patent (USP) also discloses a kind of method of the dual damascene formula metal interconnecting by the manufacturing of high conductivity metal material for No. 6271593, yet it has used multilayer dielectric layer to increase the complexity of making, and causes manufacturing cost to increase.Moreover its dielectric layer that utilizes high-dielectric coefficient also can't be avoided the element problem that RC postpones when running as etching stopping layer.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of dual damascene formula hatch frame, this manufacture method can be simplified manufacturing step, reduces manufacturing cost.
Another object of the present invention is to provide a kind of manufacture method of using the dual damascene formula metal interconnecting of dual damascene formula hatch frame of the present invention, can avoid the RC delay issue of element when running.
To achieve these goals, the manufacture method of dual damascene formula hatch frame of the present invention, comprise the following steps: to provide a semiconductor-based end that is formed with dielectric layer, form one afterwards and have first photoresist layer of contact hole patterns of openings on above-mentioned dielectric layer, and then form a sacrifice layer on first photoresist layer, and insert above-mentioned contact hole patterns of openings, form one and have second photoresist layer of intraconnections pattern on sacrifice layer, and second photoresist layer exposes the sacrifice layer of contact hole patterns of openings top, serve as cover curtain etch sacrificial layer with second photoresist layer again, so that the intraconnections patterns of openings is transferred to sacrifice layer.Serve as the cover curtain with second photoresist layer again, first photoresist layer of etching in regular turn and dielectric layer so that the intraconnections patterns of openings is transferred to dielectric layer, form an intraconnections opening, and along contact hole patterns of openings etching dielectric layer, in dielectric layer, to form the contact hole opening.Form a conductive layer at last on the dielectric layer that forms intraconnections patterns of openings and contact hole patterns of openings, and, expose dielectric layer, to form dual damascene formula hatch frame the conductive layer planarization.
The manufacture method of described dual damascene formula hatch frame, dielectric layer material are by comprising silicon dioxide (SiO
2), Pyrex (borosilicate glass; BSG), boron-phosphorosilicate glass (borophosphatesilicate glass; BPSG), fluorine doped-glass (fluorosilicate glass; FSG) or tetraethoxy silicate (tetraethyl-ortho-silicate; TEOS) wherein arbitrary single or multiple lift material is made.
The manufacture method of described dual damascene formula hatch frame, first and second photoresist layer are siliceous photoresistance (chemically amplified silicon resist), or deep UV photoresistance (DUV photoresist), also can be different photoresists.
The manufacture method of described dual damascene formula hatch frame, sacrifice layer are preferably by I-linear light resistance (I-line resist) or other material that is fit to and are constituted, for example non-photosensitive photoresistance (non-photosensitive resist).
The manufacture method of described dual damascene formula hatch frame by the ratio of described two photoresist layer etch-rates of etch process parameters modulation and sacrificial layer etching speed, is adjusted the degree of depth of intraconnections opening.
The manufacture method of described dual damascene formula hatch frame, when the etch sacrificial layer and first photoresist layer, the etch-rate of the etch-rate of this dielectric layer and first photoresist layer is suitable.
The manufacture method of described dual damascene formula hatch frame, the etch-rate of this sacrifice layer are than the etch-rate height of described two photoresist layers, and its etch-rate ratio is 5-15: 1.
The manufacture method of described dual damascene formula hatch frame, it further comprises the following steps: to form a conductive layer on this dielectric layer, and inserts in this contact hole opening and the intraconnections opening; And this conductive layer of planarization, expose inner layer dielectric layer, to form inserted metal interconnecting and contact hole embolism.
The manufacture method of described dual damascene formula hatch frame, this conductive layer be gold, copper, silver, aluminium, and tungsten is wherein arbitrary or its alloy material is made.
Beneficial effect of the present invention is: provide a kind of manufacture method of dual damascene formula hatch frame, to make the structure of the dual damascene formula metal interconnecting that contains the contact hole embolism.The present invention also provides the dual damascene formula metal interconnecting manufacture method of three layers of photoresistance of a kind of use in addition, can simplify manufacturing step, reduce manufacturing cost, simultaneously, the invention provides a kind of dual damascene formula metal interconnecting manufacture method that does not need etching stopping layer, can avoid the parasitic capacitance between dielectric layer to increase, and then reduce the delay that makes element RC when running.
Description of drawings
Figure 1A is the layout profile of known inserted metallization manufacture method;
Figure 1B is the layout profile of known formation contact hole opening;
Fig. 1 C is the layout profile that known formation contains the dual damascene formula opening of contact hole opening;
Fig. 1 D is that known formation second metal level is on dielectric layer and insert the layout profile of contact hole opening and intraconnections opening;
Fig. 1 E is the layout profile of the dual damascene formula metal interconnecting after the known planarization;
Fig. 2 A is the layout profile of the inserted metallization manufacture method of the formation of preferred embodiment of the present invention;
Fig. 2 B is the layout profile that formation of the present invention has first photoresist layer of contact hole patterns of openings;
Fig. 2 C is the layout profile of formation sacrifice layer of the present invention;
Fig. 2 D is the layout profile that formation of the present invention has second photoresist layer of intraconnections patterns of openings.
Fig. 2 E, Fig. 2 F and Fig. 2 G are the layout profiles that etching of the present invention has the intraconnections hatch frame of contact hole opening.
Fig. 2 H is the layout profile with intraconnections hatch frame of contact hole opening of the present invention;
Fig. 2 I is the layout profile of the dual damascene formula metal interconnecting after the planarization of the present invention.
Wherein, description of reference numerals is as follows:
10～semiconductor-based the end; 11～the first metal layer; 12～dielectric layer; 15～the first photoresist layers; 16～contact hole opening; 17～the second photoresist layers; 18～intraconnections opening; 19～dual damascene formula opening; 20～the second metal levels; 21～inserted metal interconnecting; 22～dual damascene formula metal interconnecting.
101～semiconductor-based the end; 102～the first metal layer; 103～dielectric layer; 104～the first photoresist layers; 105～contact hole patterns of openings; 106～sacrifice layer; The sacrifice layer of 106 '～contact hole patterns of openings; 107～intraconnections patterns of openings; 108～the second photoresist layers; E1, E2～reactive ion etching; 109～dual damascene formula opening; 110～intraconnections opening; 111～inserted metal interconnecting; 112～dual damascene formula metal interconnecting.
Embodiment
In Fig. 2 A, a semiconductor-based end 101 that is formed with the first metal layer 102, be provided, as a silicon base, can form any required semiconductor element on it, herein for simplicity, only with smooth substrate 101 expressions.Form a dielectric layer 103 then thereon.Wherein dielectric layer 103 can be by one or more layers dielectric material, as SiO
2, Pyrex (borosilicate glass; BSG), boron-phosphorosilicate glass (borophosphate silicate glass; BPSG), fluorine doped-glass (fluorosilicateglass; FSG) or tetraethoxy silicate (tetraethyl-ortho-silicate; TEOS) made.In other words, promptly as the inner layer dielectric layer (ILD) in the inserted metal interconnecting manufacturing.
Secondly, shown in Fig. 2 B, Fig. 2 C and Fig. 2 D, be coated with one first photoresist layer 104 (being siliceous photoresist layer 1 or DUV1), have first photoresist layer 104 of contact hole patterns of openings 105 on dielectric layer 103 through forming one behind the exposure imaging.Afterwards, form a sacrifice layer 106 (as I-linear light resistance layer) on first photoresist layer 104, and insert in the above-mentioned contact hole pattern 105.After this, be coated with one second photoresist layer 108 (being siliceous photoresist layer 2 or DUV2) again, through forming second photoresist layer 108 with intraconnections pattern 107 behind the exposure imaging on sacrifice layer 106, and second photoresist layer 108 exposes the sacrifice layer 106 of interlayer hole pattern below.
According to a better embodiment of the present invention, first and second photoresist layer is siliceous photoresistance or deep UV photoresist layer, and the thickness of first and second photoresist layer is respectively 1000～5000 , and first and second photoresist layer can also be different photoresists.On the other hand, sacrifice layer is preferably by I-linear light resistance material and is constituted, its thickness is 4000～12000 , or by the etch-rate that the meets sacrifice layer material higher than the etch-rate of first photoresist layer, for example non-photosensitive photoresistance (non-photosensitive resist) material.
Shown in Fig. 2 E, serve as the cover curtain with second photoresist layer 108 again, with anisotropic (anisotropic) etching manufacture, as reactive ion etching (RIE) mode or electric paste etching mode, the preferably is reactive ion etching (RIE) mode E1, etch sacrificial layer 106, select the etching condition of the rate of etch of sacrifice layer 106 far above second photoresist layer, 108 rate of etch, its speed ratio is 5-15: 1, so that intraconnections patterns of openings 107 is transferred on the sacrifice layer 106, because sacrifice layer 106 rate of etch are far above the rate of etch of second photoresist layer 108, by the time of controlling etching (over etching), the sacrifice layer 106 ' in the contact hole pattern 105 is very fast etched and expose dielectric layer 103.
Shown in Fig. 2 F, with second photoresist layer 108 is the cover curtain, by reactive ion etching (RIE) processing procedure E2 first photoresist layer 104 of etching in regular turn and dielectric layer 103, the rate of etch of selection sacrifice layer 106 is equivalent to the etching condition of second photoresist layer, 108 rate of etch, etching first photoresist layer 104 and dielectric layer 103.Because of first photoresist layer 104 and the suitable etch-rate of second photoresist layer, 108 tools, when second photoresist layer 108 also etched and when exposing sacrifice layer 106, intraconnections patterns of openings 107 can be transferred to first photoresist layer 104, and along contact hole patterns of openings 105 etching dielectric layers 103.
Shown in Fig. 2 G, with sacrifice layer 106 is the cover curtain, by reactive ion etching (RIE) mode etching dielectric layer 103, select dielectric layer 103 rate of etch to be higher than the etching condition of first photoresist layer, 104 rate of etch, so that intraconnections patterns of openings 107 is transferred to dielectric layer 103, and continue along contact hole patterns of openings 105 etching dielectric layers 103, till the first metal layer 102 that exposes bottom, in dielectric layer 103, to form a contact hole opening 109.Remove the sacrifice layer 106 and first photoresist layer 104 then, to form dual damascene formula hatch frame.
Shown in Fig. 2 I, with galvanoplastic, evaporation (evaporation) method, sputter (sputtering) method, or Metalorganic chemical vapor deposition (MOCVD) method, the preferably is galvanoplastic, deposit one second conductive layer, as gold, copper, silver, aluminium, and the wherein arbitrary or alloy material of tungsten, the preferably is a copper, on the dielectric layer 103 that forms tool contact hole opening 109 and intraconnections opening 110, and insert in contact hole opening 109 and the intraconnections opening 110, second conductive layer being imposed planarization makes again, until exposing dielectric layer, contain the dual damascene formula metal interconnecting 111 of contact embolism 112 with formation.
It is to lose back production method or cmp (CMP) production method that above-mentioned planarization is made.
By the better embodiment of the invention described above as can be known, the manufacture method of a kind of manufacture method of dual damascene formula hatch frame and dual damascene formula metal interconnecting thereof has the making step of simplifying, can reduce manufacturing cost, and the degree of depth of metal interconnecting can be by the ratio of two photoresist layer etch-rates of etch process parameters modulation and sacrificial etch speed, perhaps adjust the degree of depth of intraconnections opening, to reach optimization by the thickness of first photoresist layer.
The present invention also provides a kind of dual damascene formula intraconnections manufacture that does not need etching stopping layer in addition, can avoid the parasitic capacitance between dielectric layer to increase, and then reduces the RC delay of element when running.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing to change and retouching, so protection scope of the present invention is when looking being as the criterion that the accompanying Claim book defined.
Claims (10)
1. the manufacture method of a dual damascene formula hatch frame comprises the following steps:
The one semiconductor-based end that is formed with dielectric layer, be provided; It is characterized in that:
Form one and have first photoresist layer of contact hole patterns of openings on this dielectric layer;
Form a sacrifice layer on this first photoresist layer, and insert in the above-mentioned contact hole patterns of openings;
Form second photoresist layer with intraconnections patterns of openings on this sacrifice layer, and this second photoresist layer manifests the sacrifice layer of this contact hole patterns of openings top;
With this second photoresist layer is this sacrifice layer of cover curtain etching, so that this intraconnections patterns of openings is transferred to sacrifice layer; And
With this second photoresist layer is the cover curtain, this first photoresist layer of etching in regular turn and this dielectric layer so that this intraconnections patterns of openings is transferred to this dielectric layer, form the intraconnections opening, and along this this dielectric layer of contact hole patterns of openings etching, in this dielectric layer, to form the contact hole opening.
2. the manufacture method of dual damascene formula hatch frame as claimed in claim 1 is characterized in that: dielectric layer is made by the wherein arbitrary single or multiple lift material of silicon dioxide, Pyrex, boron-phosphorosilicate glass, fluorine doped-glass and tetraethoxy silicate.
3. the manufacture method of dual damascene formula hatch frame as claimed in claim 1 is characterized in that: first and second photoresist layer is siliceous photoresistance or deep UV photoresistance.
4. the manufacture method of dual damascene formula hatch frame as claimed in claim 1 is characterized in that: first and second photoresist layer is different photoresist.
5. the manufacture method of dual damascene formula hatch frame as claimed in claim 1 is characterized in that: sacrifice layer is made of I-linear light resistance material or non-photosensitive photoresist.
6. the manufacture method of dual damascene formula hatch frame as claimed in claim 1 is characterized in that: by the ratio of described two photoresist layer etch-rates of etch process parameters modulation and sacrificial layer etching speed, adjust the degree of depth of intraconnections opening.
7. the manufacture method of dual damascene formula hatch frame as claimed in claim 1 is characterized in that: when the etch sacrificial layer and first photoresist layer, the etch-rate of the etch-rate of this dielectric layer and first photoresist layer is suitable.
8. the manufacture method of dual damascene formula hatch frame as claimed in claim 1 is characterized in that: the etch-rate of this sacrifice layer is than the etch-rate height of described two photoresist layers, and its etch-rate ratio is 5-15: 1.
9. the manufacture method of dual damascene formula hatch frame as claimed in claim 1, it is characterized in that: it further comprises the following steps:
Form a conductive layer on this dielectric layer, and insert in this contact hole opening and the intraconnections opening; And
This conductive layer of planarization exposes inner layer dielectric layer, to form inserted metal interconnecting and contact hole embolism.
10. the manufacture method of dual damascene formula hatch frame as claimed in claim 9 is characterized in that: this conductive layer is gold, copper, silver, aluminium, and tungsten is wherein arbitrary or its alloy material is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03156045 CN1282237C (en) | 2003-08-29 | 2003-08-29 | Method for making double inserted open structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03156045 CN1282237C (en) | 2003-08-29 | 2003-08-29 | Method for making double inserted open structure |
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| Publication Number | Publication Date |
|---|---|
| CN1591818A true CN1591818A (en) | 2005-03-09 |
| CN1282237C CN1282237C (en) | 2006-10-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 03156045 Expired - Fee Related CN1282237C (en) | 2003-08-29 | 2003-08-29 | Method for making double inserted open structure |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100420009C (en) * | 2005-08-15 | 2008-09-17 | 台湾积体电路制造股份有限公司 | Semiconductor device and open structure of semiconductor device |
| CN100419995C (en) * | 2005-12-13 | 2008-09-17 | 台湾积体电路制造股份有限公司 | Dual-damascene process |
| CN101459119B (en) * | 2007-12-13 | 2010-11-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| CN101131928B (en) * | 2006-08-21 | 2011-11-02 | 兰姆研究有限公司 | Method of forming double inlay feature in porous low-k dielectric layer |
| CN103579116A (en) * | 2012-08-10 | 2014-02-12 | 南亚科技股份有限公司 | Method for manufacturing multiple grooves in substrate |
| CN113782486A (en) * | 2020-06-10 | 2021-12-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
-
2003
- 2003-08-29 CN CN 03156045 patent/CN1282237C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100420009C (en) * | 2005-08-15 | 2008-09-17 | 台湾积体电路制造股份有限公司 | Semiconductor device and open structure of semiconductor device |
| CN100419995C (en) * | 2005-12-13 | 2008-09-17 | 台湾积体电路制造股份有限公司 | Dual-damascene process |
| CN101131928B (en) * | 2006-08-21 | 2011-11-02 | 兰姆研究有限公司 | Method of forming double inlay feature in porous low-k dielectric layer |
| CN101459119B (en) * | 2007-12-13 | 2010-11-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| CN103579116A (en) * | 2012-08-10 | 2014-02-12 | 南亚科技股份有限公司 | Method for manufacturing multiple grooves in substrate |
| CN113782486A (en) * | 2020-06-10 | 2021-12-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113782486B (en) * | 2020-06-10 | 2024-02-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| Publication number | Publication date |
|---|---|
| CN1282237C (en) | 2006-10-25 |
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