CN1589030A - Super large scale integrated circuit system structure of moving estimation and data buffer storage method - Google Patents
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Abstract
This invention relates to a system and a process procedure realized by data buffer storage super large scale IC in multisize multimode motion estimation of digital video signal encode including two super high speed buffer storage capable of addressing independently for storing the processed data in the current and reference frames. The data exchange among the high speed buffer storage, the external storage and a motion evaluator takes the 4x4 data block as the basic unit. The invention puts forward a method for supporting the supply of high speed data necessary for estimation from 4x4 to 16x16 various modes motions.
Description
Affiliated technical field
The invention belongs to the electron trade technical field, be specifically related to a kind of super large scale integrated circuit system structure, and metadata cache and the method that provides when carrying out multiple dimensioned multi-mode estimation in this integrated circuit.
Background technology
Fig. 1 is to be estimation (Motion Estimation, functional schematic ME) of unit with the piece in the general video coding.The method of estimation is that to block of pixels that is encoded in the current frame image, search differs minimum block of pixels with it in the window of an appointment in reference frame image, as optimum Match.Estimation obtains two values: the skew that is the block of pixels that is encoded with respect to optimum Match block of pixels in the reference frame, i.e. a motion vector MV (Motion Vector); Another is the residual absolute value sum SAD between block of pixels and the optimum Match pixel of being encoded.This part calculating has accounted for the very big proportion of whole cataloged procedure amount of calculation, and therefore, whether effectively the execution efficient of this part hardware be directly connected to the operation of whole integrated circuit (IC) chip.
Fig. 2 is the H.264/MPEG-4 functional schematic of estimation in the AVC standard of ITU-T.In this standard, there is the block of pixels of seven kinds of different sizes and shape to be used to estimation.
Estimation is occupied considerable status in the whole video cataloged procedure, also occupied a large amount of processor resources, especially in H.264, introduced the motion estimation techniques of various patterns of from 4 * 4 to 16 * 16 various yardsticks, further increased the amount of calculation and the complexity of estimation, therefore the quick execution for motion estimation process is an essential condition that realizes H.264 real-time coding.
Simultaneously, because the asynchronous development between technological improvement, commercialization and the standardisation process three has formed the situation that multiple coding standard coexists in the field of video encoding.Therefore, on same computing platform, be necessary to the support that comprises MPEG-1/2/4 and multiple digital video coding standard H.264.
Summary of the invention
An object of the present invention is to provide a kind of super large scale integrated circuit system structure, for the quick execution of motion estimation process provides a kind of hardware configuration.
A kind of super large scale integrated circuit system structure, be used for encoding digital video signals motion-estimation step data cache and provide, it is characterized in that comprising:
A current frame data buffer;
A reference frame data buffer;
Data channel between current frame data buffer and the external memory storage;
Data channel between reference frame data buffer and the external memory storage;
Data channel between current frame data buffer and the multimode exercise estimator;
Data channel between reference frame data buffer and the multimode exercise estimator.
Wherein the institutional framework of data buffer is:
Data buffer is divided into four physical bodies;
Each physical bodies comprises the cache line (CACHE LINE) of some;
The size of each cache line is 16 bytes, is divided into the word of 4 nybbles;
Each cache line has a sign (TAG) field.
Wherein the multimode exercise estimator is by four duplicate processing unit PE-A of internal structure (302), PE-B (303), and PE-C (304), and PE-D (305) forms.
Another object of the present invention provide a kind of in this super large scale integrated circuit system structure metadata cache and the method that provides, the quick execution of motion estimation process is achieved.
This method may further comprise the steps:
The stored partial pixel data of external memory storage are called in the data cache device;
The controller access high-speed memory carries out addressing to present frame and reference frame data;
Present frame and reference frame data are called in the multimode exercise estimator carry out estimation.
Wherein the mapping method between the stored pixel data of data buffer and external memory storage comprises:
Pixel data is that base unit is done whole moving between data cache device and external memory storage with 4 * 4 block of pixels;
Once the data between data cache device and external memory storage move, and also comprise three association 4 * 4 block of pixels, lay respectively at right side, downside, and the lower right side of above-mentioned 4 * 4 block of pixels;
From external memory storage when the data cache device is called in data, in the identical cache line (CACHE LINE) of the numbering that one 4 * 4 block of pixels and three association 4 * 4 block of pixels thereof are assigned to four different physical bodies in the same data cache device respectively.
The mapping method that wherein carries out the pixel data exchange between data buffer and the multimode exercise estimator comprises:
Pixel data is that base unit is done whole moving between data cache device and multimode exercise estimator with 4 * 4 block of pixels;
All processing unit PE-A in the multimode exercise estimator, PE-B, PE-C, PE-D obtain the current frame pixel data from same present frame data cache device jointly;
All processing unit PE-A in the multimode exercise estimator, PE-B, PE-C, PE-D obtain the reference frame pixel data from same reference frame high speed data buffer jointly.
Wherein the addressing method of data cache device comprises:
Its row index of the position calculation of 4 * 4 block of pixels in original image and the row index of searching by needs;
Determine the row index and the row index of three related 4 * 4 block of pixels by the row index of above-mentioned 4 * 4 block of pixels and row index;
Row index and row index by 4 * 4 block of pixels are united buffer address and the TAG matched signal that forms the data cache device;
Judge with the TAG matched signal whether the data in the cache line are desired 4 * 4 block of pixels;
If the data in the cache line are not desired 4 * 4 block of pixels, this 4 * 4 block of pixels and associated pixel blocks of data are called in Cache and revised the TAG value from external memory storage.
In described very lagre scale integrated circuit (VLSIC) and metadata cache and the method that provides, can there be L reference frame high speed buffer to come respectively the data of L reference frame to be carried out buffer memory.
In described very lagre scale integrated circuit (VLSIC) and metadata cache and the method that provides, when L reference frame high speed buffer, controller at first produces one and selects signal, and one of selection is operated from L Cache.
The present invention did at the motion-estimation step in the calculation processes such as digital video and image encoding, transcoding, and special-purpose very lagre scale integrated circuit (VLSIC) Parallel Implementation structure, make and can support to comprise H.264 all MPEG/ITU-T class standard H.26x of the AVS standard of (being MPEG-4 the 10th part) standard and China of up-to-date ITU-T based on the multimode asic chip group of new generation of its exploitation.The scope of application contains a plurality of industrial fields that comprise Digital Television, the network media, information household appliances, multimedia mobile communication, videodisc etc.
Description of drawings
Fig. 1 is to be estimation (Motion Estimation, functional schematic ME) of unit with the piece in the general video coding;
Fig. 2 is the H.264/MPEG-T functional schematic of estimation in the AVC standard of ITU-T;
Fig. 3 is a super large scale integrated circuit system structure of the present invention;
Fig. 4 is the institutional framework of the present invention's one specific embodiment high speed buffer;
Fig. 5 is that the current frame image data are deposited strategy in a cache line;
Fig. 6 is the allocation strategy of the part of a frame current frame video image when being stored in the Cache;
Fig. 7 is the addressing method of present frame Cache in the present invention's one specific embodiment;
Control logic flow process when Fig. 8 is the controller access high-speed memory;
Fig. 9 is the addressing method of reference frame high speed buffer in the present invention's one specific embodiment;
Figure 10 is the addressing method of multi-reference frame situation Cache.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are described in further detail.
Fig. 3 is a super large scale integrated circuit system structure of the present invention, is an energy to from 4 * 4,4 * 8,8 * 4,8 * 8,8 * 16,16 * 8, carry out the parallel device of estimation to the block of pixels of various geometries such as 16 * 16 and size.If it is repeated to use more number of times, it also can carry out estimation to the block of pixels greater than 16 * 16.
The behavior of whole device is controlled by a controller (301).Operational order (308) decision of sending by controller is defended in initiation of calculating and operator scheme choosing.The core component of device is by four duplicate processing unit PE-A of internal structure (302), PE-B (303), PE-C (304), and the multimode exercise estimator of PE-D (305) composition.Each PE can independently finish the estimation of the block of pixels of one 4 * 4 size, one group of motion vector MV-A consequently, MV-B, MV-C, MV-D and corresponding residual absolute value and SAD-A, SAD-B, SAD-C, SAD-D.These motion vectors and residual absolute value and be sent to controller (301) and do further processing.Four PE also have data path and control access interconnected (310), make them can work in coordination with the estimation of finishing than 4 * 4 bigger block of pixels.
Whole multimode exercise estimator provides the input data by a current frame data CACHE (306) and reference frame search window data CACHE (307), and these data are directed to respectively among four PE.Because four PE are when being ME, data have certain correlation, and promptly the search window of 4 PE has certain overlapping.Therefore, the shared identical cover CACHE device of these four PE.
The same with most of calculation elements, CACHE device among the present invention is that data access (reading and writing) speed is higher than external memory storage (311 far away, 312), capacity is far smaller than external memory storage, and in general manufacturing cost (unit/bit) is higher than the cache portion of external memory storage.It is the parts that data directly are provided to the multimode exercise estimator, and the more images data are stored externally in the memory (311,312).Between external memory storage and the CACHE data exchange channel is arranged, but do not have direct data exchange channel between external memory storage and the multimode exercise estimator.
Fig. 4 is the institutional framework of a specific embodiment high speed buffer of the present invention.The CACHE size of depositing current frame data is divided into four individualities for 8K (1K=1,024) byte (Byte, 1 byte=8 a binary digit bit), and each body is 2K Bytes.Each body has 128 CACHE LINE, and the size of each CACHE LINE is 16 bytes, is divided into the word of 4 nybbles.In addition, each CACHE LINE also has a TAG (sign) field.The TAG field is not used for depositing view data, but controller is used for a control field to the CACHE data access.In a specific implementation example, the length of TAG field is 11 binary digits.
The aufbauprinciple that it may be noted that Fig. 4 can have different specific implementations, and for example, total size of CACHE can be greater than or less than 8K, and the body number in the CACHE can be four, the numeral that the size of each body and CACHE LINE number needn't provide for Fig. 4, or the like.Principle of the present invention is applicable to all these variations.
Figure 5 shows that the current frame image data are that base unit leaves among the CACHE with 4 * 4 block of pixels in the present invention.According to this design, no matter be that view data is called in CACHE from external memory storage, or the view data among the CACHE called in the multimode exercise estimator and participated in the estimation computing, be that whole unit carries out all with 4 * 4 block of pixels.Fig. 5 and show that one 4 * 4 block of pixels deposits strategy in a CACHE LINE, wherein four brightness values of first row of this 4*4 block of pixels deposited in first word of each CACHE LINE (4 bytes); Four brightness values of second row of this 4*4 block of pixels deposited in second word; Four brightness values of the third line of this 4*4 block of pixels deposited in the 3rd word; Four brightness values of the fourth line of this 4*4 block of pixels deposited in the 4th word.
Allocation strategy when the part that Figure 6 shows that a frame current frame video image is stored among the CACHE.As Fig. 6 A, the view data that is assigned with is split into some 4 * 4 block of pixels from the pixel in the upper left corner.We wherein are followed successively by 0th, the 1 from several topmost with the row-coordinate of each 4 * 4 block of pixels of index i mark ... or the like; Row coordinate with each 4 * 4 block of pixels of index j mark is followed successively by the 0th, the 1 from the Far Left number ... or the like.Therefore, in the frame video image coordinate of one 4 * 4 block of pixels in the upper left corner be (i, j)=(0,0), or the like.
The present invention at a specific implementation in, the maximum that we establish index i and j is 1023.Therefore, index i and j respectively can represent with ten binary digits respectively.The manageable maximum image of She Ji device is of a size of 4096 * 4096 pixels like this.When this principle and device were used to handle bigger image, a figure place that only needs to increase index i and/or j got final product.
Allocation rule when current frame image is stored among the CACHE is, the first, and from the pixel in the upper left corner, brightness data is that unit is assigned among the CACHE with 4 * 4 block of pixels; Second, the 0th individuality of CACHE is always deposited i, the j index is the 4*4 block of pixels of even number, it is even number that the 1st individuality is always deposited the i index, the j index is the 4*4 block of pixels of odd number, and it is odd number that the 2nd individuality is always deposited the i index, and the j index is the 4*4 block of pixels of even number, the 3rd individuality is always deposited i, and the j index is the 4*4 block of pixels of odd number.
Fig. 6 B has provided a specific implementation of this rule.As can be seen, according to such allocation rule, count from the upper left corner of image, four 4*4 block of pixels forming each 8 * 8 block of pixels just are assigned to respectively in four CACHE bodies.In fact, count from the upper left corner of image, four 4*4 block of pixels forming each 8 * 8 block of pixels are called as related 4*4 block of pixels, shown in Fig. 6 C.
Allocation rule according to Fig. 6 shows at the specific implementation among Fig. 4, can have 512 4*4 block of pixels to be assigned among the current frame data CACHE simultaneously.
Figure 7 shows that controller (301) carries out addressing to the 4*4 block of pixels that leaves in the present frame among the CACHE.According to the design of Fig. 5, each externally between memory and the CACHE and between CACHE and the multimode exercise estimator base unit of exchanges data be a 4*4 block of pixels, therefore, the base unit that is addressed among the CACHE is a CACHE LINE.
When controller will be sought one 4 * 4 block of pixels among the CACHE, it need provide two indexs, and one is the row index i (701) of this 4 * 4 block of pixels, and another is the row index j (702) of this 4 * 4 block of pixels.Wherein, constitute an individual choice signal (703) jointly, be used for selecting one in four individualities in CACHE by the 0th of row index and row index the 0th.Select signal (704) by the 1st, 2 of row index and the 1st to 5 common formation one individual interior CACHE LINE of row index, be used in selected CACHE body, specifying a CACHE LINE.TAG field and 4 * 4 block of pixels of CACHE LINE (706) in this selected CACHE body are read respectively.At last, constitute a TAG matched signal (705) jointly, be used for judging 4 * 4 block of pixels data (708) that are read out whether effectively (by a comparator 707) by the 3rd to 9 of row index and row index the 6th to 9.If the TAG information that is read out equates that with TAG matched signal 705 4 * 4 block of pixels that then are read out are exactly the data (hitting) that will look for.If TAG information that is read out and TAG matched signal 705 are unequal, 4 * 4 block of pixels that then are read out are not the data that will look for, are invalid data.
Control logic flow process when Figure 8 shows that controller access CACHE.When controller will be sought one 4 * 4 block of pixels among the CACHE, its needed to determine earlier the row index and the row index of this block of pixels.Fig. 8 (B) display line index and row index respectively with pixel-matrix coordinate (R, relation C).One width of cloth digitized image is divided into several rows (horizontal direction is used the R mark) and row (vertical direction is used the C mark), and the coordinate of the pixel in the wherein upper left corner is R=0, C=0.If the coordinate of the top left corner pixel of current 4 * 4 block of pixels that are considered for (R, C), the algorithm that provides according to Fig. 8 (A) then, the row, column index that can determine this 4 * 4 block of pixels is i=R/4 and j=C/4, here "/" symbology division.
For example, if the coordinate of the top left corner pixel of current 4 * 4 block of pixels that are considered is that (R=8, C=16), then the row, column index of this 4 * 4 block of pixels is respectively i=2 and j=4.
Next, controller need be determined the row, column index (Fig. 8 (A)) of other three associated pixel pieces.For example, if the row, column index of 4 * 4 block of pixels of current 4 * 4 block of pixels that are considered is respectively i=2 and j=4, then the associated pixel piece index on the right with its next-door neighbour is i=2 and j=5, with its next-door neighbour's the associated pixel piece index of bottom be i=3 and j=4, the bottom-right associated pixel piece index that is close to it is i=3 and j=5, or the like.
Next, controller will be according to (i, j) value according to the method for Fig. 7, are taken out required block of pixels data in CACHE.If the data of looking for just (hit) in CACHE, then control flow enters next procedure (for example, asking in the estimation computings such as difference).If the data of looking for are in CACHE, then controller is called in CACHE with relevant data from external memory storage.Calling in the deposit position of data in CACHE calculates by the rule of Fig. 7.Disposable data of being called in comprise the data of these 4 * 4 block of pixels and the data of other three 4 * 4 block of pixels that are associated.Simultaneously, the TAG value of relevant CACHE LINE is recomputated and is reset.Then, control flow enters next procedure (for example, asking in the estimation computings such as difference).
What reference frame CACHE deposited is the data of search window in the reference frame.It is identical with present frame that it deposits strategy, that is: (1) is base unit with 4 * 4 block of pixels.(2) each 4 * 4 block of pixels has a unique correspondence (i, j) index is pressed the computational methods of Fig. 8 (B) and determined by the coordinate of its top left corner pixel in reference frame.(3) the CACHE institutional framework of reference frame is identical with Fig. 4, and just total capacity is big four times: with the local data that 4 CACHE bodies are deposited reference frame, the size of each body is the 8K byte, 16 bytes of each CACHE behavior, and it is capable that each body has 512 CACHE.(4) the 0th individuality of CACHE is always deposited i, the j index is the reference frame 4*4 block of pixels of even number, it is even number that the 1st individuality is always deposited the i index, the j index is the reference frame 4*4 block of pixels of odd number, it is odd number that the 2nd individuality is always deposited the i index, the j index is the reference frame 4*4 block of pixels of even number, and the 3rd individuality is always deposited i, and the j index is the reference frame 4*4 block of pixels of odd number.(5) when the 4*4 of needs block of pixels is not in CACHE, to be unit with 8 * 8 block of pixels call in CACHE with needed 4*4 block of pixels and three 4*4 block of pixels being associated thereof from external memory storage to control logic.
Figure 9 shows that the addressing process of reference frame CACHE: the 0th of the i coordinate and j coordinate the 0th selects signal as body; The 1st to the 4th of the i coordinate and j coordinate the 1st to the 5th selects signal as CACHE LINE in the body: the 5th to the 9th of the i coordinate and j coordinate the 6th to the 9th as the TAG matched signal.
Figure 10 shows that when a plurality of reference frame (for example, the B-frame prediction among the MPEG-2 and H.264 in the multiframe reference prediction), the tissue of CACHE and addressing.Wherein, if L reference frame arranged, then there is L to resemble the CACHE that Fig. 9 provides in the device and comes respectively the data of this L reference frame to be carried out buffer memory.Each CACHE has 4 CACHE bodies, and each individuality has 512 CACHE LINE, and each CACHE LINE can store the brightness data of one 4 * 4 block of pixels.When visit reference frame CACHE, controller at first produces the CACHE selection signal (1000) that a width is at least (log 2L) position, comes to select from L CACHE a CACHE to carry out following operation.After a CACHE was selected, ensuing addressing operation was the same with Fig. 9.
It may be noted that at last disclosed treatment principle and structural design can have many variations, but these variations do not constitute to material alteration of the present invention.For example, call in the process of data to the CACHE from external memory storage among Fig. 8, be not limited to the rule of " disposable data of being called in comprise the data of this 4 * 4 block of pixels and the data of other three 4 * 4 block of pixels of being associated ", be applicable to that also other data call in strategy.In addition, can all not open up a CACHE during multi-reference frame for each reference frame yet, but 4 CACHE bodies among all shared CACHE of all reference frames.At this moment only need do simple the processing to the Tag position gets final product.
At last, though the method that the present invention proposes proposes at the video signal coding process, it is equally applicable to other processing and analytic process to vision signal, motion prediction for example, and motion analysis, motion tracking, or the like.
Claims (9)
1, a kind of super large scale integrated circuit system structure of estimation, be used for encoding digital video signals motion-estimation step data cache and provide, it is characterized in that comprising:
A) current frame data buffer;
B) reference frame data buffer;
C) data channel between current frame data buffer and the external memory storage;
D) data channel between reference frame data buffer and the external memory storage;
E) data channel between current frame data buffer and the multimode exercise estimator;
F) data channel between reference frame data buffer and the multimode exercise estimator.
2, the super large scale integrated circuit system structure of estimation according to claim 1 is characterized in that the institutional framework of data buffer is:
A) data buffer is divided into four physical bodies;
B) each physical bodies comprises the cache line (CACHE LINE) of some;
C) size of each cache line is 16 bytes, is divided into the word of 4 nybbles;
D) each cache line has a sign (TAG) field.
3, according to the super large scale integrated circuit system structure of the described estimation of claim 1, it is characterized in that the multimode exercise estimator is by four duplicate processing unit PE-A of internal structure (302), PE-B (303), PE-C (304), and PE-D (305) forms.
4, the method that is used for the super large scale integrated circuit system structure metadata cache of the described estimation of claim 1 is characterized in that this method may further comprise the steps:
A) the stored partial pixel data of external memory storage are called in the data cache device;
B) the controller access high-speed memory carries out addressing to present frame and reference frame data;
C) present frame and reference frame data are called in the multimode exercise estimator and carry out estimation.
5, the method for metadata cache according to claim 4 is characterized in that the mapping method between the stored pixel data of data buffer and external memory storage comprises:
A) pixel data is that base unit is done whole moving between data cache device and external memory storage with 4 * 4 block of pixels;
B) once the data between data cache device and external memory storage move, and also comprise three association 4 * 4 block of pixels, lay respectively at right side, downside, and the lower right side of above-mentioned 4 * 4 block of pixels;
C) from external memory storage when the data cache device is called in data, in the identical cache line (CACHE LINE) of the numbering that one 4 * 4 block of pixels and three association 4 * 4 block of pixels thereof are assigned to four different physical bodies in the same data cache device respectively.
6, the method for metadata cache according to claim 4 is characterized in that the mapping method that carries out the pixel data exchange between data buffer and the multimode exercise estimator comprises:
A) pixel data is that base unit is done whole moving between data cache device and multimode exercise estimator with 4 * 4 block of pixels;
B) all processing unit PE-A in the multimode exercise estimator, PE-B, PE-C, PE-D obtain the current frame pixel data from same present frame data cache device jointly;
C) all processing unit PE-A in the multimode exercise estimator, PE-B, PE-C, PE-D obtain the reference frame pixel data from same reference frame high speed data buffer jointly.
7, the method for metadata cache according to claim 4 is characterized in that the addressing method of data cache device comprises:
A) its row index of the position calculation of 4 * 4 block of pixels in original image and the row index of searching by needs;
B) determine the row index and the row index of three related 4 * 4 block of pixels by the row index of above-mentioned 4 * 4 block of pixels and row index;
C) unite buffer address and the TAG matched signal that forms the data cache device by the row index and the row index of 4 * 4 block of pixels;
D) judge with the TAG matched signal whether the data in the cache line are desired 4 * 4 block of pixels;
E) if the data in the cache line are not desired 4 * 4 block of pixels, this 4 * 4 block of pixels and associated pixel blocks of data are called in Cache and revised the TAG value from external memory storage.
8,, it is characterized in that having L reference frame high speed buffer to come respectively the data of L reference frame to be carried out buffer memory according to the super large scale integrated circuit system structure of claim 1,4 described estimation and the method for metadata cache.
9, the method for the super large scale integrated circuit system structure of estimation according to claim 7 and metadata cache, it is characterized in that when L reference frame high speed buffer, controller at first produces one and selects signal, selects one and operate from L Cache.
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| CN101543069B (en) * | 2006-11-30 | 2012-07-04 | Lsi公司 | Memory reduced H264/MPEG-4AVC codec |
| CN103067709A (en) * | 2011-12-30 | 2013-04-24 | 诸城市新东方汽车仪表有限责任公司 | Cache structure used for video compression motion estimation |
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| CN108737833A (en) * | 2018-05-25 | 2018-11-02 | 珠海市杰理科技股份有限公司 | Data buffering method, system, computer equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100339976C (en) * | 2004-08-09 | 2007-09-26 | Thomson宽带研发（北京）有限公司 | Multiple mold multiple scale movement evaluation super large scale integrated circuit system structure and method |
| CN101543069B (en) * | 2006-11-30 | 2012-07-04 | Lsi公司 | Memory reduced H264/MPEG-4AVC codec |
| CN102369552B (en) * | 2009-01-12 | 2014-11-05 | 布瑞科技股份有限公司 | Memory subsystem |
| CN103067709A (en) * | 2011-12-30 | 2013-04-24 | 诸城市新东方汽车仪表有限责任公司 | Cache structure used for video compression motion estimation |
| CN108737833A (en) * | 2018-05-25 | 2018-11-02 | 珠海市杰理科技股份有限公司 | Data buffering method, system, computer equipment and storage medium |
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