CN1588269A - Power source management state control method - Google Patents
Power source management state control method Download PDFInfo
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- CN1588269A CN1588269A CN 200410068756 CN200410068756A CN1588269A CN 1588269 A CN1588269 A CN 1588269A CN 200410068756 CN200410068756 CN 200410068756 CN 200410068756 A CN200410068756 A CN 200410068756A CN 1588269 A CN1588269 A CN 1588269A
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Abstract
This invention is a power supply supervisor status control method which is used in a computer system. The computer system contains a CPE, a north bridge chip, a south bridge chip and a peripheral unit joined with the north bridge chip. The CPE prepares to go into a electricity-saving mode for a stop time pulse signal sent out by the south bridge chip; after the CPE finishes the preparation it sends out a stop leaving signal to the north bridge chip; for the stop leaving signal the north bridge chip makes the peripheral unit go into a corresponding peripheral unit power supply supervisor status; the north bridge chip sends out the stop leaving signal to the south bridge chip and the south bridge chip makes the computer system go into a corresponding system power supply supervisor status for the received signal.
Description
Technical field
The present invention is a kind of look-at-me control system and control method, refers to especially be provided with and the look-at-me control system and the control method that are applied in the computer system.
Background technology
See also Fig. 1, it is the computer system functions synoptic diagram of a utilization high-speed peripheral control unit interface bus protocol (PCI ExpressProtocol), it is mainly by CPU (central processing unit) 10, north bridge chips 11, South Bridge chip 12, power supply 13 and a plurality of high-speed peripheral control unit interface bus peripheral unit 140,141,142,143,144 (hereinafter to be referred as PCI Express assembly 140,141,142,143,144), and north bridge chips 11 is control center's (english term is called root complex) of whole high-speed peripheral control unit interface bus system, is linked and all link (Express Link) fast by one between each PCI Express assembly and control center.
See also Fig. 2 again, it is the process flow diagram that control aforementioned calculation machine system carries out power supply managing, at first, operating on operating system on the computer system utilizes a power management to export to write circulation that the power management I/O port in the South Bridge chip 12 (Power Management I/O Port) 121 is carried out data to write, and then startup power management states S1, S3, one of among S4 or the S5, and when receiving after these data write circulation, Power Management Unit 120 in the South Bridge chip 12 is just sent one and is stopped clock signal (STPCLK) to this CPU (central processing unit) 10, and after CPU (central processing unit) 10 receives that this stops clock signal (STPCLK), when if this CPU (central processing unit) 10 has been ready to enter battery saving mode, just this CPU (central processing unit) 10 can be sent the instruction cycle of a suspension of licence (STPGNT cycle) again and transmit by the commentaries on classics of north bridge chips 11 and to notify this South Bridge chip 12.And when this South Bridge chip 12 is received the instruction cycle of suspension of licence (STPGNT cycle), just can send the SUSB signal of representing sleep state S3, or send the SUSB signal of representing sleep state S4 or S5 and the combination of SUSC signal, and power supply 13 just comes the power supply of some assembly in the halt system in response to the combination of SUSB signal or SUSB signal and SUSC, with from the different power management states S1 of the degree of entering, S3, S4 or S5.And S1, S3, on behalf of computer system, S4 or S5 be in different power down modes respectively, wherein S1 is expressed as holding state (standby mode), S3 is expressed as and suspends to random access memory (Suspend To RAM, be called for short STR) state, meaning is that computer system is temporary to random access memory with significant data, close the power supply of devices such as CPU (central processing unit) 10 and hard disk, but keep random access memory power supply so that data do not run off, and when system is waken up, just the significant data that will be temporary in random access memory reloads, and can be waken up fast in the hope of system.The software of then representing the plug of power supply unit still to be connected to civil power as for S4 shuts down (Soft off), the hardware shutdown (Mechanicaloff) that on behalf of the plug of power supply unit, S5 then pulled out.
See also Fig. 3 again, it is to link the power management states conversion synoptic diagram that connects PCI Express assembly on (Express Link) fast for it in the high-speed peripheral control unit interface bus protocol (PCI Express Protocol), wherein L0 represents normal operation (fully active link state), L0s represents holding state (Standby state), and the low power supply holding state (Lower Power Standbystate) of L1 representative, L2/L3 then represents low power supply sleep state (Lower Power Sleep state) and zero power supply off-mode (Zero Power Sleep state) respectively.Wherein before being transformed into L2 or L3, PCI Express assembly need be converted to a L2/L3 standby condition (L2/L3 ready) earlier, whether the power management states of viewing system is in the state with accessory power supply then, when system is in the state (for example above-mentioned S1, S3) with accessory power supply, PCI Express assembly just is transformed into the low power supply sleep state (LowerPower Sleep state) of L2, and when system was in the state (for example above-mentioned S5) with accessory power supply, PCI Express assembly just was transformed into the zero power supply off-mode of L3.
But, following defective has taken place in above-mentioned two technological means in known integration process, because will directly transmitting by the commentaries on classics of north bridge chips 11, the instruction cycle of the suspension of licence (STPGNT cycle) that CPU (central processing unit) 10 is sent notifies this South Bridge chip 12, and when this South Bridge chip 12 is received the instruction cycle of suspension of licence (STPGNT cycle), just can send the SUSB signal of representing sleep state S3, or send the SUSB signal of representing sleep state S4 or S5 and the combination of SUSC signal, and power supply 13 just comes the power supply of some assembly in the halt system in response to the combination of SUSB signal or SUSB signal and SUSC, with the different power management states S3 of the degree of entering, S4 or S5.But above-mentioned these actions will be violated in the high-speed peripheral control unit interface bus protocol (PCI Express Protocol) the power management standard for PCI Express assembly, because be connected the power supply of the PCI Express assembly on the north bridge chips 11 this moment is to be removed under the state of no early warning, make PCI Express assembly under the state that can't expect, be removed power supply, so may cause these PCI Express assemblies when being activated again, can't successfully finish link initialization action (initialization) next time, cause can't operate as normal defective.And how effectively solve the problem of above known approaches, for developing fundamental purpose of the present invention.
Summary of the invention
The present invention is a kind of power source management state control method, be applied in the computer system, this computer system has a CPU (central processing unit), a north bridge chips, a South Bridge chip and is connected in a peripheral unit on this north bridge chips, and this control method comprises: this CPU (central processing unit) one stopped clock signal and prepared to enter a battery saving mode in response to this South Bridge chip sends; This CPU (central processing unit) is just sent a suspension of licence signal to this north bridge chips after finishing the preparation that enters this battery saving mode; This north bridge chips makes this peripheral unit enter a corresponding peripheral unit power management states in response to this suspension of licence signal; And this north bridge chips with this suspension of licence singal transduction to this South Bridge chip, this South Bridge chip makes this computer system enter a corresponding power supply managing state in response to this this suspension of licence signal.
According to above-mentioned conception, power source management state control method of the present invention, wherein this north bridge chips can be supported a high-speed peripheral control unit interface bus protocol, and this peripheral unit that is connected on this north bridge chips is a high-speed peripheral control unit interface bus assembly.
According to above-mentioned conception, power source management state control method of the present invention, wherein this CPU (central processing unit) writes circulation by the data that the power management I/O port of this north bridge chips in this South Bridge chip sends, this South Bridge chip is just corresponding send this stop clock signal, and this north bridge chips is compared to one group of register value in response to these data write the round-robin master data, and when this comparison result meets a particular result, this north bridge chips will stop next this suspension of licence signal that is sent by this CPU (central processing unit), and this peripheral unit is sent a peripheral unit power management states switching signal.
According to above-mentioned conception, power source management state control method of the present invention, after wherein this north bridge chips sends this peripheral unit power management states switching signal, will be in receiving that power management states that this peripheral unit returns converts after signal or a schedule time arrive, and sends out this suspension of licence signal to this South Bridge chip again.
According to above-mentioned conception, power source management state control method of the present invention, wherein the preset content of this group register value is as follows: one checks that sleep commands starts the value that the register place value is made as representative " startup "; One checks that sleep address register value is set at the address of this power management I/O port; One checks that sleep commands kind register value is set at " I/O port writes circulation "; One checks that the sleep first data register value is set at one first default value; One checks that the sleep first cover curtain register value is set at one second default value; One checks that the sleep second data register value is set at one the 3rd default value; And an inspection sleep second a cover curtain register value is set at one the 4th default value.
According to above-mentioned conception, power source management state control method of the present invention, wherein this north bridge chips is compared to this group register value in response to these data write circulation, and it comprises the following step: check that this sleep commands starts the register place value and whether represents " startup "; Check that these data write the round-robin destination address and whether equal this inspection sleep address register value; Check that these data write the round-robin instruction type and whether equal this inspection sleep commands kind register value; Whether that checks that these data write that round-robin writes data and this second default value equals first default value with the door operation result; And be all when being when above-mentioned state, this north bridge chips will stop next this suspension of licence signal that is sent by this CPU (central processing unit), and this peripheral unit is sent a peripheral unit power management states switching signal.
According to above-mentioned conception, power source management state control method of the present invention, wherein this north bridge chips is compared to this group register value in response to these data write circulation, and it comprises the following step: check that this sleep commands starts the register place value and whether represents " startup "; Check that these data write the round-robin destination address and whether equal this inspection sleep address register value; Check that these data write the round-robin instruction type and whether equal this inspection sleep commands kind register value; Whether that checks that these data write that round-robin writes data and the 4th default value equals the 3rd default value with the door operation result; And be all when being when above-mentioned state, this north bridge chips will stop next this suspension of licence signal that is sent by this CPU (central processing unit), and this peripheral unit is sent a peripheral unit power management states switching signal.
According to above-mentioned conception, power source management state control method of the present invention wherein more comprises the following step: this CPU (central processing unit) writes circulation by one first data that the one first power management I/O port of this north bridge chips in this South Bridge chip sends; And the just corresponding system management interrupt signal that sends of this South Bridge chip makes this CPU (central processing unit) carry out a system management interrupt service to this CPU (central processing unit) so that this South Bridge chip send one stop clock signal.
According to above-mentioned conception, power source management state control method of the present invention, wherein this system management interrupt service of this CPU (central processing unit) execution comprises the following step: one in this north bridge chips checked that sleep commands starts the register place value and is set at " startup "; In this north bridge chips one checked that sleep address register value is set at the address of second source management I/O port; In this north bridge chips one checked that sleep commands kind register value is set at " I/O port writes circulation "; In this north bridge chips one checked that the sleep first data register value is set at one first default value; In this north bridge chips one checked that the sleep first cover curtain register value is set at one second default value; In this north bridge chips one checked that the sleep second data register value is set at one the 3rd default value; In this north bridge chips one checked that the sleep second cover curtain register value is set at one the 4th default value; This CPU (central processing unit) writes circulation by one second data that this north bridge chips this second source management I/O port in this South Bridge chip sends; And this north bridge chips writes circulation with these second data and changes and to reach this South Bridge chip.
According to above-mentioned conception, power source management state control method of the present invention, wherein this north bridge chips writes circulation and carries out the following step in response to receiving these second data: check that this sleep commands starts the register place value and whether represents " startup "; Check that these second data write the round-robin destination address and whether equal this inspection sleep address register value; Check that these second data write the round-robin instruction type and whether equal this inspection sleep commands kind register value; Whether that checks that these second data write that round-robin writes data and this second default value equals first default value with the door operation result; And be all when being when above-mentioned state, this north bridge chips will stop next this suspension of licence signal that is sent by this CPU (central processing unit), and this peripheral unit is sent a peripheral unit power management states switching signal.
According to above-mentioned conception, power source management state control method of the present invention, wherein this north bridge chips writes circulation and carries out the following step in response to receiving these second data: check that this sleep commands starts the register place value and whether represents " startup "; Check that these second data write the round-robin destination address and whether equal this inspection sleep address register value; Check that these second data write the round-robin instruction type and whether equal this inspection sleep commands kind register value; Whether that checks that these second data write that round-robin writes data and the 4th default value equals the 3rd default value with the door operation result; And be all when being when above-mentioned state, this north bridge chips will stop next this suspension of licence signal that is sent by this CPU (central processing unit), and this peripheral unit is sent a peripheral unit power management states switching signal.
According to above-mentioned conception, power source management state control method of the present invention, wherein this to stop clock signal be to belong to the signal that this South Bridge chip is issued to this CPU (central processing unit), and this suspension of licence signal is to belong to the special instruction circulation that this CPU (central processing unit) is issued to this South Bridge chip.
Description of drawings
Fig. 1 is the computer system functions synoptic diagram of utilization high-speed peripheral control unit interface bus protocol (PCI Express Protocol).
Fig. 2 is the process flow diagram that control chart 1 described computer system is carried out power supply managing.
Fig. 3 be in the high-speed peripheral control unit interface bus protocol for its chain fast connect the power management states conversion synoptic diagram of PCIExpress assembly.
Fig. 4 is that the present invention is the power source management state control method schematic flow sheet that the above-mentioned known approaches defective of improvement is developed.
Wherein, description of reference numerals is as follows:
The 10-CPU (central processing unit); The 11-north bridge chips; The 12-South Bridge chip; Power supply 13;
The 120-Power Management Unit; 140-high-speed peripheral control unit interface bus peripheral unit;
141-high-speed peripheral control unit interface bus peripheral unit;
142-high-speed peripheral control unit interface bus peripheral unit;
143-high-speed peripheral control unit interface bus peripheral unit;
144-high-speed peripheral control unit interface bus peripheral unit.
Embodiment
See also Fig. 4, it is that the present invention is the power source management state control method schematic flow sheet that the above-mentioned known approaches defective of improvement is developed, and it applies on the computer system of utilization high-speed peripheral control unit interface bus protocol (PCI Express Protocol) as shown in Figure 1 equally.At first, the present invention realizes one group of register earlier in north bridge chips 11, and it includes:
A. check that sleep commands starts register (CHK_Sleep_CMD_En register bit);
B. check sleep address register (CHK_Sleep_Addr register);
C. check sleep commands kind register (CHK_Sleep_CMD register);
D. check sleep first data register (CHK_Sleep_Data1 register);
E. check the sleep first cover curtain register (CHK_Sleep_Data2 register);
F. check sleep second data register (CHK_Sleep_Mask1 register);
G. check the sleep second cover curtain register (CHK_Sleep_Mask2 register); And
H. power management event returns status register (PME_TO_ACK_Status register).
And system software will be organized the value such as the following mode of register earlier and set:
A. this inspection sleep commands in this north bridge chips is started the register place value and be set at " startup ";
B. this inspection sleep address register value in this north bridge chips is set at the address (for example 4004h) of power management I/O port;
C. this inspection sleep commands kind register value in this north bridge chips is set at " I/O port writes circulation ";
D. this inspection sleep first data register value in this north bridge chips is set at one first default value (for example 28h);
E. this inspection sleep first cover curtain register value in this north bridge chips is set at one second default value (for example 03Fh);
F. this inspection sleep second data register value in this north bridge chips is set at one the 3rd default value (for example 24h);
G. this inspection sleep second cover curtain register value in this north bridge chips is set at one the 4th default value (for example 03Fh);
Then when operating system (Operating System) desires to make computer system to enter a battery saving mode, just make this CPU (central processing unit) 10 write circulation by the data that the power management I/O port (for example I/O port 4004h) of this north bridge chips 11 in this South Bridge chip 12 sends, this South Bridge chip 12 is just corresponding send one stop clock signal (STPCLK), and this north bridge chips 11 is passed to the South Bridge chip 12 except these data being write the circulation commentaries on classics, also writing the round-robin master data in response to these data comes above-mentioned this group register value is compared, when comparison result meets a particular result, this north bridge chips 11 will stop the instruction cycle of a next suspension of licence signal (STPGNTcycle) that is sent by this CPU (central processing unit) 10, and to described high-speed peripheral control unit interface bus peripheral unit 140,141,142,143,144 respectively send a peripheral unit power management states switching signal, and then make described high-speed peripheral control unit interface bus peripheral unit 140,141,142,143,144 all enter sleep or closed conditions such as L2 shown in Figure 3 or L3.And give all peripheral units when this north bridge chips 11 sends this peripheral unit power management states switching signal, and receiving that a power management states that all peripheral units return converts after signal or a schedule time arrive, north bridge chips 11 just can be delivered to this South Bridge chip 12 with the instruction cycle of this suspension of licence signal (STPGNT cycle), and South Bridge chip 12 can make this computer system enter a corresponding power supply managing state (for example above-mentioned power management states S3, S4 or S5) in response to this suspension of licence signal at last.
Lifting an example describes, when operating system (Operating System) desires to make computer system to enter a S3 battery saving mode, the data that this CPU (central processing unit) 10 is sent by the I/O port 4004h of this north bridge chips 11 in this South Bridge chip 12 write circulation (writing data is 24h), this South Bridge chip 12 is just corresponding send one stop clock signal (STPCLK), and this north bridge chips 11 is passed to the South Bridge chip 12 except these data being write the circulation commentaries on classics, also writing the round-robin master data in response to these data comes above-mentioned this group register value is compared, in this example, this checks that it is " startup " that sleep commands starts the register place value, it is identical with the default value of this inspection sleep address register that these data write round-robin destination address 4004h, these data write round-robin kind I/O port and write circulation also the default value with this inspection sleep commands kind register is identical, what these data write that round-robin writes data 24h and the 4th default value 03Fh also is to equal the 3rd default value 24h with the door operation result, therefore comparison result all meets this particular result, this north bridge chips 11 will be configured to stop the instruction cycle of a next suspension of licence signal (STPGNT cycle) that is sent by this CPU (central processing unit) 10 this moment, and to described high-speed peripheral control unit interface bus peripheral unit 140,141,142,143,144 respectively send a peripheral unit power management states switching signal, and then make described high-speed peripheral control unit interface bus peripheral unit 140,141,142,143,144 all enter sleep or closed conditions such as L2 shown in Figure 3 or L3.Power management event passback this moment status register just plays a role, when this north bridge chips 11 sends that this peripheral unit power management states switching signal is given all peripheral units but the power management states not receiving all peripheral units as yet and returned when converting signal or schedule time no show, power management event passback status register (for example will be in the conversion unfinished state, value is " 0 "), and after this north bridge chips 11 receives that a power management states that all peripheral units return converts signal or should arrive the schedule time, power management event passback status register just then (for example be in the state of converting, value is " 1 "), this moment, north bridge chips 11 just can be delivered to this South Bridge chip 12 with the instruction cycle of this suspension of licence signal (STPGNT cycle), and South Bridge chip 12 just can make this computer system enter a corresponding S3 power supply managing state in response to this suspension of licence signal at last.
In addition, when battery saving mode that operating system (Operating System) is desired to make computer system enter a S4 or S5, the data that this CPU (central processing unit) 10 is sent by the I/O port 4004h of this north bridge chips 11 in this South Bridge chip 12 write circulation (writing data is 28h), this South Bridge chip 12 is just corresponding send one stop clock signal (STPCLK), and this north bridge chips 11 is passed to the South Bridge chip 12 except these data being write the circulation commentaries on classics, also writing the round-robin master data in response to these data comes above-mentioned this group register value is compared, in this example, this checks that it is " startup " that sleep commands starts the register place value, it is identical with the default value of this inspection sleep address register that these data write round-robin destination address 4004h, these data write round-robin kind I/O port and write circulation also the default value with this inspection sleep commands kind register is identical, what these data write that round-robin writes data 28h and this second default value 03Fh also is to equal the first default value 28h with the door operation result, therefore comparison result all meets this particular result, this north bridge chips 11 will be configured to stop the instruction cycle of a next suspension of licence signal (STPGNT cycle) that is sent by this CPU (central processing unit) 10 this moment, and to described high-speed peripheral control unit interface bus peripheral unit 140,141,142,143,144 respectively send a peripheral unit power management states switching signal, and then make described high-speed peripheral control unit interface bus peripheral unit 140,141,142,143,144 all enter sleep or closed conditions such as L2 shown in Figure 3 or L3.Power management event passback this moment status register just plays a role, when this north bridge chips 11 sends that this peripheral unit power management states switching signal is given all peripheral units but the power management states not receiving all peripheral units as yet and returned when converting signal or schedule time no show, power management event passback status register (for example will be in the conversion unfinished state, value is " 0 "), and after this north bridge chips 11 receives that a power management states that all peripheral units return converts signal or should arrive the schedule time, power management event passback status register just then (for example be in the state of converting, value is " 1 "), this moment, north bridge chips 11 just can be delivered to this South Bridge chip 12 with the instruction cycle of this suspension of licence signal (STPGNT cycle), and South Bridge chip 12 just can make this computer system enter a corresponding S4 or S5 power supply managing state in response to this suspension of licence signal at last.
Moreover power source management state control method of the present invention more can change with following embodiment step to be finished:
One first data that this CPU (central processing unit) 10 is sent by the one first power management I/O port (40F0h) of this north bridge chips 11 in this South Bridge chip 12 write circulation (writing data is 24h or 28h);
The just corresponding system management interrupt signal that sends of this South Bridge chip 12 is to this CPU (central processing unit) 10, this CPU (central processing unit) is carried out a system management interrupt service (System Management Interrupt, SMI), with so that this South Bridge chip 12 send one stop clock signal;
And this system management interrupt service that this CPU (central processing unit) 10 is carried out comprises the following step:
A. this inspection sleep commands in this north bridge chips is started the register place value and be set at " startup ";
B. this inspection sleep address register value in this north bridge chips is set at the address (for example 40FFh) of power management I/O port;
C. this inspection sleep commands kind register value in this north bridge chips is set at " I/O port writes circulation ";
D. this inspection sleep first data register value in this north bridge chips is set at one first default value (for example 28h);
E. this inspection sleep first cover curtain register value in this north bridge chips is set at one second default value (for example 03Fh);
F. this inspection sleep second data register value in this north bridge chips is set at one the 3rd default value (for example 24h);
G. this inspection sleep second cover curtain register value in this north bridge chips is set at one the 4th default value (for example 03Fh);
This CPU (central processing unit) 10 writes circulation (writing data is 24h or 28h) by one second data that this north bridge chips 11 this second source management I/O port (40FFh) in this South Bridge chip sends; And
This north bridge chips 11 writes the circulation commentaries on classics with these second data and reaches this South Bridge chip 12 and carry out the following step:
Check that this sleep commands starts the register place value and whether represents " startup ";
Check that these second data write the round-robin destination address and whether equal this inspection sleep address register value;
Check that these second data write the round-robin instruction type and whether equal this inspection sleep commands kind register value;
Check these second data write round-robin write data and this second default value whether equal first default value with the door operation result or check that these second data write that round-robin writes data and the 4th default value whether equal the 3rd default value with the door operation result; And
When above-mentioned state is all when being, this north bridge chips 11 will stop next this suspension of licence signal that is sent by this CPU (central processing unit), and described high-speed peripheral control unit interface bus peripheral unit 140,141,142,143,144 respectively sent a peripheral unit power management states switching signal, and then make described high-speed peripheral control unit interface bus peripheral unit 140,141,142,143,144 all enter sleep or closed conditions such as L2 shown in Figure 3 or L3.Power management event passback this moment status register just plays a role, when this north bridge chips 11 sends that this peripheral unit power management states switching signal is given all peripheral units but the power management states not receiving all peripheral units as yet and returned when converting signal or schedule time no show, power management event passback status register (for example will be in the conversion unfinished state, value is " 0 "), and after this north bridge chips 11 receives that a power management states that all peripheral units return converts signal or should arrive the schedule time, power management event passback status register just then (for example be in the state of converting, value is " 1 "), this moment, north bridge chips 11 just can be delivered to this South Bridge chip 12 with the instruction cycle of this suspension of licence signal (STPGNT cycle), and South Bridge chip 12 just can make this computer system enter a corresponding power supply managing state in response to this suspension of licence signal at last.
In sum, it is to be removed under the expected state that technological means of the present invention can make the power supply of the PCI Express assembly that is connected on the north bridge chips 11, so can make these PCI Express assemblies when being activated again, can successfully finish link initialization action (initialization) next time, successfully solve the problem of above known approaches, reach exploitation fundamental purpose of the present invention.And the above-mentioned mode of utilizing register, cover curtain to carry out computing can provide the elasticity of design via changing each default value, but the present invention invents to such an extent that carry out various modifications by the person skilled in the art, but does not all break away from protection scope of the present invention.
Claims (12)
1. a power source management state control method is applied in the computer system, and this computer system has a CPU (central processing unit), a north bridge chips, a South Bridge chip and is connected in a peripheral unit on this north bridge chips, and wherein, this control method comprises:
This CPU (central processing unit) one stopped clock signal and prepared to enter a battery saving mode in response to this South Bridge chip sends;
This CPU (central processing unit) is just sent a suspension of licence signal to this north bridge chips after finishing the preparation that enters this battery saving mode;
This north bridge chips makes this peripheral unit enter a corresponding peripheral unit power management states in response to this suspension of licence signal; And
To this South Bridge chip, this South Bridge chip makes this computer system enter a corresponding power supply managing state in response to this this suspension of licence signal to this north bridge chips with this suspension of licence singal transduction.
2. power source management state control method as claimed in claim 1 it is characterized in that this north bridge chips can support a high-speed peripheral control unit interface bus protocol, and this peripheral unit that is connected on this north bridge chips is a high-speed peripheral control unit interface bus assembly.
3. power source management state control method as claimed in claim 1, it is characterized in that this CPU (central processing unit) writes circulation by the data that the power management I/O port of this north bridge chips in this South Bridge chip sends, this South Bridge chip is just corresponding send this stop clock signal, and this north bridge chips is compared to one group of register value in response to these data write the round-robin master data, and when this comparison result meets a particular result, this north bridge chips will stop next this suspension of licence signal that is sent by this CPU (central processing unit), and this peripheral unit is sent a peripheral unit power management states switching signal.
4. power source management state control method as claimed in claim 3, after it is characterized in that this north bridge chips sends this peripheral unit power management states switching signal, will be in receiving that power management states that this peripheral unit returns converts after signal or a schedule time arrive, and sends out this suspension of licence signal to this South Bridge chip again.
5. power source management state control method as claimed in claim 3 is characterized in that the preset content of this group register value is as follows:
One checks that sleep commands starts the value that the register place value is made as representative " startup ";
One checks that sleep address register value is set at the address of this power management I/O port;
One checks that sleep commands kind register value is set at " I/O port writes circulation ";
One checks that the sleep first data register value is set at one first default value;
One checks that the sleep first cover curtain register value is set at one second default value;
One checks that the sleep second data register value is set at one the 3rd default value; And
One checks that the sleep second cover curtain register value is set at one the 4th default value.
6. power source management state control method as claimed in claim 5, it is characterized in that this north bridge chips in response to these data write the circulation and this group register value is compared, it is characterized in that comprising the following step:
Check that this sleep commands starts the register place value and whether represents " startup ";
Check that these data write the round-robin destination address and whether equal this inspection sleep address register value;
Check that these data write the round-robin instruction type and whether equal this inspection sleep commands kind register value;
Whether that checks that these data write that round-robin writes data and this second default value equals first default value with the door operation result; And
When above-mentioned state is all when being, this north bridge chips will stop next this suspension of licence signal that is sent by this CPU (central processing unit), and this peripheral unit is sent a peripheral unit power management states switching signal.
7. power source management state control method as claimed in claim 5, it is characterized in that this north bridge chips in response to these data write the circulation and this group register value is compared, it is characterized in that comprising the following step:
Check that this sleep commands starts the register place value and whether represents " startup ";
Check that these data write the round-robin destination address and whether equal this inspection sleep address register value;
Check that these data write the round-robin instruction type and whether equal this inspection sleep commands kind register value;
Whether that checks that these data write that round-robin writes data and the 4th default value equals the 3rd default value with the door operation result; And
When above-mentioned state is all when being, this north bridge chips will stop next this suspension of licence signal that is sent by this CPU (central processing unit), and this peripheral unit is sent a peripheral unit power management states switching signal.
8. power source management state control method as claimed in claim 1 is characterized in that more comprising the following step:
This CPU (central processing unit) writes circulation by one first data that the one first power management I/O port of this north bridge chips in this South Bridge chip sends; And
The just corresponding system management interrupt signal that sends of this South Bridge chip makes this CPU (central processing unit) carry out a system management interrupt service to this CPU (central processing unit) so that this South Bridge chip send one stop clock signal.
9. power source management state control method as claimed in claim 8 is characterized in that this system management interrupt service that this CPU (central processing unit) is carried out comprises the following step:
In this north bridge chips one checked that sleep commands starts the register place value and is set at " startup ";
In this north bridge chips one checked that sleep address register value is set at the address of second source management I/O port;
In this north bridge chips one checked that sleep commands kind register value is set at " I/O port writes circulation ";
In this north bridge chips one checked that the sleep first data register value is set at one first default value;
In this north bridge chips one checked that the sleep first cover curtain register value is set at one second default value;
In this north bridge chips one checked that the sleep second data register value is set at one the 3rd default value;
In this north bridge chips one checked that the sleep second cover curtain register value is set at one the 4th default value;
This CPU (central processing unit) writes circulation by one second data that this north bridge chips this second source management I/O port in this South Bridge chip sends; And
This north bridge chips writes the circulation commentaries on classics with these second data and reaches this South Bridge chip.
10. power source management state control method as claimed in claim 8 is characterized in that this north bridge chips writes circulation and carries out the following step in response to receiving these second data:
Check that this sleep commands starts the register place value and whether represents " startup ";
Check that these second data write the round-robin destination address and whether equal this inspection sleep address register value;
Check that these second data write the round-robin instruction type and whether equal this inspection sleep commands kind register value;
Whether that checks that these second data write that round-robin writes data and this second default value equals first default value with the door operation result; And
When above-mentioned state is all when being, this north bridge chips will stop next this suspension of licence signal that is sent by this CPU (central processing unit), and this peripheral unit is sent a peripheral unit power management states switching signal.
11. power source management state control method as claimed in claim 8 is characterized in that this north bridge chips writes circulation and carries out the following step in response to receiving these second data:
Check that this sleep commands starts the register place value and whether represents " startup ";
Check that these second data write the round-robin destination address and whether equal this inspection sleep address register value;
Check that these second data write the round-robin instruction type and whether equal this inspection sleep commands kind register value;
Whether that checks that these second data write that round-robin writes data and the 4th default value equals the 3rd default value with the door operation result; And
When above-mentioned state is all when being, this north bridge chips will stop next this suspension of licence signal that is sent by this CPU (central processing unit), and this peripheral unit is sent a peripheral unit power management states switching signal.
12. power source management state control method as claimed in claim 1, it is characterized in that this stops clock signal is to belong to the signal that this South Bridge chip is issued to this CPU (central processing unit), and this suspension of licence signal is to belong to the special instruction circulation that this CPU (central processing unit) is issued to this South Bridge chip.
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| CN 200410068756 CN1278204C (en) | 2004-09-06 | 2004-09-06 | Power source management state control method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100381975C (en) * | 2005-12-19 | 2008-04-16 | 威盛电子股份有限公司 | Computer system and its power supply management method |
| CN100397300C (en) * | 2005-05-12 | 2008-06-25 | 辉达公司 | System command transmission method for computer system |
| CN100407103C (en) * | 2005-04-22 | 2008-07-30 | 辉达公司 | Computer system and its system chip power-saving mode instruction transmission method |
| CN103984901A (en) * | 2014-06-11 | 2014-08-13 | 上海新储集成电路有限公司 | Trusted computer system and application method thereof |
-
2004
- 2004-09-06 CN CN 200410068756 patent/CN1278204C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100407103C (en) * | 2005-04-22 | 2008-07-30 | 辉达公司 | Computer system and its system chip power-saving mode instruction transmission method |
| CN100397300C (en) * | 2005-05-12 | 2008-06-25 | 辉达公司 | System command transmission method for computer system |
| CN100381975C (en) * | 2005-12-19 | 2008-04-16 | 威盛电子股份有限公司 | Computer system and its power supply management method |
| CN103984901A (en) * | 2014-06-11 | 2014-08-13 | 上海新储集成电路有限公司 | Trusted computer system and application method thereof |
| CN103984901B (en) * | 2014-06-11 | 2017-08-25 | 上海新储集成电路有限公司 | A kind of trusted computer system and its application process |
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| CN1278204C (en) | 2006-10-04 |
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