CN1581812A - Apparatus for realizing ethernet VDSL accessing in ATM-DSLAM - Google Patents
Apparatus for realizing ethernet VDSL accessing in ATM-DSLAM Download PDFInfo
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- CN1581812A CN1581812A CN 03140152 CN03140152A CN1581812A CN 1581812 A CN1581812 A CN 1581812A CN 03140152 CN03140152 CN 03140152 CN 03140152 A CN03140152 A CN 03140152A CN 1581812 A CN1581812 A CN 1581812A
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Abstract
The device includes following parts and connections: multiplexing chip, VDSL set chips, FPGA parts, CPU, power source module, clock generation and driving module; multiplexing chip through UTOPIA interface and microprocessor interface is connected to FPGA parts and CPU; VDSL set chips through SMII interface and microprocessor interface is connected to FPGA parts and CPU; FPGA parts partition, process, convert Ethernet data packet into ATM cells, as well as constitute ATM cells to Ethernet data packet in order to carry out full duplex transmission data, and static binding of physical layer IDs between SMII interface and UTOPIA interface is carried out; CPU controls and manages VDSL set chips, FPGA part multiplexing chip; power source module supplies power at different voltages, and clock generation module generates clock signal. The invention can realize ADSL and VDSL access mode to be mixed inserted into ATM DSLAM system.
Description
Technical field
The present invention relates to a kind of DSL of utilization Digital Subscriber Loop and carry out the device of data communication, especially relate to a kind of device that Ethernet VDSL inserts of in ATM DSLAM, realizing.
Background technology
Along with DSL (Digital Subscriber Loop, Digital Subscriber Loop) technology, ADSL (Asymmetrical Digital Subscriber Loop particularly, ADSL (Asymmetric Digital Subscriber Line)) technology, constantly obtain the approval of user and telecom operators, the construction of DSLAM (Digital Subscriber Line AccessMultiplexer, Digital Subscriber Line Access Multiplexer) has really become the focus that the broadband is built at these 2 years.Traditional DSLAM network side interface generally adopts ATM (Asynchronous Transfer Mode, asynchronous transfer mode) interface, the telecom operators that relatively are fit to have the ATM metropolitan area network.This DSLAM based on the ATM framework is ATM DSLAM.
VDSL (Very high-speed Digital Subscriber Loop, the very high bit rate digital subscriber line road) be to be used for in-plant ultrahigh speed DSL technology, can on copper twisted pairs, transmit data more at a high speed than ADSL, VDSL provide 13Mbit/s to 52Mbit/s downstream rate and 1.5Mbit/s to the upstream rate of 26Mbit/s.Length of transmission line is no more than 300m during its maximum downstream rate, when transmission rate when 13Mbit/s is following, transmission range can reach 1.5km.The two-forty of VDSL can realize that high-quality video request program, interactive game, interactive mode teaching and video telephone etc. need the application of high bandwidth.
Though the atm network development speed slows down, but still the meeting long-term existence, and have irreplaceable advantage aspect end-to-end Qos (Qualityof Service service quality) assurance, the multiple service supporting.In order to protect investment, ATM DSLAM will long-term existence in the atm network environment.
For existing ATM DSLAM, generally only provide the access way of ADSL, but for building or the community user relatively concentrated, the broadband access method that this distance of VDSL is moderate is because its higher transmission rate then has more attraction.This just requires existing ATM DSLAM preferably to support VDSL and ADSL mixed insertion to use with, so that technology is backward compatible.Realize this two kinds of access way fusions on equipment, beyond doubt the best mode of ADSL and VDSL combination.ADSL and VDSL access technology also can be selected according to many objective factors such as user's distribution situation, bandwidth demand, transmission range, line quality situations fully flexibly by operator in addition, realize the intersection of different user is covered.
Summary of the invention
Technical problem to be solved by this invention provides a kind of device of realizing Ethernet VDSL access in ATM DSLAM, thereby realizes ADSL and VDSL mixed insertion in existing ATM DSLAM equipment, to satisfy the different demands of different user.
In order to address the above problem, the invention provides a kind of device that Ethernet VDSL inserts of in ATM DSLAM, realizing, be used for ATM DSLAM system, its characteristics are, comprising: multiplexing chip, VDSL nest plate, FPGA field programmable gate array, CPU processor, power module, clock generating and driver module; Described multiplexing chip is by UTOPIA interface (Universal Test ﹠amp; Operations PHY Interfacefor ATM ATM universal test and operation-interface) be connected with described CPU processor with described FPGA field programmable gate array respectively with Microprocessor Interface, and be connected with the core board of described ATM DSLAM system by LVDS (Low Voltage DifferentialSignaling Low Voltage Differential Signal) interface and carry out two-way point-to-point communication; Described VDSL nest plate is connected with described CPU processor with described FPGA field programmable gate array respectively with Microprocessor Interface by SMII interface (Serial Media IndependentInterface serial transmission Media Independent Interface), and sends and receive Ethernet data by twisted-pair feeder; Described FPGA field programmable gate array is used for Ethernet data bag dividing processing being converted to ATM cell and ATM cell being formed the Ethernet data bag carry out full duplex position transmission data, and carries out the static state binding of the physical layer ID of SMII interface and UTOPIA interface; Described CPU processor is used for control and manages described VDSL nest plate, FPGA field programmable gate array and multiplexing chip; Described power module produces different magnitudes of voltage by level conversion and powers, and described clock generating and driver module are used to produce needed corresponding clock signal.
The device that above-mentioned Ethernet VDSL inserts, its characteristics are that described FPGA field programmable gate array also is used to carry out data traffic control.
The device that above-mentioned Ethernet VDSL inserts, its characteristics are, further comprise the SSRAM synchronized SRAM that is connected with described FPGA field programmable gate array.
The device that above-mentioned Ethernet VDSL inserts, its characteristics are, described FPGA field programmable gate array further comprises transmission/reception SMII interface module, transmission/reception segment processing module, UTOPIA interface module, outer/inner storage control module, Microprocessor Interface module and internal storage; Described transmission/reception SMII interface module is connected with described UTOPIA interface module by described transmission/reception segment processing/recombination module, described outer/inner storage control module is connected with the Microprocessor Interface module with described transmission/reception segment processing/recombination module, transmission/reception SMII interface module respectively, and described internal storage is connected with described storage inside control module.。
The device that above-mentioned Ethernet VDSL inserts, its characteristics are, described reception SMII interface module, the data that are used for receiving become 10 bit data through serial to parallel conversion, wherein 2bit is used for the control of SMII interface, and all the other 8 is valid data, controls valid data simultaneously and writes in the respective frame buffering; Described transmission SMII interface module is used for the Ethernet data bag grouping from described UTOPIA interface module is write corresponding transmit port frame buffering.
The device that above-mentioned Ethernet VDSL inserts, its characteristics are, described transmission segment processing module, be used for arrangement according to dispatch list, to be sent to the corresponding port of described UTOPIA interface module from the ethernet data frame conversion of described SMII interface module and the ATM cell of segment processing one-tenth support AAL5 (ATM Adaptation Layer 5 ATM Adaptation Layer 5) agreement; Described reception segmentation recombination module is used for each receiving port formation of the described UTOPIA interface module of poll, starts described port data is received processing, and converts the ATM cell that is received to ethernet data frame.
The device that above-mentioned Ethernet VDSL inserts, its characteristics are, described outer/inner storage control module, be used to finish outer/inner SSRAM bus interface, and the operation of described transmission/reception segment processing/recombination module, transmission/reception SMII interface module and Microprocessor Interface module read-write outer/inner SSRAM is arbitrated.
The device that above-mentioned Ethernet VDSL inserts, its characteristics are that described reception segment processing/recombination module has limit priority when described outer/inner SSRAM is carried out read-write operation.
Adopt said apparatus, can overcome ADSL access way single in the existing ATM DSLAM equipment, realize ADSL and VDSL mixed insertion technology.
The present invention is described in detail below in conjunction with drawings and Examples.
Description of drawings
Fig. 1 is the used VDSL user's plate primary structure block diagram of the present invention.
Fig. 2 is the inner primary structure block diagram of FPGA among Fig. 1.
Embodiment
The VDSL of Ethernet inserts to cooperate with ATM DSLAM product by VDSL user's plate and realizes, ZXDSL 8220 systems with ZTE are example, this ZXDSL 8220 is a kind of ATM DSLAM products, mainly comprises upper plate, core board and user's plate in this system.The function of this VDSL user's plate is that the user interface and the last company that finish based on the VDSL system of Infineon scheme converge.From connecting scheme, it and general A DSL subscriber plate do not have any difference, but since the VDSL system of Infineon scheme commonly used be based on IP, so be to adopt a FPGA to realize that Ethernet interface (SMII) arrives the conversion of atm interface (UTOPIA) in that veneer is inner in this enforcements.
Be illustrated in figure 1 as the connection diagram of each functional module of VDSL user's plate.This DSL subscriber's plate comprises: multiplexing chip 3, VDSL nest plate 1, FPGA field programmable gate array 2, CPU processor 4, power module 6, clock generating and driver module 7.Wherein, VDSL nest plate 1 is to utilize the VDSL technology based on QAM (Quadrature Amplitude Modulation quadrature amplitude modulation) to send and receive Ethernet data on twisted-pair feeder.This FPGA field programmable gate array 2 is responsible for Ethernet data bag dividing processing is converted to ATM cell and ATM cell is reassembled into the Ethernet data bag.The function that this FPGA field programmable gate array 2 is finished comprises the static state binding of the PHY ID that realizes 10M/100Mbps Ethernet interface speed full duplex transmission data, data traffic control and SMII interface and UTOPIA interface.Multiplexing chip 3 provides utopia bus interface, LVDS interface and Microprocessor Interface.Multiplexing chip 3 on VDSL user's plate is used with the multiplexing chip of core board in ZXDSL 8220 systems, connects by backboard, finishes point-to-point communication.The whole service data flow is two-way as shown in Figure 1, and the data of coming from subscribers feeder are to VDSL nest plate 1, arrives multiplexing chip 3 again through the interface conversion of this FPGA field programmable gate array 2, is converted to backboard on the LVDS signal again.The effect of CPU microprocessor 4 is control and management VDSL nest plate 1, FPGA field programmable gate array 2 and multiplexing chip 3.Power module 6 is that all kinds of chips are powered by the power supply that level conversion produces different magnitudes of voltage, and clock generating and driver module 7 are according to the different clock signal of the required generation of all kinds of chips.
Be illustrated in figure 2 as the inner primary structure block diagram of FPGA.These FPGA field programmable gate array 2 inside mainly are divided into transmission SMII interface module (TxSmii) 21, receive SMII interface module (RxSmii) 22, send segment processing module (TxSar) 23, receive segmentation recombination module (RxSar) 24, UTOPIA interface module 25 (Utopia), external storage controller module 26 (Emc), storage inside controller module 27 (Imc), Microprocessor Interface module 28 modules such as (CpuItf).Wherein, external storage controller module 26 (Emc) is connected with synchronized SRAM 30 (SSRAM), and storage inside controller module 27 (Imc) is connected with internal storage 29 (RAM).The function of each module is respectively described below:
The work that this reception SMII interface module (RxSmii) 22 is carried out is as follows:
The data of 24 tunnel full duplex 125Mbps SMII receiving interfaces are reduced to 12.5MHz behind serial to parallel conversion 10 bit data wherein 2bit are used for the control of SMII interface, per 2 the 8bit valid data of other 8bit position valid data are formed 16 valid data, write the interface frame buffering.Simultaneously, 222 pairs 24 tunnel inputs of RxSmii controller poll, if a certain road interface frame buffering non-NULL, then select this road, inquire about the uplink port information table on this road in the internal RAM then, judge according to the read-write pointer whether port external frame buffering is non-full, if then log-on data is moved, frame data are written in the external RAM frame buffering, as synchronous static random access memory 30 (SSRAM), and data are made CRC check, if crc error, bag counting pointer does not add one; frame is dropped, if correct counting pointer adds one.Amended pointer exists in the uplink port information table on this road in the internal storage 29 (RAM).
The work that transmission segment processing module (TxSar) 23 is carried out is as follows:
According to the arrangement of dispatch list, start the data that send corresponding port at each time slot.Whether non-full, if full, then do not start transmission if at first inquiring about UTOPIA interface module 25 (Utopia) transmit queue (TxQueue), if not full, then start transmission, carry out next step operation.Inquire about the uplink port information table in the internal storage 29 (RAM) then, judge according to the read-write pointer whether port has the bag needs to send.If do not have, this time slot unit that do not post a letter then; If have, the CPCS-PDU that then forms AAL5 behind this bag interpolation 1483B head, through the AAL5 segment processing, send a cell in this port transmit queue of UTOPIA interface module 25 (Utopia) at this time slot, revise the write pointer of this port of UTOPIA interface module 25 (Utopia).Secondly, revise the read pointer in this port uplink port information table, and write internal storage 29 (RAM).Mac frame has CRC (PID=0x0001) and does not have two kinds of processing modes of CRC (PID=0x0007) and all supports in the 1483B protocol encapsulation.
The work that this reception segmentation recombination module (RxSar) 24 carries out is as follows:
At first, each receiving port formation of poll UTOPIA interface module 25 (Utopia), if find a certain port non-NULL, the reception that then starts this port is handled; Then, whether full, if full, then jump to next port if inquiring about this port external buffer district, if not full, be for further processing; Secondly, the cell of receiving is done the processing that AAL5 receives reorganization and removes the 1483B protocol header, the Ether frame data that recover are write in the external frame buffering, and revise this port write pointer in the down link port information table in internal storage 29 (RAM), also revise UTOPIA interface module 25 (Utopia) receiving port read pointer simultaneously.
The work that this transmission SMII interface module (TxSmii) 21 is carried out is as follows:
At first, 24 transmission SMII mouths are divided into 3 groups (0～7,8～15,16～23), 3 groups of ports of TxSmii controller 212 polls, and each the most multidirectional in principle wherein one group interface frame buffering 211 writes the 64bytes content, switches to next group then.When being polled to a certain group, TxSmii controller 212 is inquired about successively the down link port information table from last transmit port and is read and write pointer, if scanned 8 ports of this group, external buffer is sky, then skip this group, if find a certain port buffering non-NULL, then move this port data before this.Then, when each one group of port obtains bus, before the whole bag data of front port have been removed, do not switch to next port, after having removed, just switch to the port that next need send in this group.Move all at every turn and will revise read pointer in the down link port information table.Every group of shared 100Mbps bandwidth of 8 transmit ports, whole transmission link has the bandwidth of 300Mbps in theory.
The work that external storage controller module 26 (Emc) is carried out is as follows:
At first, finish outside SSRAM bus interface function.Secondly, transmission SMII interface module (TxSmii) 22, reception SMII interface module (RxSmii) 21, transmission segment processing module (TxSar) 23, reception segmentation recombination module (RxSar) 24, UTOPIA interface module 25 (Utopia), 28 5 modules of Microprocessor Interface module being read and write the operation of the synchronized SRAM 30 (SSRAM) of outside arbitrates, give to receive SMII interface module (RxSmii) 21, thereby guarantee the instant bandwidth that its 800Mbps is above with limit priority.Outside synchronized SRAM 30 (SSRAM) operates in 32bit*50MHz, has the bandwidth of 1.6Gbps in theory.For guaranteeing making full use of of external bus bandwidth, the outside synchronized SRAM 30 (SSRAM) of visit must be with the mode of operation of 32bit, and preferably use the visit of continuous multicycle, this point has given assurance by internal external frame buffer RAM by the mode of 64bytes block management.
The work that storage inside controller module 27 (Imc) carries out is as follows:
At first, finish inner SSRAM bus interface function.Secondly, the operation that sends SMII interface module (TxSmii) 22, reception SMII interface module (RxSmii) 21, transmission segment processing module (TxSar) 23, reception segmentation recombination module (RxSar) 24, UTOPIA interface module 25 (Utopia), 28 5 module reading and writing internals of Microprocessor Interface module memory 29 (RAM) is arbitrated, give to receive SMII interface module (RxSmii) 21, thereby guarantee its real-time with limit priority.Internal storage 29 (RAM) is mainly used in the storage following message: dispatch list, uplink port information table, down link port information table.Internal storage 29 (SRAM) operates in 32bit*50MHz, has the bandwidth of 1.6Gbps in theory.
This UTOPIA interface module 25 (Utopia) is mainly finished following work:
At sending direction, the 24 tunnel independently take a fixed space of transmit frame buffering separately, are used for maximum 4 cells in every road of buffer memory (cell), the every road of sending module poll frame buffering, and an if not empty and transmission mouthful permission sends, and then sends cell with this road corresponding address.At receive direction, 24 the tunnel independently take a fixed space of received frame buffering separately, are used for maximum 4 cells in every road of buffer memory (cell), and receiver module writes the cell of receiving in the cell-buffering of corresponding port, if buffering is full, then outside transmit leg is produced sign of back.The mechanism of 24 tunnel individual buffer can be avoided the congested situation that causes other road of whole UTOPIA interface module 25 (Utopia) all can not send cell of single channel.
Microprocessor control module 28 (CpuItf) is main to realize and the interface function of outer CPU that 4 pairs of FPGA field programmable gate arrays 2 of CPU microprocessor are operated to make things convenient for, maintenance and management.System can be configured FPGA field programmable gate array 2 by this interface, reading state and statistical information, and FPGA field programmable gate array 2 can send interruption to system.
The above only is the present invention's preferred embodiment wherein, is not to be used for limiting practical range of the present invention; All equalizations of doing according to claim of the present invention change and modify, and are claim of the present invention and contain.
Claims (8)
1, a kind of device of in ATM DSLAM, realizing Ethernet VDSL access, be used for ATM DSLAM system, it is characterized in that, comprising: multiplexing chip, VDSL nest plate, FPGA field programmable gate array, CPU processor, power module, clock generating and driver module; Described multiplexing chip is connected with described CPU processor with described FPGA field programmable gate array respectively with Microprocessor Interface by the UTOPIA interface, and is connected with the core board of described ATMD SLAM system by Low Voltage Differential Signal LVDS interface and carries out two-way point-to-point communication; Described VDSL nest plate is connected with described CPU processor with described FPGA field programmable gate array respectively with Microprocessor Interface by the SMII interface, and sends and receive Ethernet data by twisted-pair feeder; Described FPGA field programmable gate array is used for Ethernet data bag dividing processing being converted to ATM cell and ATM cell being formed the Ethernet data bag carry out full duplex position transmission data, and carries out the static state binding of the physical layer ID of SMII interface and UTOPIA interface; Described CPU processor is used for control and manages described VDSL nest plate, FPGA field programmable gate array and multiplexing chip; Described power module produces different magnitudes of voltage by level conversion and powers, and described clock generating and driver module are used to produce needed corresponding clock signal.
2, the device of Ethernet VDSL access according to claim 1 is characterized in that, described FPGA field programmable gate array also is used to carry out data traffic control.
3, the device of Ethernet VDSL access according to claim 1 is characterized in that, further comprises the SSRAM synchronized SRAM that is connected with described FPGA field programmable gate array.
4, the device that inserts according to claim 1 or 3 described Ethernet VDSL, it is characterized in that, described FPGA field programmable gate array further comprises transmission/reception SMII interface module, transmission/reception segment processing module, UTOPIA interface module, outer/inner storage control module, Microprocessor Interface module and internal storage; Described transmission/reception SMII interface module is connected with described UTOPIA interface module by described transmission/reception segment processing/recombination module, and described outer/inner storage control module is connected with the Microprocessor Interface module with described transmission/reception segment processing/recombination module, transmission/reception SMII interface module respectively; Described internal storage is connected with described storage inside control module.
5, the device of Ethernet VDSL access according to claim 4, it is characterized in that, described reception SMII interface module, the data that are used for receiving become 10 bit data through serial to parallel conversion, wherein 2bit is used for the control of SMII interface, all the other 8 is valid data, controls valid data simultaneously and writes in the respective frame buffering; Described transmission SMII interface module is used for the Ethernet data bag grouping from described UTOPIA interface module is write corresponding transmit port frame buffering.
6, the device of Ethernet VDSL access according to claim 4, it is characterized in that, described transmission segment processing module, be used for arrangement according to dispatch list, to be sent to the corresponding port of described UTOPIA interface module from the ethernet data frame conversion of described SMII interface module and the ATM cell of segment processing one-tenth support AAL5 agreement; Described reception segmentation recombination module is used for each receiving port formation of the described UTOPIA interface module of poll, starts described port data is received processing, and converts the ATM cell that is received to ethernet data frame.
7, the device of Ethernet VDSL access according to claim 4, it is characterized in that, described outer/inner storage control module, be used to finish outer/inner SSRAM bus interface, and the operation of described transmission/reception segment processing/recombination module, transmission/reception SMII interface module and Microprocessor Interface module read-write outer/inner SSRAM is arbitrated.
8, the device of Ethernet VDSL access according to claim 7 is characterized in that described reception segment processing/recombination module has limit priority when described outer/inner SSRAM is carried out read-write operation.
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| CNB03140152XA CN100544293C (en) | 2003-08-08 | 2003-08-08 | A kind of device of in ATM DSLAM, realizing Ethernet VDSL access |
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| CNB03140152XA CN100544293C (en) | 2003-08-08 | 2003-08-08 | A kind of device of in ATM DSLAM, realizing Ethernet VDSL access |
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| CN1581812A true CN1581812A (en) | 2005-02-16 |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007054031A1 (en) * | 2005-11-10 | 2007-05-18 | Huawei Technologies Co., Ltd. | A method and apparatus for implementing xdsl hybrid access |
| WO2008080329A1 (en) * | 2006-12-31 | 2008-07-10 | Huawei Technologies Co., Ltd. | A method, system and access equipment for realizing service configuration |
| WO2009000126A1 (en) * | 2007-06-22 | 2008-12-31 | Zte Corporation | Vdsl2 accessing device and service handing method thereof |
| CN100452800C (en) * | 2005-06-09 | 2009-01-14 | 烽火通信科技股份有限公司 | FPGA based rapid Ethernet port bandwidth control system |
| CN100547960C (en) * | 2005-03-18 | 2009-10-07 | 中国科学院自动化研究所 | A kind of asymmetric high speed semi-duplex communicating system and communication means |
| CN101018185B (en) * | 2005-12-09 | 2010-05-12 | 英飞凌科技股份公司 | Bonding circuit for a line card and method for bonding data fragments |
| WO2011069303A1 (en) * | 2009-12-11 | 2011-06-16 | 中兴通讯股份有限公司 | X digital subscriber line (xdsl) data transmission device and method |
| CN101194435B (en) * | 2005-06-10 | 2011-09-07 | 适应性频谱和信号校正股份有限公司 | Vectored dsl nesting |
| CN101147350B (en) * | 2005-03-23 | 2012-01-11 | 株式会社Ntt都科摩 | MIMO multiplex communication apparatus and signal separation method |
| CN101238693B (en) * | 2005-06-10 | 2012-03-28 | 适应性频谱和信号校正股份有限公司 | Dsl system loading and ordering |
| CN103577378A (en) * | 2013-11-15 | 2014-02-12 | 哈尔滨工业大学深圳研究生院 | Full-duplex asynchronous serial communication method |
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- 2003-08-08 CN CNB03140152XA patent/CN100544293C/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100547960C (en) * | 2005-03-18 | 2009-10-07 | 中国科学院自动化研究所 | A kind of asymmetric high speed semi-duplex communicating system and communication means |
| CN101147350B (en) * | 2005-03-23 | 2012-01-11 | 株式会社Ntt都科摩 | MIMO multiplex communication apparatus and signal separation method |
| CN100452800C (en) * | 2005-06-09 | 2009-01-14 | 烽火通信科技股份有限公司 | FPGA based rapid Ethernet port bandwidth control system |
| CN101194435B (en) * | 2005-06-10 | 2011-09-07 | 适应性频谱和信号校正股份有限公司 | Vectored dsl nesting |
| CN101238693B (en) * | 2005-06-10 | 2012-03-28 | 适应性频谱和信号校正股份有限公司 | Dsl system loading and ordering |
| US7756161B2 (en) | 2005-11-10 | 2010-07-13 | Huawei Technologies Co., Ltd. | Method and device for XDSL hybrid access |
| WO2007054031A1 (en) * | 2005-11-10 | 2007-05-18 | Huawei Technologies Co., Ltd. | A method and apparatus for implementing xdsl hybrid access |
| CN101018185B (en) * | 2005-12-09 | 2010-05-12 | 英飞凌科技股份公司 | Bonding circuit for a line card and method for bonding data fragments |
| CN101001241B (en) * | 2006-12-31 | 2011-04-20 | 华为技术有限公司 | Method, system and access equipment for implementing CPE working mode self-adaption |
| WO2008080329A1 (en) * | 2006-12-31 | 2008-07-10 | Huawei Technologies Co., Ltd. | A method, system and access equipment for realizing service configuration |
| US8908712B2 (en) | 2006-12-31 | 2014-12-09 | Huawei Technologies Co., Ltd. | Method, system and access device for implementing service configuration |
| WO2009000126A1 (en) * | 2007-06-22 | 2008-12-31 | Zte Corporation | Vdsl2 accessing device and service handing method thereof |
| WO2011069303A1 (en) * | 2009-12-11 | 2011-06-16 | 中兴通讯股份有限公司 | X digital subscriber line (xdsl) data transmission device and method |
| CN103577378A (en) * | 2013-11-15 | 2014-02-12 | 哈尔滨工业大学深圳研究生院 | Full-duplex asynchronous serial communication method |
| CN103577378B (en) * | 2013-11-15 | 2016-09-07 | 哈尔滨工业大学深圳研究生院 | A kind of full duplex asynchronous serial communication method |
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