CN1577820A - Semiconductor package and producing method thereof - Google Patents
Semiconductor package and producing method thereof Download PDFInfo
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- CN1577820A CN1577820A CNA2004100545334A CN200410054533A CN1577820A CN 1577820 A CN1577820 A CN 1577820A CN A2004100545334 A CNA2004100545334 A CN A2004100545334A CN 200410054533 A CN200410054533 A CN 200410054533A CN 1577820 A CN1577820 A CN 1577820A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Abstract
Provided is a semiconductor package that can be improved in reliability and yield by preventing a semiconductor chip mounted on a substrate from being damaged, and to provide a method of manufacturing the package. In the semiconductor package, a resin 7 is provided to cover the peripheral side of a small-diameter chip (semiconductor chip) 5 face-down mounted on a large-diameter chip 3 serving as a substrate. Particularly, the resin 7 is provided on the large-diameter chip 3 in a state where the resin 7 completely covers the side wall of the small-diameter chip 5 and, at the same time, completely surround the chip 5 with a thickness t in the plane at the same height as that of the top surface of the chip 5.
Description
Technical field
The present invention relates to semiconductor packages and manufacture method thereof, particularly relate to the semiconductor packages and the manufacture method thereof of semiconductor chip upside-down mounting at wiring substrate and other semiconductor chips.
Background technology
Miniaturization and densification with semiconductor packages are purpose, are to carry out the mounting means (so-called flip-chip) of semiconductor chip upside-down mounting at wiring substrate.Know also that a plurality of semiconductor chips of handlebar are assembled in and realize the semiconductor packages of multifunction in fact in the encapsulation.This semiconductor packages prevents the thick filmization of package thickness by the slimming of semiconductor chip.
The semiconductor chip slimming following the carrying out of manufacturing of semiconductor packages.At first be installed on flip-chip on each position on the substrate that is formed with distribution cutting apart a plurality of semiconductor chips that wafer obtains with upside-down mounting.Inject sealing resin and solidify the back on the composition surface of substrate and semiconductor chip then by semiconductor chip is carried out the slimming of semiconductor chip from back side grinding.This order also can be following order in addition, that is, the wafer state before segmented semiconductor chip is carried out slimming, again this wafer is installed in (with reference to following patent documentation 1) on the substrate that has been divided into each semiconductor chip afterwards.After superincumbent the finishing, carry out as required the substrate that the slimming semiconductor chip is installed is divided into each part that semiconductor chip is installed, relatively substrate forms the electrode that takes out usefulness to the outside, the operation that further is installed in substrate on the lead frame and implements that lead-in wire connects etc. according to the form of semiconductor packages.
Patent documentation 1: the spy opens 2002-170918 communique (especially with reference to Fig. 5, Fig. 6 and paragraph 0043,0045).
As mentioned above, also substrate is implemented various operations make the state that the slimming semiconductor chip has been installed in the operation of semiconductor packages on substrate after.But these operations are to carry out with the state that semiconductor chip exposes on substrate, thus in the processing procedure of substrate, appear at slimming easily semiconductor chip above the bight produce the breach equivalent damage.This becomes the main cause that causes that the semiconductor packages accepted product percentage reduces.And after thermal cycle reliability test and moisture absorption in the backflow test, cover if resin useless is reliable between semiconductor chip periphery and substrate, then peel off between semiconductor chip and substrate and slowly carry out, take place finally that the bonding part is peeled off and the problem that breaks.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor chip damage that can prevent to be installed on the substrate, and can seek to improve the semiconductor packages and the manufacture method thereof of reliability and accepted product percentage.
In order to reach this purpose, semiconductor packages of the present invention is provided with resin, it is to cover the state that is installed in the semiconductor chip side week on the substrate, particularly this resin is when the sidewall of semiconductor chip is covered fully, with the face of this sustained height above semiconductor chip on full week of this semiconductor chip is arranged on the substrate with the state with thickness (thickness non-0 certain numerical value more than) encirclement.Be semiconductor chip to be equivalent to the back side during to substrate flip-chip on this is said.
This semiconductor packages has not only suppressed exposing of bight, the semiconductor chip back side, and full week of semiconductor chip backside bight is carried out reliably protecting with the resin with thickness.Owing to become the state that surrounds with resin between semiconductor chip and substrate, so become the state of semiconductor chip secure fixation at substrate with thickness.
The manufacture method of semiconductor packages of the present invention is by in sequence following.At first the semiconductor chip upside-down mounting on substrate, full week of the side perisporium of this semiconductor chip is covered with resin.Then become with the face of this (being the back side) sustained height above semiconductor chip on before full week surrounds with the described resin with thickness (thickness non-0 certain numerical value more than) this semiconductor chip the state, this semiconductor chip and this resin are carried out slimming.
According to this manufacture method, by adjusting the resin state on substrate, supply with and the degree of semiconductor chip and resin slimming, then become with the face of semiconductor chip backside sustained height on full week of this semiconductor chip with state with the above resin encirclement of certain thickness.Therefore become the state that full week of semiconductor chip backside bight carries out secure fixation or protected, when carrying out the thin-walled property of semiconductor chip and carrying out preventing the added damage of semiconductor chip in the later operation with resin with thickness.
As mentioned above; according to semiconductor packages of the present invention; because be installed in the bight, top of the semiconductor chip on the substrate by the resin energy reliably protecting with thickness all entirely; so damage of semiconductor chip when preventing slimming; prevent slimming simultaneously the operation of semiconductor chip after slimming in be damaged; and because energy secure fixation semiconductor chip and substrate, so can seek to improve the reliability of semiconductor packages.Because the damage of semiconductor chip when having prevented slimming,, can further improve reliability like this so semiconductor chip can also be made thinner.
Manufacture method according to semiconductor packages of the present invention; by becoming the state that is installed in the full week of bight, top of the semiconductor chip on the substrate with resin reliably protecting with thickness; the damage of semiconductor chip when preventing slimming; the added damage of semiconductor chip that has prevented simultaneously in the operation afterwards slimming can seek to improve the accepted product percentage of semiconductor packages.
Description of drawings
Fig. 1 is the profile of expression embodiment semiconductor package example;
Fig. 2 is the plane graph of Fig. 1 semiconductor packages major part;
Fig. 3 be the embodiment semiconductor packages manufacturing procedure picture (one of);
Fig. 4 is the manufacturing procedure picture (two) of embodiment semiconductor packages.
Embodiment
Describe semiconductor packages of the present invention and manufacture method thereof below with reference to the accompanying drawings in detail.
＜semiconductor packages 〉
Fig. 1 is the profile of semiconductor packages of the present invention, and Fig. 2 is the plane graph of semiconductor packages major part shown in Figure 1.
Wherein big footpath chip 3 is the semiconductor chips that for example formed by the logic system semiconductor element, is provided with at this and has omitted illustrated a plurality of electrode pad (omitting diagram).Seek and being connected of path chip 5 by being arranged on protrusion sheet 9 on these electrode pads.
When a plurality of path chip 5 is installed on the chip 3 of big footpath, cover with resin 7 sidewall of at least one the path chip 5 in the path chip that is installed on the big footpath chip 3 with above-mentioned the sort of state.
As shown in the figure, chip described in this semiconductor packages 1 is to be installed in the fixing states of big footpath chip 3 on the back welding dish 11 of lead frame with conductive paste (silver paste etc.) to A.And the connecting line 15 that is arranged on the lead-in wire 13 usefulness metal wires etc. of electrode pad (omitting diagram) and lead frame from big footpath chip 3 peripheral parts that resin 7 exposes is connected.
Reinstate sealing resin 17 resin-sealed being integral with big footpath chip 3 that protrudes the sheet connection and path chip 5 with the back welding dish 11 and the connecting line 15 1 of lead frame mutually.
The sidewall of path chip 5 becomes the state that is covered by resin 7 fully in the semiconductor packages 1 of this structure, has not only suppressed exposing of bight, path chip 5 back side, and the full week of bight, the back side that makes path chip 5 resin 7 by having thickness by reliably protecting.Therefore; fully slimming path chip 5 with also protected in 7 reliable maintenances of resin; so between path chip and substrate, also be difficult to peel off, on path chip 5, be difficult to occur the damage of breach and crackle etc., guaranteed the reliability of semiconductor packages 1.
Mutually the big footpath chip 3 of upside-down mounting and path chip 5 be in thermal cycling test for example, is mutually to an opposite side warpage.Therefore effect has the stress of peeling off on the protrusion sheet 9 in the bight of path chip 5, takes place sometimes to protrude that sheet 9 is stripped from and the bad situation that breaks.But by little with big footpath chip 3 usefulness resins, 7 secure fixation, and then can also make path chip 5, so can prevent the generation of described bad situation with big footpath chip 3 warpages the inhibition of the buckling force of path chip 5 path chip 5 sides.Even big footpath chip 3 is made path chip 5 very thin, also can suppress little to the buckling force of path chip 5, so can make path chip 5, can prevent the generation of described bad situation with big footpath chip 3 warpages.Above result is that semiconductor packages 1 can obtain higher reliability.
The manufacture method of＜semiconductor packages 〉
The manufacture method of semiconductor packages of the present invention is described according to each section process chart below., on the parts identical, pay prosign and describe as the manufacture method of an example at this with described structure member with the semiconductor packages 1 of Fig. 1 and Fig. 2 explanation.
At first shown in Fig. 3 (1), the wafer that is made of a plurality of big footpaths chip 3 parts 30 that is formed with semiconductor element in the installed surface side is prepared as substrate.Go up to form at the electrode pad (diagram is omitted) of each big footpath chip 3 part of this wafer 30 then and protrude sheet 9.Also can carry on the back mill (grinding) thickness to a certain degree to this wafer 30 in advance.
Preparation is by cutting apart a plurality of path chips 5 that other wafers obtain.The electrode pad of this path chip 5 (diagram is omitted) is provided with and protrudes sheet 9.Just form when protruding the wafer state that sheet 9 both can be before being divided into shaped like chips, also can when chip status, form the protrusion sheet.And these path chips 5 also can just be carried on the back the thickness that is ground to a certain degree in advance when the wafer state before this path chip 5 is cut apart.
On described wafer 30, be coated with the resin 7 of sealing usefulness then.At this moment to adjust the viscosity and the quantity delivered of resin 7, so that when next operation is installed path chip 5 on wafer 30, make resin 7 reach enough height on path chip 5 complete all sidewalls.But the state that the part that will keep connecting line is connected when each big footpath chip 3 of wafer 30 being connected with connecting line of back is exposed from resin 7.
Shown in Fig. 3 (2), path chip 5 is installed on each big footpath chip 3 part of wafer 30 then, and electrode pad (diagram is omitted) separately is electrically connected by protruding sheet 9.Meanwhile full week of the sidewall of path chip 5 is covered enough height, this resin 7 is solidified with the resin 7 that is pre-provisioning on the wafer 30.So just strengthened the mechanical connection (fixing) of 5 pairs of wafers 30 of path chip.This installation for example can use the flip-chip junctor to carry out in turn, like that big footpath chip 3 parts is installed a path chip 5 as shown, or also can a plurality of path chips 5 be installed to big footpath chip 3 parts.
The supply of the resin 7 on wafer 30, both can after protruding on each big footpath chip 3 part that sheet 9 has been connected electrically in path chip 5 wafer 30, carry out, also can path chip 5 is connected electrically on chip 3 parts of big footpath preceding with after both sides carry out.
As long as protrude sheet 9 before described installation, be arranged at least one side of wafer 30 and path chip 5 just can, also can supply between big footpath chip 3 parts and path chip 5 when mounted.
As required, path chip 5 used to the installment state of big footpath chip 3 parts big footpath each electrode pad of chip 3 parts (diagram is omitted) is carried out pin survey after this is installed to carry out evaluation of measuring.
Then shown in Fig. 3 (3); grinding is carried out with back of the body mill apparatus in fitted on the back side to path chip 5 installed surfaces of wafer 30 following back side of path chip 5 of state of the boundary belt 31 that is formed with adhesive linkage (diagram is omitted), makes each path chip 5 slimming on the wafer 30.At this moment the resin 7 that side by side covers path chip 5 perisporiums also is ground and filming simultaneously, as front usefulness Fig. 2 is illustrated, with the face of the back side 5a sustained height of path chip 5 on, resin 7 becomes and has thickness t and surround the path chip states in 5 full weeks (thickness that non-0 certain numerical value is above).This grinding is carried out grinding with 2000# again after for example carrying out grinding with accurate grinding with micro mist granularity 360# earlier.
After the slimming of path chip 5 is finished, boundary belt 31 is peeled off.It also can be the UV gel-type resin that boundary belt 31 is bonded in the adhesive linkage of using on the wafer 30, at this moment 5 slimmings of path chip after by adhesive linkage UV is solidified, just can easily peel off boundary belt 31 from the back side of wafer 30.
As above 5 slimmings of path chip after, as long as need, also can carry out the further slimming of wafer 30 as follows.
At first shown in Fig. 4 (1), on path chip 5 installed surfaces of wafer 30, be fitted in the boundary belt that is formed with adhesive linkage 33 on the thin-film material 35.Shown in Fig. 4 (2), the back side one side usefulness the installed surface of the wafer 30 that usefulness adhesive linkage 33 is covered is carried on the back the mill apparatus grinding, then wafer 30 slimmings.This grinding and front carry out just can with the slimming of the path chip 5 that Fig. 3 (3) illustrates equally.At last adhesive linkage 33 usefulness UV irradiation wait it is solidified after, as Fig. 4 (3), wafer 30 is attached on the cutting blade 39, the adhesive linkage 33 that has solidified is peeled off from wafer 30 with thin-film material 35 is taken off.
Shown in Fig. 4 (4), the wafer 30 that is attached on the cutting blade 39 is cut apart each big footpath chip 3 part that constitutes this wafer 30 then.At this moment use segmenting device, by cutting off action and cut out a plurality of big footpaths chip 3 from wafer 30 along the regional line that is set on the wafer 30.Like this in slimming big footpath chip 3 on by protrude sheet 9 upside-down mountings than its more slimming path chip 5, just can obtain all many core assemblies sheets that has adequately protected with resin 7 of the side of path chip 5 to A.
As shown in Figure 1, on the back welding dish 11 of lead frame, carry out the chips welding of chip after more than finishing to big footpath chip 3 sides of A.At this moment big footpath chip 3 can use general grafting material silver paste etc. with engaging of back welding dish 11.
Then, use the line welder that big footpath chip 3 13 is connected by connecting line 15 with going between.When carrying out line welding,, also can carry out ultraviolet irradiation or plasma treatment to electrode pad for the solder joints of the electrode pad (aluminium electrode) that improves big footpath chip 3.
Then being installed in sealing with in the mould, the substrate that disposes in this dies cavity and path chip 5 and back welding dish 11 and connecting line 15 1 being reinstated sealing resin 17 carry out resin-sealed by back welding dish 11 and lead-in wire 13 lead frames that constitute.At this moment be purpose to improve chip to the sealing of A and sealing resin 17, also can before resin-sealed, carry out ultraviolet irradiation to A or plasma shines chip.
Undertaken by sealing resin 17 resin-sealed after, removing the outer dress of the resin burr of sealing resin 17 and soldering plating etc. handles, afterwards the lead-in wire 13 part bending machining that extend out from sealing resin 17 are become the shape (for example sea-gull spread the wings shape) of regulation, semiconductor packages 1 has just been finished.
According to above-mentioned manufacture method, the adjustment path chip 5 that illustrate by the state of on wafer 30, supplying with resin 7 that illustrate with Fig. 3 (1) and Fig. 3 (2) with Fig. 3 (3) and the degree of resin 7 slimmings, just become with the face of the back side sustained height of path chip 5 on use all full states of resin 7 encirclement path chips 5 with thickness t (thickness more than non-0 the certain numerical value).Therefore in the thickness reducing step of path chip 5 and resin 7, covered by resin 7 and it is difficult to breakage, and bight, the back side also is difficult to breakage in the later operation of path chip 5 slimmings along with bight, the back side.Path chip 5 and big footpath chip 3 are firmly fixed by resin 7.Can seek to improve the accepted product percentage of semiconductor packages 1 like this.Can also seek to improve reliability.And above-mentioned manufacture method need not append manufacturing process and just can implement, thus can suppress the rising of worker ordinal number and manufacturing cost, so can seek to reduce manufacturing cost.
Even when big footpath chip 3 is carried out slimming, also because as illustrating with Fig. 3 (1), be that path chip 5 is installed on the preceding big footpath chip 3 of slimming,, kept the intensity of big footpath chip 3 so guaranteed to install the thickness of the big footpath chip 3 of path chip 5 states.Therefore even when partly carrying out pin test and appraisal valency to semiconductor chip being installed in state on the chip of big footpath carries out confirming operation and to big footpath chip 1a, the breakage that also can not produce big footpath chip 3.
As illustrate like that with Fig. 4 (2), the slimming of big footpath chip 3 be be installed in path chip 5 on the big footpath chip 3 be embedded in the resin 33 following of situation greatly directly the installed surface of chip 3 in planarization carry out under the state.The grinding pressure that is added in chip 3 back sides, big footpath like this when carrying out the slimming of big footpath chip 3 averages out in face, so prevented the crackle by the inhomogeneous big footpath chip 3 that causes of grinding pressure.Therefore can be 3 slimmings fully of big footpath chip.
According to the above, can seek: big footpath chip 3 is not damaged, can fully carry out slimming to the big footpath chip 3 that path chip 5 is installed from the back side, the chip that path chip 5 and the chip 1a upside-down mounting of big footpath are obtained is to A and used the further slimming of this chip to the semiconductor packages 30 of A, with the raising accepted product percentage, cut down manufacturing cost.
By as illustrate with Fig. 4 (1) on the thin-film material 35 first applying resins 33, energy is easily peeled off resin 33 from the big footpath chip 3 as illustrating with Fig. 4 (3) and is taken off.
Add as the necessary equipment of the manufacturing of semiconductor packages 30, flip-chip welding machine, chip welding machine, seam welder, transmission device for molding etc. also all are to utilize the existing equipment of both having deposited, do not need new equipment investment, can suppress production cost cheaply.
Also can be with following order when also implementing the filming of big footpath chip 3.Promptly also can at first as illustrating, be installed in path chip 5 (semiconductor chip) on the wafer 30 with Fig. 3 (1), Fig. 3 (2), carry out behind the confirming operation by the order that illustrates with Fig. 4 (1) and Fig. 4 thereafter (2) slimming of path chip 5 is carried out in wafer 30 slimmings then as illustrating with Fig. 3 (3).In this case owing to also be path chip 5 to be installed in carry out on the slimming wafer 30 before, and by making the path chip 5 that has been installed on the wafer 30 installed surface one side of wafer 30 become the planarization state by imbedding in the resin 33, carry out the slimming of wafer 30 again, so can obtain the effect same with the foregoing description.So long as the order of the foregoing description has just been guaranteed the thickness of the wafer 30 before cutting apart wafer 30, so can further prevent the damage of wafer 30.
In the above-described embodiments as with Fig. 1 explanation, resin molded type semiconductor encapsulation 1 and the manufacture method thereof of using lead frame is illustrated, but so long as use the semiconductor chip upside-down mounting cut apart the right words of the chip that obtains on the chip of wafer just can, be not limited to the semiconductor packages 1 of this form.For example when the ball grid array package (BGA encapsulation) of using substrate and land grid array encapsulate the semiconductor packages manufacturing of arbitrary forms such as semiconductor packages of (LGA encapsulation) or gas-tight seal type, can be suitable for too, can obtain same effect.
Claims (6)
1, a kind of semiconductor packages, possess: substrate, at mounted semiconductor chip on the described substrate and the resin on described substrate, supplied with the state that covers described semiconductor chip side week, it is characterized in that, described resin when the sidewall of described semiconductor chip is covered fully, with the face of this sustained height above semiconductor chip on full week of this semiconductor chip is arranged on the described substrate with the state with the encirclement of thickness ground.
2, semiconductor packages as claimed in claim 1 is characterized in that, described substrate is made of semiconductor chip.
3, semiconductor packages as claimed in claim 1 is characterized in that, described semiconductor chip upside-down mounting is on described substrate.
4, semiconductor packages as claimed in claim 1 is characterized in that, the thickness of described semiconductor chip is than the thin thickness of described substrate.
5, a kind of manufacture method of semiconductor packages is characterized in that, comprising: covering process, its semiconductor chip upside-down mounting and cover full week of the side perisporium of this semiconductor chip on substrate with resin; Thickness reducing step, before the state that on the face that becomes with sustained height above the described semiconductor chip, full week of this semiconductor chip is surrounded with the described resin with thickness, this semiconductor chip and this resin are carried out slimming from this semiconductor chip backside one side.
6, the manufacture method of semiconductor packages as claimed in claim 5 is characterized in that, described substrate is made of the wafer that constitutes with the semiconductor chip before cutting apart.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP278030/2003 | 2003-07-23 | ||
| JP2003278030A JP2005045041A (en) | 2003-07-23 | 2003-07-23 | Semiconductor package and its manufacturing method |
| JP278030/03 | 2003-07-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1577820A true CN1577820A (en) | 2005-02-09 |
| CN100578763C CN100578763C (en) | 2010-01-06 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200410054533A Expired - Fee Related CN100578763C (en) | 2003-07-23 | 2004-07-23 | Semiconductor package and producing method thereof |
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| Country | Link |
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| JP (1) | JP2005045041A (en) |
| CN (1) | CN100578763C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4774999B2 (en) * | 2006-01-18 | 2011-09-21 | ソニー株式会社 | Manufacturing method of semiconductor device |
| KR101719636B1 (en) * | 2011-01-28 | 2017-04-05 | 삼성전자 주식회사 | Semiconductor device and fabricating method thereof |
-
2003
- 2003-07-23 JP JP2003278030A patent/JP2005045041A/en active Pending
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2004
- 2004-07-23 CN CN200410054533A patent/CN100578763C/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| JP2005045041A (en) | 2005-02-17 |
| CN100578763C (en) | 2010-01-06 |
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