CN1568129A - Circuit substrate and manufacturing method thereof - Google Patents
Circuit substrate and manufacturing method thereof Download PDFInfo
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- CN1568129A CN1568129A CN 03148734 CN03148734A CN1568129A CN 1568129 A CN1568129 A CN 1568129A CN 03148734 CN03148734 CN 03148734 CN 03148734 A CN03148734 A CN 03148734A CN 1568129 A CN1568129 A CN 1568129A
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- hole
- circuit substrate
- manufacture method
- sheet material
- metal level
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- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention relates to a circuit baseboard. It includes: a sheet material, plural metal layers and a insulator. The sheet material contains several electric trace layers, and at least one hole formed in the sheet material. The metal layer is formed side panel of the hole and connects to the corresponding electric trace layer. The insulator is formed in the hole to make the metal layer electric independence with each other. Moreover, the invention supplies a method to make the circuit baseboard.
Description
Technical field
The present invention relates to a kind of circuit substrate and manufacture method thereof, particularly a kind of circuit substrate and manufacture method thereof that is applied to integrated circuit.
Background technology
Circuit substrate is an electronic industry base material commonly used now, except be applied to general printed circuit board (PCB) (printing circuit board, PCB) outside, can also be as the substrate (substrate) of integrated circuit structure dress.In recent years, be to adapt to the integrated circuit aggregationization, and the demand of structure packing technique multiwayization, slimming, the electric trace spacing little so develop, and the high-density circuit substrate more than the number of plies.
As shown in Figure 1, circuit substrate 10 mainly comprises a sheet material 100, and sheet material 100 by a core sheet material 101, and multilayer dielectric layer 110, electric trace layer 130 be superimposed to form each other, and each electric trace layer 130 is by guide hole 140 (via), as through hole (through hole), buried via hole (buried via), or blind hole (blind via) connects the signal of each electric trace layer 130.With the through hole is example, it earlier runs through an aperture with the mode of machine drilling or laser drill insulating barrier 110 and the electric trace layer 130 after superimposed, and form a thin copper in the aperture perisporium in the mode of electrodeless plating (electro-less plating), increase thick copper layer to electroplate (electro plating) mode again, at last fill up the insulation material in the space in aperture again, as resin (epoxy).Be provided with hole pad 160 (via land) around the guide hole 140, it is in order to electrically connect electric trace layer 130 and guide hole 140, and generally speaking, if the diameter of guide hole 140 is 300 μ m, then the diameter of hole pad 160 is 500 μ m.In addition, for saving the shared area of hole pad 160, that is the design of non-porous pads (landless), but its process technique and cost are higher.
Yet, as shown in Figure 2,, make the arrangement space of electric trace layer 130 reduce because hole pad 160 can occupy many zones of electric trace layer 130, cause electric trace 130a must design carefullyyer, and both spacings also need more trickle.Therefore, not only increase the degree of difficulty of processing procedure, also have a strong impact on electrical quality, as increasing the problem that signal disturbs.In addition, refer again to Fig. 2,, therefore increase the part of electric trace 130a turnover, that is increase the length in the path of signal transmission because hole pad 160 occupies many spaces of electric trace layer 130.
For addressing the above problem, can directly dwindle the aperture of guide hole 240 and improve.As shown in Figure 3, utilize electricity slurry, Nd:YAG laser, or excite state laser technology such as (excimer laser) forms the guide hole 240 of small-bore, when guide hole 240 apertures dwindle, just can increase the arrangement space of electric trace layer 230, and the part of electric trace 230a turnover is reduced.Yet on the processing procedure of electroplating guide hole 240 hole wall metals, because the aperture is too small, the degree of difficulty of processing procedure can significantly promote.
Summary of the invention
At the problems referred to above, purpose of the present invention is for providing a kind of circuit substrate and manufacture method thereof, and it can increase the wiring density of circuit substrate under the situation of line footpath that does not reduce electric trace and spacing.
Another object of the present invention is for providing a kind of circuit substrate and manufacture method thereof, and it reduces the transmission range of circuit substrate signal.
For reaching above-mentioned purpose, according to circuit substrate provided by the present invention, it includes a sheet material, several metal levels, reaches an insulator.Sheet material has several layers of electric trace layer, and is formed with at least one hole in the sheet material, and these metal levels are formed on the sidewall of hole, and corresponding with it the respectively electric trace layer of these metal levels electrically connects.Insulator is formed in the hole, uses so that these metal levels are electrically independent each other.
In addition, the present invention also provides a kind of manufacture method of circuit substrate, and it includes the following step: at first, provide one to have the sheet material of several layers of electric trace layer earlier, and form at least one hole in this sheet material.Then, form the perisporium of a metal level, form at least one cutting apart in hole again, to cut apart metal level in this hole.At last, clog an insulator in cut apart and hole in.
Because being the metal level that utilizes insulator will be formed at the hole wall, circuit substrate of the present invention is separated into several electrically metal levels independently, so each metal level all can be used as the guide hole that connects each electric trace layer, that is be that function with several guide holes concentrates in the hole.So, just can significantly reduce the shared area of guide hole,, in addition, the part of electric trace turnover is reduced, to shorten the path of signal transmission so that the wiring density of circuit substrate improves.
In addition, the present invention also provides the manufacture method of foregoing circuit substrate, and it is after forming a metal level prior to the hole wall, forms the metal level of cutting apart wall again and is divided into several metal levels, so can form a plurality of guide holes in a hole.So, remove and to avoid directly making the problem that the small-bore hole produces the plating difficulty, more can form a plurality of guide holes apace.
Description of drawings
Fig. 1 is the generalized section of circuit substrate;
Fig. 2 is the vertical view of available circuit substrate;
Fig. 3 is the vertical view of existing another kenel circuit substrate;
Fig. 4 A is the vertical view of circuit substrate of the present invention;
Fig. 4 B is the generalized section of circuit substrate of the present invention;
Fig. 5 A to 5H is the generalized section of the manufacture method of circuit substrate of the present invention;
Fig. 5 I to 5J is the vertical view of the manufacture method of circuit substrate of the present invention.
Symbol description among the figure
10 circuit substrates
100 sheet materials
101 core sheet materials
110 insulating barriers
130 electric trace layers
The 130a electric trace
140 guide holes
160 hole pads
230 electric trace layers
The 230a electric trace
240 guide holes
400 circuit substrates
401 core sheet materials
410 insulating barriers
420 copper foil layers
421 photoresist layers
430 electric trace layers
The 430a electric trace
The 430b electric trace
440 holes
450 metal levels
The 450a metal level
The 450b metal level
451 photoresist layers
460 hole pads
460a hole pad
460b hole pad
470 cut apart
480 insulators
Embodiment
Describe the specific embodiment of the present invention in detail below in conjunction with drawings and Examples.
Fig. 4 A, 4B are the schematic diagram of first preferred embodiment that substrate provided in a circuit according to the invention.In present embodiment, circuit substrate 400 includes a sheet material, at least one hole 440, metal level 450a, 450b, an insulator 480.Sheet material by a core sheet material 401, and number layer insulatings 410, several layers of electric trace layer 430 be superimposed and form.The material of insulating barrier 410 can be two maleic acid vinegar imines (Bismaleimide-Triazine, BT), or FR-4 epoxy resin.Electric trace layer 430 can be by forming a copper foil layer (copper foillayer) in insulating barrier 410 surfaces, on this copper foil layer, form a patterned light blockage layer then, and serve as cover curtain with this photoresist layer, local Copper Foil is removed in etching, through after the removal photoresist layer, just can obtain required electric trace layer 430 again.
The schematic diagram that please refer to Fig. 5 A to 5G is with the manufacture method of explanation according to circuit substrate provided by the present invention.Shown in Fig. 5 A (generalized section), a core sheet material 401 at first is provided, its upper and lower surface is provided with copper foil layer 420.Core sheet material 401 can use material hard and have high glass transition temperature (Glass Transition Temperature, a preimpregnation film (Prepreg) Tg).Shown in Fig. 5 B, on copper foil layer 420, form a photoresist layer 421, through overexposure (exposure), the processes such as (development) of developing, finish design transfer, and then remove partly copper foil layer 420, to obtain electric trace layer 430 (Fig. 5 C) with etching mode.
Shown in Fig. 5 D, be coated with an insulating material on electric trace layer 430 to form an insulating barrier 410.The step that repeats Fig. 5 A, Fig. 5 B and Fig. 5 C is to make the sheet material that is superimposed by multilayer dielectric layer 410 and electric trace layer 430.Then, shown in Fig. 5 E, utilize machine drilling method (mechanical drilling), laser to burn the method (laser ablation) of melting, photochemical reaction method (photochemical reaction) or electric paste etching method (plasma etching) and form hole 440.
Shown in Fig. 5 F, form a metal level 450 in hole 440, and the surface of insulating barrier 410.Because the inwall of hole 440 and the surface of insulating barrier 410 mainly are the composite materials of non-conductor, event must make the tool catalysis characteristics earlier " palladium " be attached on the hole wall surface, form a thin copper layer with wireless plating technology in the wall of hole 440 and the surface of insulating barrier 410 again, the about 0.5 μ m of the thickness of this thin copper layer.Then, again with general galvanoplastic thickening thin copper layer, to form metal level 450, the about 20 μ m of its thickness.In addition, also can utilize Direct Electroplating method (direct plating) to form metal level 450.The Direct Electroplating method is surface applied one conducting polymer film (conductive polymer) or the conductive carbon dust layer prior to the wall of hole 440 and insulating barrier 410, forms metal level 450 with galvanoplastic again.
Shown in Fig. 5 G, carry out little shadow definition processing procedure, it is to form a photoresist layer 451 on insulating barrier 410 lip-deep metal levels 450, carry out patterning with the exposure imaging technology then, and serve as cover curtain with the photoresist layer behind the patterning 451, local Copper Foil is removed in etching, remove photoresist layer 451 more at last after, just can make electric trace layer 430 and hole pad 460 (as Fig. 5 H).Hole pad 460 is formed at the outer rim of hole 440, and generally speaking, when the diameter of hole 440 was 300 μ m, then the diameter of hole pad 460 was about 500 μ m.
Then, shown in Fig. 5 I (hole vertical view), the method for melting of utilizing laser to burn forms cuts apart 470, and wherein laser burns and melts the method kind and can be carbon dioxide laser (CO
2Laser), the ruby laser of neodymium-doped (Nd:YAG Laser), and excite state laser (Excimer Laser).In addition, can also the machine drilling method, laser burns and melt method, photochemical reaction method or electric paste etching method, form and cut apart 470.Cut apart 470 with hole 440 separated into two parts, wherein except that the metal level 450 of hole 440 walls is divided into two parts (metal level 450a, 450b), hole pad 460 also is divided into two parts ( hole pad 460a, 460b).
Shown in Fig. 5 J, fill an insulator 480, as epoxy resin, in hole 440, so that all fill up insulator 480 in the hole 440.Insulator 480 is in order to isolating metal level 450a, the 450b of hole 440 walls, and makes both mutually for electrically independent, and metal level 450a, 450b are electrically connected with electric trace 430a, 430b respectively.
In sum, the present invention has following advantage:
1. circuit substrate of the present invention, be that the metal level that utilizes insulator will be formed at the hole wall is separated into several electrically metal levels independently, so each metal level all can be as the guide hole that connects each electric trace layer, that is be that function with several guide holes concentrates in the hole.So, just can significantly reduce the shared area of guide hole,, in addition, the part of electric trace turnover is reduced, to shorten the path of signal transmission so that the wiring density of circuit substrate relatively improves.
2. the manufacture method of circuit substrate of the present invention is that the metal level of cutting apart wall with formation is divided into several metal levels again after forming a metal level prior to the hole wall, so can form a plurality of guide holes in a hole.So, remove and to avoid directly making the problem that the small-bore hole produces the plating difficulty, more can form a plurality of guide holes apace.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this operator; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion as the scope person of defining that look claims.
Claims (24)
1. a circuit substrate is characterized in that, comprises:
One sheet material has several layers of electric trace layer, and is formed with a hole in this sheet material at least;
Several metal levels are formed on the sidewall of this hole, and these metal levels electrically connect with corresponding electric trace layer respectively; And
At least one insulator is formed in this hole, uses so that these metal levels are electrically independent each other.
2. circuit substrate as claimed in claim 1 is characterized in that, more comprises:
Several hole pads, around the periphery of this hole, and corresponding these metal levels are provided with.
3. circuit substrate as claimed in claim 1 is characterized in that, this hole is a through hole.
4. circuit substrate as claimed in claim 1 is characterized in that, this hole is a buried via hole.
5. circuit substrate as claimed in claim 1 is characterized in that, this hole is a blind hole.
6. circuit substrate as claimed in claim 1 is characterized in that, the material of this metal level is a copper.
7. circuit substrate as claimed in claim 1 is characterized in that, the material of this first insulator is an epoxy resin.
8. circuit substrate as claimed in claim 1 is characterized in that, this sheet material by number layer insulatings and these electric trace layers be superimposed each other form.
9. circuit substrate as claimed in claim 1 is characterized in that, these hole pads are made of copper.
10. the manufacture method of a circuit substrate is characterized in that, comprises step:
(a) provide a sheet material;
(b) form at least one hole in this sheet material;
(c) form a metal level in the perisporium of this hole;
(d) form at least one cutting apart in this hole, to cut apart this metal level; And
(e) filling one insulator is in this hole and this are cut apart.
11. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, more form a hole pad in step (c) on this sheet material, and this hole pad is positioned at the periphery of this hole.
12. the manufacture method of circuit substrate as claimed in claim 11 is characterized in that, this is cut apart and also cuts apart this hole pad in step (d).
13. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, this hole is a through hole.
14. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, this hole is a buried via hole.
15. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, this hole is a blind hole.
16. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, this metal level is made of copper.
17. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, the material of this insulator is an epoxy resin.
18. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, this sheet material is made of number layer insulatings and the several layers of electric trace layer institute that is superimposed each other.
19. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, this metal level forms a film with an electrodeless plating method in the perisporium of this hole earlier, again this film is carried out galvanoplastic and forms.
20. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, this metal level forms a conducting polymer film prior to the perisporium of this hole, carries out galvanoplastic again and forms.
21. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, this is cut apart with a machine drilling method and forms.
22. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, this is cut apart and burns the method for melting with a laser and formed.
23. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, this is cut apart with a photochemical reaction method and is formed.
24. the manufacture method of circuit substrate as claimed in claim 10 is characterized in that, this is cut apart with an electric paste etching method and is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03148734 CN1568129A (en) | 2003-06-24 | 2003-06-24 | Circuit substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03148734 CN1568129A (en) | 2003-06-24 | 2003-06-24 | Circuit substrate and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1568129A true CN1568129A (en) | 2005-01-19 |
Family
ID=34472362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03148734 Pending CN1568129A (en) | 2003-06-24 | 2003-06-24 | Circuit substrate and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1568129A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378933C (en) * | 2005-03-14 | 2008-04-02 | 日月光半导体制造股份有限公司 | Method for manufacturing a semiconductor package with a laminated chip cavity |
| US8104171B2 (en) | 2008-08-27 | 2012-01-31 | Advanced Semiconductor Engineering, Inc. | Method of fabricating multi-layered substrate |
| CN104703412A (en) * | 2015-04-07 | 2015-06-10 | 深圳市化讯应用材料有限公司 | Method for metallizing hole |
-
2003
- 2003-06-24 CN CN 03148734 patent/CN1568129A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378933C (en) * | 2005-03-14 | 2008-04-02 | 日月光半导体制造股份有限公司 | Method for manufacturing a semiconductor package with a laminated chip cavity |
| US8104171B2 (en) | 2008-08-27 | 2012-01-31 | Advanced Semiconductor Engineering, Inc. | Method of fabricating multi-layered substrate |
| CN104703412A (en) * | 2015-04-07 | 2015-06-10 | 深圳市化讯应用材料有限公司 | Method for metallizing hole |
| CN104703412B (en) * | 2015-04-07 | 2016-04-13 | 深圳市化讯应用材料有限公司 | A kind of method of hole metallization |
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |