CN1567979A - Television receiver - Google Patents
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- CN1567979A CN1567979A CN 03145705 CN03145705A CN1567979A CN 1567979 A CN1567979 A CN 1567979A CN 03145705 CN03145705 CN 03145705 CN 03145705 A CN03145705 A CN 03145705A CN 1567979 A CN1567979 A CN 1567979A
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Abstract
The invention is a television receptor, especially relates to the parallel and vertical scanning system design about the television receptor. The parallel synchronous frequency and vertical synchronous frequency of the television are increased to 1.5 times, in two scan times of traditional one, now it can scans for three times, thus the flash of picture can be reduced.
Description
Technical field
The present invention is a kind of television receiver, particularly about the design of the level and the vertical scan system of television receiver.
Technical background
The display flicker problem of television set, be because low picture sweep speed, promptly be a per second 50-60 picture (50Hz～60Hz), this problem came into question many years, particularly some the national spectators in the television system of 50 pictures of per second (50Hz PAL) are perplexed by this problem, spectators' eyes must be stood the harmful effect of TV flicker, if just relatively good as the television system of picture scanning frequency with 60 pictures of per second (60Hz).Common TV even if improve the TV esolving degree and improve media content, still exists irritating flicker problem, and this flicker problem is a major defect of traditional tv.The modern science and technology suggestion improves the quality of display; hd-tv (High Definition Television for example; HDTV); promote the new standard set up jointly by government and industry leader; but this process but is very slowly, and its reason is to be price that still immature capital construction, industry program content are comprehensive, not expensive as yet and still unsolved modulation standard or the like.
Another one proposes it is to adopt vertical renewal rate of double frequency or continous way scanning line by line, for example " 100i " system (100Hz alternating expression) or " 60p " (60Hz is continous way line by line) system, these systems need expensive element and set up a new framework, comprised cathode ray tube (cathode ray tube, CRT) and the renewal of other control circuit, these systems since selling at exorbitant prices be difficult for being accepted by the consumer.
Summary of the invention
One of purpose of the present invention is to reduce the flicker of television image;
Two of purpose of the present invention is under traditional television transmission standard, NTSC for example, and PAL and SECAM reduce the flicker of television image;
Three of purpose of the present invention is to reduce the flicker of television image and do not increase too many cost.
These purposes can be reached with the scanning frequency that improves television image, this can improve the number of pictures of per second via improving the standard scanning frequency and vertical scanning frequency, just can reduce the flicker of picture, simultaneously, the signal of video signal of each bar scan line must remain unchanged.Just must reduce the residence time of each picture element (pixel) on each horizontal scanning line, and reduce each image time.(just improving the number of pictures in each second).
In order to reduce the flicker of television indicator, design of the present invention is exactly the TV synchronousing signal that adopts 1.5 times of standard frequencies, and in the PAL system, or the vertical scanning frequency that produces 89.91Hz is in the NTSC system in order to the vertical scanning frequency that produces 75.00Hz.1.5 overtones band is in the selection of lowering the better balance between flicker and the price.
The present invention is except adopting 1.5 frequencys multiplication, and remaining Synchronous Processing all standard television with traditional is identical.Cathode ray tube (cathode ray tube, CRT) still can use general standard television cathode ray tube now, simultaneously, the design of the employed horizontal deflection circuit of conventional television, at NTSC, also consistent in PAL and the SECAM different system, need not change, simultaneously, cost is then very nearly the same with existing TV horizontal deflection circuit.The advantage of a uniqueness of the present invention is that the television receiver for all sizes has applicability, for example most popular family expenses 25 "～36 " TV.These television sets do not have the high image quality system usually, because hd-tv needs the display screen of large-size, usually greater than 40 " so that appreciate the image quality of High Resolution.
The framework that the present invention is same, can certainly extend use at hd-tv, yet, the cost of hd-tv system can increase many, this be since the price of the needed scanning of continous way line by line of the needed multiple frequency of synchronous scanning, cathode ray tube (CRT) and high-res high due to.
As for detailed construction of the present invention, application principle, effect and effect, then the explanation of doing with reference to following adjoint can be understood completely:
Description of drawings
Fig. 1 is the running calcspar that shows traditional television receiver;
Fig. 2 shows that the present invention changes the basic flow sheet of horizontal frequency;
Fig. 3 A is reveal competence synchronizing signal and vertical synchronizing signal sequential chart＜NTSC or PAL (M) sequential chart 〉;
Fig. 3 B be reveal competence synchronizing signal and vertical synchronizing signal sequential chart＜PAL (I, B, G, H, D, N) or the SECAM sequential chart;
Fig. 4 shows television receiver calcspar of the present invention;
Fig. 5 shows to use the image processing chip of the present invention in general television set;
Fig. 6 is a show image process chip calcspar;
Embodiment
The present invention is in order to reduce the flicker of television image display, go for the hardware configuration of general now standard TV receiver, do not need consumer payment as the progressive-scan tv or the price of the costliness of hd-tv, be compatible to television broadcasting standard now again.
Television set calcspar now as shown in Figure 1, comprise adjuster 10, medium amplifier 11, voice decoder 12 is in order to decoding frequency modulation message, Sound Processor Unit 13 is in order to handle modulating signal, and sound intensifier 14 is in order to the voice emplifying signal and drive sound amplifier (TV loudspeaker) 15.Image processing partly comprises image decoding device 16 to be made in order to the signal of video signal of conversion amplitude modulation scan line and becomes digital date, and generation horizontal sync frequencies Fh and vertical synchronizing frequency Fv, these frequencies all are according to NTSC, PAL and SECAM standard are in order to produce staggered signal of video signal, that is corresponding respectively under 50Hz or the sampling rate of 60Hz, and each picture produces 525 or 625 scan lines.These digital dates can be handled in image processor 17, and change and the generation anaiog signal, and these signals are amplified by image amplifier 18, so that drive cathode ray tube 19.Image-decoding device 16 produces the synchronizing signal of separating, and in order to feed-in image synchronous processing device 20, cathode ray tube 19 deflection yokes are controlled via deflection output stage 22.Each picture comprises odd field and even field with half interlacing of sweep speed.
Cardinal principle of the present invention is the scanning frequency that increases picture, and this purpose can be reached via improving the standard scanning frequency and vertical scanning frequency.When the number of pictures of per second increased, the interval between picture and the picture shortened, thereby improved because the caused flicker problem of vertical scanning slowly.
With scanning frequency and the vertical scanning frequency of improving the standard, the scanning frequency that improves whole image is to lower flicker in the present invention.Yet the signal of video signal of each horizontal scanning line must be integrated.Each bar horizontal scanning line is made of many pixels, via the residence time that shortens each pixel, just can reduce the sweep time of horizontal scanning line, that is to say that horizontal frequency must improve.Similarly, vertical scanning is (for example the scanning of each even number of NTSC system or the picture of odd-numbered scan lines has 262.5 scan lines) that is made of many scan lines.Via the sweep time that shortens each horizontal scanning line, the needed time of each vertical scanning just can shorten.
When vertical scanning frequency was increased to 1.5 times, the time of picture scanning had just reduced, and the time of twice traditional scanning picture can provide three scanning, and the flicker of reduction picture.Because flicker be since slowly scanning frequency near or be lower than the cause of the limit that persists susceptibility of human eyes, so, just can reduce the problem of image flicker widely as long as improve number of pictures in the unit interval.
In the present invention, all input signals all are the signals of standard, comprise NTSC, PAL and SECAM signal, and they have the specification of following horizontal sync frequencies Fh and vertical synchronizing frequency Fv respectively:
NTSC：Fh＝15.734KHz，Fv＝59.94Hz
PAL(I，B，G，H，D，N)：Fh＝15.625KHz，Fv＝50.00Hz
SECAM：Fh＝15.625KHz；Fv＝50.00Hz
The present invention increases by 1.5 times of horizontal sync frequencies and vertical frequencys, and Fig. 2 shows frequency shift calcspar of the present invention.Voice signal wherein is in different FREQUENCY CONTROL, so separated coming handled in addition.
It is necessary that the present invention comprises scan rate conversion, and can change simultaneously the image format of receiving becomes and want the form that shows, and number and pixel clock pulse frequency with the image output scan line are designed in the image processor of programmable.
The Fh and the Fv of the present invention's redesign produce following specification:
NTSC：Fh＝23.601KHz，Fv＝89.91Hz
PAL(I，B，G，H，D，N)：Fh＝23.4375KHz，Fv＝75.00Hz
PAL(M)：Fh＝23.601KHz，Fv＝89.91Hz
SECAM：Fh＝23.4375KHz，Fv＝75.00Hz
The change execution mode of synchronizing frequency as shown in Figure 2, image decoding device 16 is through the A/D switch technology, the transformational analogy signal of video signal makes becomes digital date.The digital image data is corresponding to each pixel on the horizontal scanning line, be written to memory body in the picture buffer 28 to preserve the image digital date via data path 27, the digital date that is stored in the picture buffer 28 is read with clock pulse speed faster, be converted into the analogy signal of video signal then in reading data blocks 31 in order to drive cathode ray tube, therefore, in order to the time than the horizontal scanning line of input of becoming sweep time of the horizontal scanning line that shows for short.The input level synchronizing signal of controlling the scan line time of next time turning back is written among the picture buffer, is transformed into a fast new synchronizing signal of synchronizing signal than input through display control circuit then.Similarly, in order to control the vertical synchronizing signal of the input of the reciprocal time of vertical scanning each time, also be converted into a synchronizing signal faster.
The clock pulse that reads data in the picture buffer memory body is produced by clock pulse generator 32, this is a frequency generator, it is to use a quartzy oscillator as reference frequency and phase locked loop, in order to produce a different new clock pulse and a synchronizing frequency.The output frequency of frequency generator is controlled by programmable buffer 36, and it is the frequency division in order to the voltage-controlled oscillator in the decision frequency generator, in order to produce NTSC, PAL or the needed new frequency of SECAM-system.In cathode ray tube sequencing control block, it is to read control block 26 feed-in clock pulse frequencies in picture buffer via a picture buffer to the signal that comes from clock pulse generator 32 by feed-in; And produce new display horizontal sync frequencies 23.601kHz (being used in the NTSC signal) and new vertical synchronizing frequency 89.91Hz (being used in the NTSC signal).Horizontal-drive signal is produced by pixel counter 33, it is in comparison blocks 35, calculate the number of the pixel of each scan line, in order to be compared to the counting of the Fh of decision in advance, so that begin and stop block 34 in horizontal synchronization, the turning back and restart of controlling level scanning.Similarly, vertical synchronizing signal is produced by scan line counter 37, it is to calculate the number of scanning lines of vertical scanning each time, in order to being compared in comparison blocks 39 the Fv counting of decision in advance, begin and stop the turning back and restart of vertical scanning in the block 38 in order to the control vertical synchronization.New synchronizing signal sequential chart is compared to traditional synchronizing signal, and NTSC standard and Fig. 3 B show the PAL standard as shown in Figure 3A.
Improve the horizontal synchronization of television receiver and the plan of vertical synchronization, it is the image processor block 47 that is contained in based on picture, as a television receiver block, as Fig. 4. shown in, the further feature that has also comprised the advance TV receiver based on the image processor block 47 of picture, as shown in Figure 5, these features comprise the image camera, VCR, PC-VGA, the MPEG image, digital image interface (Digital Visual Interface, the DVI) input of image, the input signal of all these application, all be to adopt traditional form, NTSC for example, PAL or SECAM, and handle as shown in Figure 2 in an identical manner.The calcspar of image processor block 47 of the present invention, as shown in Figure 5, this block is an image processor based on picture, is approximately 23.5KHz Fh synchronous processing device in order to generation, and corresponding Fv uses so that NTSC, PAL and SECAM-system to be provided; The main change is the image processor that replaces in traditional television receiver, as shown in Figure 1, have picture for the image processor on basis in order to produce synchronizing signal.
The present invention is based on the image processor of picture, be a system single chip (System-On-Chip, SOC), use advanced CMOS field to imitate the brilliant pipe of electricity (complementary metal oxide semiconductor, CMOS) hybrid signalling technique, combine alternating expression to scanning of continous way line by line and the conversion that is returned to alternating expression, but the amplification of program or dwindle, cathode ray tube timing sequence generating and many other image processing skills.Principal character of the present invention is the synchronizing frequency with 1.5 times, the about 25mm of die size
2Use CMOS 0.18um or 0.25um technology, this needs 4M Byte, 8M Byte, or the picture buffer of 16M Byte bit.Fig. 6 shows the functional block diagram based on the image processor block 47 of picture.
Functional description based on the image processor block 47 of picture is as follows:
1.MCU I/F (MCUIF): microprocessor (MCU) interface provides a device, so that internal key or outside low-cost CPU and firmware, link up with wafer, in order to set the configuration buffer, it moved, make the variation of signal of video signal string, can be written to picture buffer via the memory body moderator ... or the like, this has comprised display control and I2C serial bus on the screen.
2. buffer: buffer resides among all need the block of buffer, this has comprised configuration and control buffer, these buffers use MCU via the I2C bus access it, its objective is in order among each block, to isolate other buffer, so that the optimization of IC layout aspect, and avoid the congested of layout path, it is a path congestion of having only a central buffer block in order to be compared to.
3. (video input port, VIP): image input port provides different interfaces of numerical digit decoder, perhaps selects as an integrated image-decoding device of internal key at image input port.Image information string has comprised two ports of image-decoding device output, the output of numerical digit RGB, YCbCr, YPbPr and DVI receiver.This has comprised the conversion of bus-bar width and brightness and color phasetophase, so that image writing to the picture buffer memory body.
4. image-decoding device (CVD): the preferable mode of internal key image-decoding device is to take outside adjuster output, comprises composite or S terminal signals, produces the digital YUV signal that inner image input port needs then.The image-decoding device preferably comprises the filtration of digital 3D pectination and the captions or the decoding of information string.
5.ADC: have the output that two cover ADC receive two groups of tuners, so that SOC can support picture-in-picture (picture in picture in the image input source, PIP) or picture segmentation (picture on picture, POP), wherein need at least one group of high-speed ADC so that handle the signal source that high speed image-decoding device or YPbPr/RGB etc. line by line scan.
6. memory controller (MIU): memory controller provides the priority memory access control of picture buffer memory body.But the memory body arbitration is carried out in conjunction with the length of the cycle of program according to fixing priority.The renewal of memory body circulation is to provide during for blank interval by its clock internal counter 512 or by video signal scanning.
7. (on-screen display, OSD) write block: this block comprises the data of display control on the screen to screen control display box, is written to the display memory body.Screen control display box data can be with literal as the basis or based on the data of image, write screen control display box data and enter memory body, show that then control circuit can control screen the size of display box and amplify or dwindle processing.
8. drawing engine (GFX): this block provides 64-bit 2D image to quicken, and this has comprised the engine etc. of bit block conversion (BitBLT) and setting-out, and it can finish the action of a drawing for order in each clock pulse interval.Keep these blocks as the skip use of function of interactive TV or the guiding of the sequencing of electronic program list based on the image processor block 47 of picture.
9. screen control display box (OSD) control: hardware OSD controls reading of block processes OSD portrait memory body, flicker transparency and mixing.
10. display/image first in first out: image covers the first in first out block, handles the access that the memory body of image overlap reads, and comprises image information string, picture-in-picture (PIP) or the divided frame (POP) of OSD.Scan rate conversion and removal alternating expression function also need buffer is read access.
11. image pipeline: this block comprises the needed image in pixel path or image shows (video graphic adaptor, VGA) compatibility logic; Comprised the VGA property control, and the conversion of permission OSD, PIP and the covering of numerical digit RGB bit string.
12. color saucer: this block comprises two cover SRAM, and a cover is used in the Gamma control that shows output, and an other cover is used in the OSD image of storage based on image.
13. image pipeline: the image pipeline is carried out image and is quickened, control and mixed function.These functions comprise: the change in size of the setting of PIP imaging window, POP, colour pase conversion, X and Y image, and for example: 4: 3,16: 9, panorama, amplification dwindle, remove alternating expression, picture-rate transition; And use image 1 and image 2 first in first out (FIFO) so as to store present and handle in the scan line image data of vertical insertion.
14. display conduit: this block merges display box (OSD) on elementary image demonstration, covering and the screen.Comprise that luminance signal and color signal control, color conversion, Gamma control, black position are accurately adjusted, brightness/contrast is adjusted, the white accurate fine setting in position, color, saturation level and cover picture and mix ... or the like high picture processing, all in this block processes.
15. cathode ray tube control (CRTC): the position that shows (OSD) on synchronizing signal, covering and the screen that this CRTC block control shows.
16. (audio lip sync, ALS): this block comprises the pipeline stages control that voice signal is aimed at the needed synchronous circuit of image output information string to the sound lip synchronously.
17.DAC: this block comprises the numerical digit of RGB monitor to analogy converter.Operation voltage with 3.3V can operate 170Mhz.
18.PLL: this block comprise memory body the time pulse-phase locked loop and display pixel clock generation.
19. clock pulse: this block comprises clock pulse activation, multiplexer and buffer, and memory body, pixel, bus and image port clock pulse are provided.
20. energy conservation: this block comprises the control of different energy conservation characteristics.
21. test circuit: this block comprises test circuit, and the battery logic and the scan line buffer device/static random-access logic of standard is provided.
The above only is a preferred embodiment of the present invention, is not to be used for limiting scope of the invention process.Be that all equalizations of being done according to the present patent application claim change and modification, be all the contained lid of claim of the present invention.
Claims (11)
1. television receiver in order to receive traditional standard television signals such as NTSC, PAL or SECAM, comprises: treatment circuit, and that handles input has an amplitude modulation signal of video signal so that show an image at cathode ray tube; And have a horizontal-drive signal, a vertical synchronizing signal, in order to horizontal deflection yoke that drives aforesaid cathode ray tube respectively and the composite signal of vertically being partial to yoke; And conversion equipment, in order to the horizontal frequency (Fh) and the vertical scanning frequency (Fv) of the TV signal of transfer standard, to a higher horizontal frequency (Fh) and higher vertical scanning frequency (Fv), so that reduce the flicker of image; The TV signal of aforesaid standard is meant: traditional standard television signals such as NTSC, PAL or SECAM.
2. television receiver as claimed in claim 1 is characterized in that: wherein said higher scanning frequency Fh and Fv are that original scanning frequency be multiply by 1.5 times.
3. television receiver as claimed in claim 2 is characterized in that: wherein said Fh is changed by 59.94Hz by 15.734kHz change becoming 23.601kHz and Fv and becomes the use that 89.91Hz is matched with the NTSC modular system; Described Fh becomes 75.00Hz by 15.625kHz change becoming 23.4375kHz and Fv by the 50.00Hz change and is matched with PAL (I, B, G, H, D, N) use of modular system; Described Fh is changed by 59.94Hz by 15.734kHz change becoming 23.601kHz and Fv and becomes the use that 89.91Hz is matched with PAL (M) modular system; Described Fh is changed by 50.00Hz by 15.624kHz change becoming 23.4375kHz and Fv and becomes the use that 75.00Hz is matched with the SECAM modular system.
4. television receiver as claimed in claim 3 is characterized in that: needed time of twice scanning of the picture of standard wherein, becoming at one time is three scanning.
5. television receiver as claimed in claim 1 is characterized in that: wherein said conversion equipment comprises:
A decoder is converted into digital date with each picture element (pixel) in the described horizontal scanning line with the AM signal of video signal that the analogy kenel exists;
One first clock pulse in order to described digital date, is displaced in the series connection memory body;
One second clock pulse faster than described first clock pulse, is stored in the described digital date of described series connection memory body in order to read;
One first counter, in order to calculate on the scan line number of pixels, and in order to produce one second horizontal-drive signal, so that the horizontal yoke of number before driving;
One second counter, in order to the number of scanning lines of calculating scanning, and in order to produce one second vertical synchronizing signal, so that drive described vertical yoke;
A numerical digit is changeed analogy converter, in order to will come from described series connection memory body digital date, is converted into anaiog signal, drives described cathode ray tube; And
Clock pulse generator provides described first clock pulse and described second clock pulse.
6. television receiver as claimed in claim 5, it is characterized in that: wherein said clock pulse generator is to come from a frequency generator to produce, and comprises a quartzy oscillator of reference, phase locked loop, but and the buffer of a program, in order to planning clock generator frequency.
7. television receiver as claimed in claim 1, it is characterized in that: more comprise auxiliary circuit in order to be in harmonious proportion image video camera, Video Recorder, computer, interconnecting device or DVI connector, so that its signal of video signal goes for one of following television standard system: NTSC, PAL and SECAM-system.
8. television receiver as claimed in claim 7 is characterized in that: the device of wherein said auxiliary circuit and described raising Fh and Fv is to be contained among the System on Chip/SoC (SOC).
9. television receiver as claimed in claim 8 is characterized in that: wherein said System on Chip/SoC (SOC) comprises:
(1) MCUI/F (MCUIF): microprocessor (MCU) interface provides a device, so that internal key or outside low-cost CPU and firmware, link up with wafer, in order to set the configuration buffer, it moved, make the variation of signal of video signal string, can be written to picture buffer via the memory body moderator. or the like, this has comprised display control and I on the screen
2The C bus-bar of connecting;
(2) buffer: buffer resides among all need the block of buffer, and this has comprised configuration and control buffer, and these buffers use MCU via I
2The access of C bus-bar it, its objective is that in order among each block, to isolate other buffer so that the optimization of IC layout aspect, and avoid the congested of layout path, it is a path congestion of having only a central buffer block in order to be compared to;
(3) (video input port, VIP): image input port provides different interfaces of numerical digit decoder, perhaps selects as an integrated image-decoding device of internal key at image input port.Image information string has comprised two ports of image-decoding device output, the output of numerical digit RGB, YCbCr, YPbPr and DVI receiver, and this has comprised the conversion of remittance current drainage width and brightness and color phasetophase, so that image writing to picture buffer note note body;
(4) image-decoding device (CVD): the preferable mode of internal key image-decoding device is to take outside adjuster output, comprise composite or S terminal signals, produce the numerical digit YUV signal that inner image input port needs then, the image-decoding device preferably comprises the filtration of digital 3D pectination and the captions or the decoding of information string;
(5) ADC: have the output that two cover ADC receive two groups of tuners, so that SOC can support picture-in-picture (picture in picture in the image input source, PIP) or picture segmentation (picture on picture, POP), wherein need at least one group of high-speed ADC so that handle the signal source that high speed image-decoding device or YPbPr/RGB etc. line by line scan;
(6) memory controller (MIU): memory controller provides the priority memory access control of picture buffer memory body.But memory body arbitration is carried out in conjunction with the length of the cycle of program according to fixing priority, and the renewal circulation of memory body is to provide during for blank interval by its clock internal counter 512 or by video signal scanning;
(7) screen control display box (on-screen display, OSD) write block: this block comprises the data of display control on the screen, be written to the display memory body, screen control display box data can be with literal as the basis or based on the data of image, write screen control display box data and enter memory body, show that then control circuit can control screen the size of display box and amplify or dwindle processing;
(8) drawing engine (GFX): this block provides 64-bit 2D image to quicken, this has comprised the engine of bit block conversion (BitBLT) and setting-out. etc., it can be in each clock pulse interval, finish the action of a drawing for order, keep these blocks as the skip use of function of mutual fortune formula TV or the guiding of the sequencing of electronic program list based on the image processor block 47 of picture;
(9) screen control display box (OSD) control: hardware OSD controls reading of block processes OSD image internal memory, flicker transparency and mixing;
(10) display/image first in first out: image covers the first in first out block, the access that the memory body of processing image overlap reads, the image information string that comprises OSD, picture-in-picture (PIP) or divided frame (POP), scan rate conversion and removal alternating expression function also need buffer is read access;
(11) image pipeline: this block comprises the needed image in pixel path or image shows (video graphic adaptor, VGA) compatibility logic; Comprised the VGA property control, and the conversion of permission OSD, PIP and the covering of numerical digit RGB bit string;
(12) color saucer: this block comprises two cover SRAM, and a cover is used in the Gamma control that shows output, and an other cover is used in the OSD image of storage based on image;
(13) image pipeline: the image pipeline is carried out image and is quickened, control and mixed function.These functions comprise: the change in size of the setting of P1P imaging windows, POP, colour pase conversion, X and Y image, and for example: 4: 3,16: 9, panorama, amplification dwindle, remove alternating expression, picture-rate transition; And use image 1 and image 2 first in first out (FIFO) so as to store present and handle in the scan line image data of vertical insertion;
(14) display conduit: this block merges display box (OSD) on elementary image demonstration, covering and the screen.The high picture processing that comprises luminance signal and color signal control, color conversion, Gamma control, the accurate adjustment in black position, brightness/contrast adjustment, the white accurate fine setting in position, color, saturation level and cover picture mixing or the like is all in this block processes;
(15) cathode ray tube control (CRTC): the position that shows (OSD) on synchronizing signal, covering and the screen that this CRTC block control shows;
(16) the sound lip synchronously (audio lip sync, ALS): this block comprises the pipeline stages control that voice signal is aimed at the needed synchronous circuit of image output information string;
(17) DAC: this block comprises the numerical digit of RGB monitor to analogy converter, and the operation voltage with 3.3V can operate 170Mhz;
(18) PLL: this block comprise memory body the time pulse-phase locked loop and display pixel clock generation;
(19) clock pulse: this block comprises clock pulse activation, multiplexer and buffer, and memory body, pixel, bus and image port clock pulse are provided;
(20) energy conservation: this block comprises the control of different energy conservation characteristics;
(21) test circuit: this block comprises test circuit, and the battery logic and the scan line buffer device/static random-access logic of standard is provided;
10. one kind receives NTSC, and the PAL or the television image of SECAM-system reduce the method for glimmering, and comprise following step:
The RF TV signal of tuner conversion input becomes an IF-FRE (IF) signal; Produce the video signal of analogy again;
Through video decoded device, the signal of video signal of the pixel of each bar horizontal scanning line of television image is converted into digital date;
With one first clock pulse speed,, write and enter the series connection memory body described digital date;
With second a clock pulse speed that is higher than first clock rate of preceding number, read described digital date;
The digital date that comes from the described series connection memory body is read in conversion becomes analog signal, shows described television image to become; And after a number of horizontal scanning line altogether that determines in advance of described picture, increase the scanning frequency of each picture of described picture.
11. television receiver as claimed in claim 1 is characterized in that: wherein said second clock speed is 1.5 times for first clock rate, and vertical scanning is in twice sweep time by the standard picture, to carry out three scanning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03145705 CN1567979A (en) | 2003-06-23 | 2003-06-23 | Television receiver |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03145705 CN1567979A (en) | 2003-06-23 | 2003-06-23 | Television receiver |
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| CN1567979A true CN1567979A (en) | 2005-01-19 |
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| CN 03145705 Pending CN1567979A (en) | 2003-06-23 | 2003-06-23 | Television receiver |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111815744A (en) * | 2020-07-31 | 2020-10-23 | 广东汕头超声电子股份有限公司 | Signal display method of eddy current detector |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111815744A (en) * | 2020-07-31 | 2020-10-23 | 广东汕头超声电子股份有限公司 | Signal display method of eddy current detector |
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