CN1567754A - Apparatus and method for implementing automatic detection of communication interface time sequence - Google Patents
Apparatus and method for implementing automatic detection of communication interface time sequence Download PDFInfo
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- CN1567754A CN1567754A CNA031456014A CN03145601A CN1567754A CN 1567754 A CN1567754 A CN 1567754A CN A031456014 A CNA031456014 A CN A031456014A CN 03145601 A CN03145601 A CN 03145601A CN 1567754 A CN1567754 A CN 1567754A
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Abstract
The invention advances a method and device of implementing automatic detection of time sequence of communication interface, containing the steps: receiving interface signal at the detected interface; processing the received interface signal to obtain a new signal and related data; triggering corresponding time sequence and then detecting the new signal and related data; judging the detected result: if it meets the requirements, continue the course of emulating and normally detecting and otherwise stop the course or wait for the time sequence to resume and continue the course. Before triggering corresponding time sequence for detecting, it further contains: judging if the new signal and related data are at the key moment: if they are, output related information.
Description
Technical field
The invention belongs to communication field, be specifically related to a kind of apparatus and method that realize that the communication interface sequential detects automatically.
Background technology
The general employing to logic of extensive logical simulation checking sends excited data, receives through the data after this logical process then, and whether correct, reach the purpose that verifying logic is handled correctness if reexamining the data that receive.In emulation, the reception of data and send needs all that (BusFunction Model: bus functional model) carry out, BFM carries out the generation and the identification of interface sequence, thereby finishes the transmission of data by BFM.Sequential standard, normal that BFM generally only pays close attention to is only paid close attention to the data that can normally transmit.But because the complexity of communication interface standard, BFM (or logic) has received correct data and has not represented the complete protocol compliant standard of logic interfacing sequential, wherein has the standard of violating the agreement part.In addition, when the logic interfacing of defectiveness is docked with other company's chip, may in the long-play process, mistake occur, and reason is difficult to look into.And, also may there be defective in the chip interface design of other company, in the hardware product interoperability test, how to check effectively that the correctness of interface sequence just seems very important.
At present, in the logical simulation checking, general solution has following two kinds in the prior art:
A kind of method is only checked the data that tested interface transmits, and thinks as long as the data that transmit are correct, just determines that interface sequence is correct.But this detection method is inadequate, because interface sequence not necessarily can cause transmitting error in data during not in full conformity with standard time sequence, and in case error in data occurs transmitting, orientation problem is very difficult;
Another kind method is to have script function on simulator, realizes detecting the sequential function by compile script.But the weak point of this detection method is that it depends on specific simulator, and is not general.
Summary of the invention
The present invention proposes a kind of apparatus and method that realize that the communication interface sequential automatically detects, the detection that exists in the prior art is insufficient to solve, location difficulty and uncurrent problem.
For achieving the above object, solution of the present invention is:
A kind of device of realizing that the communication interface sequential detects automatically, this device comprises:
Input module is used to receive the interface signal on the detected interface;
Signal processing module is used to handle the interface signal that is received by input module;
The input trigger module is used for triggering corresponding time sequence, and then detects by signal and related data after the processing that obtains after the signal processing module processing;
Storage and control module are used for the object information after the detection of input trigger module being stored and being reported;
The cpu i/f module is used to finish the transmission of the cpu i/f sequential and the information of detection;
After handling via input module entering signal processing module, interface signal on the tested interface obtains signal and other related datas after the required processing, triggering sequential by the input trigger module detects, store the result after detecting into storage and control module, and detection information is sent out by the cpu i/f module.
Described input trigger module can be used for also judging whether described signal and other related datas are crucial moments, if then export relevant information.
Be the moment that relatively has the sign meaning in the normal state simulation process described crucial moment, can be the beginning that transmits of cell or ethernet frame or finish constantly.
The present invention has also proposed a kind of method that realizes that the communication interface sequential detects automatically, comprises following steps:
Interface signal on a, the detected interface of reception;
The interface signal that b, processing have received, signal and related data after obtaining processing;
C, triggering corresponding time sequence, and then detect signal and related data after the described processing;
Result after d, judgement detect if meet the requirements, then continues emulation and normal testing process, as if undesirable, continues emulation and testing process after then stopping emulation and testing process or waiting for timing recovery.
Before detecting, triggering corresponding time sequence among the described step c further comprises: judge whether signal and other related datas after the described processing are crucial moments, if then export relevant information.
Adopt the checkout gear of technical solutions according to the invention manufacturing in simulating, verifying, not rely on particular simulator, have good versatility, high efficiency, portability and reusability, it can be widely used in the logic testing of any employing interface, and can not cause any interference to former emulation process.In addition, the detection of sequential is no longer needed manual intervention, realized automation fully, only need after emulation finishes, check that the detection information of output gets final product.
Description of drawings
Fig. 1 is the modular structure schematic diagram of the described device of the embodiment of the invention;
Fig. 2 is the flow chart of the described method of the embodiment of the invention;
Fig. 3 is the specific implementation flow chart of the described method of the embodiment of the invention.
Embodiment
Describe the present invention in detail below in conjunction with specific embodiment situation as shown in Figure 1, 2, 3.
Present embodiment is at comprising: one of this certain criteria Interface design of multiport Utopial2 interface (level2 Universal Test ﹠ Operations PHY Interface for ATM) checkout gear independently, its outer hanging on the interface bus is as the detection of docking port sequential.
Be illustrated in figure 1 as the apparatus module structural representation of the embodiment of the invention, its composition comprises:
Input module (2) is used to receive the interface signal on the detected interface;
Signal processing module (3) is used to handle the interface signal that is received by input module;
Input trigger module (4) is used for triggering corresponding time sequence, and then detects by signal and related data after the processing that obtains after the signal processing module processing;
Storage and control module (5) are used for the object information after the detection of input trigger module being stored and being reported;
Cpu i/f module (6) is used to finish the transmission of the cpu i/f sequential and the information of detection;
After handling via input module (2) entering signal processing module (3), interface signal on the tested interface obtains signal and other related datas after the required processing, detect by input trigger module (4) triggering corresponding time sequence, store the result after detecting into storage and control module (5), and detection information is sent out by cpu i/f module (6).
Respectively each module is specifically addressed below:
1, input module (2)
After logical simulation begins, input module (2) receiving interface signal, its interface signal is specially interface sequence, as cell data etc., is sent to signal processing module (3) then.
2, signal processing module (3)
Processing is by the interface signal that input module (2) receives, and obtains signal and other related datas after the required processing in back, specifically, the signal after the processing be corresponding with original some signals, through a simply dealt level value; And other related datas are not corresponding with original some input signals, but the data that the back process is helped out that calculate according to a plurality of signal values, for example in the monitoring of multiport Utopial2 interface, do not have the port numbers value in the input signal, after address caching one need being clapped, utilize the address value behind enable signal enb value and the buffer memory to calculate selected port numbers.
3, input trigger module (4)
Be input to input trigger module (4) by signal and related data after the processing that obtains after signal processing module (3) processing, in case certain particular case occurs, for example particular value appears in certain signal, or certain signal combination situation appears, these situations tend to cause certain sequential to occur in the normal state simulation process, for example in monitoring to the Utopial2 interface of multiport, in case effective low level appears in the enb signal, then tend to cause the beginning of cell transport process, this moment is then by judging the detection of statement triggering corresponding time sequence, compare with the corresponding interface sequential and standard interface sequential, finish detection this specific time sequence process.
4, storage and control module (5)
With the object information after input trigger module (4) detection,, realize storing and reporting by register as error message, temporal information and other relevant informations.Can adopt and report interrupt mode or CPU polling mode to realize.
5, cpu i/f module (6)
By this module detection information is sent to cpu bus (7), finishes the transmission of the cpu i/f sequential and the information of detection.
Described input trigger module (4), can be used for also judging whether described signal and other related datas are crucial moments, that is: relatively have in the normal state simulation process moment that indicates meaning, can define crucial moment voluntarily, transmit beginning, finish moment or the like as cell, ethernet frame, if then export relevant information.Relevant information reports by the way, is used for grasping the logic operation process, assists location mistake etc.
The aforesaid a kind of device of realizing the communication interface automatic detection of time sequence of the embodiment of the invention, it adopts hardware description language Verilog or VHDL to write, and is illustrated in figure 3 as the whole system operation flow chart.Above-mentioned a kind of device of communication interface automatic detection of time sequence of realizing is hung over outward on the interface bus, and interface signal is as the input of this device, and like this, in course of normal operation, this device can not introduced any interference by the docking port signal.
As shown in Figures 2 and 3, the course of work of the described device of present embodiment comprises following steps:
One, receives interface signal on the detected interface (1).
After logical simulation begins,, be sent to signal processing module (3) then by input module (2) receiving interface signal.
Two, handle the interface signal that receives, and with signal and other related datas after the required processing that obtains after its processing.
After by signal processing module (3) interface signal that receives being handled, signal after obtaining processing, promptly corresponding, the simply dealt level value of process with original some signals, not corresponding with original some input signals, but the related data that the back process is helped out that calculates according to a plurality of signal values.
Three, triggering corresponding time sequence, and then detect signal and related data after the described processing.
According to signal and related data after the processing, judge whether it is crucial moment then, promptly relatively have the moment of sign meaning in the normal state simulation process, can define crucial moment voluntarily, transmit beginning, finish moment or the like as cell, ethernet frame.If then display message and mimeograph documents.
Particular value appears when certain signal occurring, or when certain particular case of certain signal combination occurring, in the normal state simulation process, tend to cause certain sequential to occur, this moment is then by judging the detection of statement triggering corresponding time sequence, with the corresponding interface sequential and standard interface sequential relatively, and then finish detection to this specific time sequence process.
Four, the result after judgement detects if meet the requirements, then continues emulation and normal testing process, as if undesirable, continues emulation and testing process after then stopping emulation and testing process or waiting for timing recovery.
If the result meets the requirements, then continue said process, again Processing Interface signal, carry out emulation and testing process, if the result is undesirable, continue emulation and testing process after then stopping emulation and testing process or waiting for timing recovery, and the object information after by storage and control module (5) input trigger module (4) being detected is realized storage by register and is reported, simultaneously detection information is sent to cpu bus (7), thereby finishes the transmission of the cpu i/f sequential and the information of detection by cpu i/f module (6).
In sum, be the embodiment of the described method and apparatus of the embodiment of the invention.Its advantage is: present embodiment hangs over outward on the interface bus, does not rely on specific simulator, and can not cause any interference to former emulation process.In addition, the detection of the clock signal of tested interface is no longer needed manual intervention, realized automation fully, only need after emulation finishes, check that the detection information of output gets final product.Present embodiment can in real time, automatically detect the agreement accordance of tested interface sequence, has good versatility, high efficiency, portability and reusability, and it can be widely used in the logic testing of any employing interface.
Claims (5)
1, a kind of method that realizes that the communication interface sequential detects automatically is characterized in that the method includes the steps of:
Interface signal on a, the detected interface of reception;
The interface signal that b, processing have received, signal and related data after obtaining processing;
C, triggering corresponding time sequence, and then detect signal and related data after the described processing;
Result after d, judgement detect if meet the requirements, then continues emulation and normal testing process, as if undesirable, continues emulation and testing process after then stopping emulation and testing process or waiting for timing recovery.
2, a kind of method that realizes that the communication interface sequential detects automatically as claimed in claim 1, it is characterized in that, before detecting, triggering corresponding time sequence among the described step c further comprises: judge whether signal and related data after the described processing are crucial moments, if then export relevant information.
3, a kind of method that realizes that the communication interface sequential detects automatically as claimed in claim 2 is characterized in that, be the moment that relatively has the sign meaning in the normal state simulation process described crucial moment.
4, a kind of device of realizing that the communication interface sequential detects automatically is characterized in that this device comprises:
Input module is used to receive the interface signal on the detected interface;
Signal processing module is used to handle the interface signal that is received by input module;
The input trigger module is used for triggering corresponding time sequence, and then detects by signal and related data after the processing that obtains after the signal processing module processing;
Storage and control module are used for the object information after the detection of input trigger module being stored and being reported;
The cpu i/f module is used to finish the transmission of the cpu i/f sequential and the information of detection;
After handling via input module entering signal processing module, interface signal on the tested interface obtains signal and other related datas after the required processing, detect by input trigger module triggering corresponding time sequence, store the result after detecting into storage and control module, and detection information is sent out by the cpu i/f module.
5, a kind of device of realizing that the communication interface sequential detects automatically as claimed in claim 4, it is characterized in that, described input trigger module can be used for also judging whether described signal and other related datas are crucial moments, if then export relevant information.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101498742B (en) * | 2008-01-30 | 2012-09-26 | 华硕电脑股份有限公司 | Automatic signal judgment method and time sequence difference automatic measuring method |
| US8306391B2 (en) | 2006-05-08 | 2012-11-06 | Thomson Licensing | Method for resuming content reproduction across devices |
| CN104022919A (en) * | 2014-06-25 | 2014-09-03 | 北京经纬恒润科技有限公司 | Method, device and system for controlling data excitation of plurality of bus interfaces |
| CN105844190A (en) * | 2016-03-18 | 2016-08-10 | 东南大学 | RFID label air interface protocol accordance automation test method based on virtual instrument |
| WO2018076682A1 (en) * | 2016-10-28 | 2018-05-03 | 深圳市中兴微电子技术有限公司 | Parallel interface time sequence control method and apparatus |
| CN117149548A (en) * | 2023-09-07 | 2023-12-01 | 上海合芯数字科技有限公司 | Method and device for measuring time sequence of server system, electronic equipment and storage medium |
-
2003
- 2003-06-24 CN CNB031456014A patent/CN100499410C/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8306391B2 (en) | 2006-05-08 | 2012-11-06 | Thomson Licensing | Method for resuming content reproduction across devices |
| CN101498742B (en) * | 2008-01-30 | 2012-09-26 | 华硕电脑股份有限公司 | Automatic signal judgment method and time sequence difference automatic measuring method |
| CN104022919A (en) * | 2014-06-25 | 2014-09-03 | 北京经纬恒润科技有限公司 | Method, device and system for controlling data excitation of plurality of bus interfaces |
| CN105844190A (en) * | 2016-03-18 | 2016-08-10 | 东南大学 | RFID label air interface protocol accordance automation test method based on virtual instrument |
| CN105844190B (en) * | 2016-03-18 | 2017-12-29 | 东南大学 | RFID label tag air interface protocol accordance automated testing method based on virtual instrument |
| WO2018076682A1 (en) * | 2016-10-28 | 2018-05-03 | 深圳市中兴微电子技术有限公司 | Parallel interface time sequence control method and apparatus |
| CN108011703A (en) * | 2016-10-28 | 2018-05-08 | 深圳市中兴微电子技术有限公司 | A kind of parallel interface sequential control method and device |
| CN108011703B (en) * | 2016-10-28 | 2020-05-26 | 深圳市中兴微电子技术有限公司 | Parallel interface time sequence control method and device |
| CN117149548A (en) * | 2023-09-07 | 2023-12-01 | 上海合芯数字科技有限公司 | Method and device for measuring time sequence of server system, electronic equipment and storage medium |
| CN117149548B (en) * | 2023-09-07 | 2024-04-26 | 上海合芯数字科技有限公司 | Method and device for measuring time sequence of server system, electronic equipment and storage medium |
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| CN100499410C (en) | 2009-06-10 |
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