CN1567529B - Multi-layer type anti-reflection layer and semiconductor process adopting the same - Google Patents
Multi-layer type anti-reflection layer and semiconductor process adopting the same Download PDFInfo
- Publication number
- CN1567529B CN1567529B CN 03141061 CN03141061A CN1567529B CN 1567529 B CN1567529 B CN 1567529B CN 03141061 CN03141061 CN 03141061 CN 03141061 A CN03141061 A CN 03141061A CN 1567529 B CN1567529 B CN 1567529B
- Authority
- CN
- China
- Prior art keywords
- reflecting layer
- layer
- multiple field
- field anti
- making method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The invention reveals a multilayer antireflection layer and the manufacturing method of semiconductor by adopting it. The multilayer antireflection layer is applied to a substrate, including a dielectric antireflection layer formed on the substrate and an organic antireflection layer formed on the dielectric antireflection layer.
Description
Technical field
The invention relates to the semiconductor lithography manufacture method, particularly relevant for the anti-reflecting layer in the photoetching manufacturing method, more particularly, the semiconductor making method that relates to a kind of multiple field anti-reflecting layer and adopt this multiple field anti-reflecting layer.
Background technology
Along with the integrated degree raising of semiconductor subassembly, the linewidth requirements of semiconductor subassembly is more and more less, and the control of critical size (critical dimension, CD) is also more and more important.In photoetching manufacturing method, because there has been the high low head of figure in wafer surface, therefore when photoresist is covered in wafer surface, can along with the planarization characteristics (planarization) of photoresist, cause the photoresist layer variable thickness.And when photoetching light is advanced in photoresist, then can form constructive/destruction interference phenomenon at reverberation and the incident light of wafer surface, thereby produce so-called hunt effect (swing effect).Above-mentioned photoresist uneven thickness and hunt effect, the ill effect that all can cause critical size to change.
Has highly reflective owing to polysilicon, metal and polysilicon/metal are laminated, reflection problems at the deep UV (ultraviolet light) wave band all is bigger than visible light wave range, therefore cause photoresist layer generation standing wave effect and notch (notching) effect will be more serious, so that the design transfer confidence level of lithographic procedures significantly reduces.
For fear of hunt effect, generally adopt the method for bottom layer anti-reflection layer (Bottom Anti-Reflective Coating, BARC), namely the film of first last layer thin thickness before the coating photoresist.On practice, BARC can divide into two large types: the first is to utilize refractive index close to the material of photoresist, and its absorptivity and thickness are usually comparatively large, and the second then can design the impact of specific light absorptivity and interference, normally puts on substrate with depositional mode.Below distinguish this BARC of two types of simple declaration.
The first type is the mode by rotary coating, and the organic polymer that will contain high absorptivity is coated substrate surface.See also Figure 1A, show the bottom layer anti-reflection layer of existing the first type.Before coating photoresist layer 16, prior to being coated with one deck organic film as BARC 14 in spin coating (spin-on) mode in the substrate 10, thickness is about 1000～
Then be coated with thereon photoresist layer 16.When projection one photoetching irradiation light 11 was in substrate 10, the light that the organic principle in the organic film (Organic Dye) can absorption base reflects was to reduce the variation of live width.Yet this kind coating still can such as assembly 12, rise and fall and produce along with the flatness of wafer surface, can't reach the phase deviation (phase shift) of stability.
The second type then is to utilize the mode of chemical vapour deposition (CVD) (CVD) to carry out film growth, and obtains dielectric medium anti-reflecting layer (Dielectric Anti-Reflection Coating, DARC).See also Figure 1B, the existing design that improves hunt effect with darc layer is described.Mainly be on matrix 20, to form a thickness about 300 in chemical vapour deposition (CVD) mode (CVD) first
About the dielectric medium anti-reflecting layer, then form thereon photoresist layer 26.This mode is specially adapted in the deep UV (ultraviolet light) photoetching technique.The layout that darc layer is subject to wafer surface rises and falls, such as assembly 22, impact less, and the main feature of this method is can be by manufacture method parameter such as gas flow, the pressure etc. of material (Si, O, N or the C) ratio of adjusting darc layer or change CVD, and reflection coefficient (the refractive index of adjustment darc layer, n) with absorption coefficient (extinction coefficient, k) value, to reach good phase deviation, form destruction interference, eliminate the reverberation of matrix 20.Yet the n that adjusts above-mentioned darc layer thickness and k value be often along with different manufacture method requirements, and different technical difficulty is arranged, and this kind anti-reflecting layer often can cause the generation undercutting of photoresist side wall profile or footing.
Above-mentioned traditional anti-reflecting layer only comprises simple layer usually, and its defective is respectively arranged, and therefore still having needs the improvement part.
Summary of the invention
In view of this, the object of the present invention is to provide anti-reflecting layer, its formation method of a kind of multiple field and the semiconductor making method that adopts this multiple field anti-reflecting layer, the advantage of the bottom layer anti-reflection layer that combination is existing two types, with control critical size (CD), improve the allowance of photoetching manufacturing method.
According to above-mentioned purpose, a kenel of the present invention provides a kind of multiple field anti-reflecting layer, be to be applicable to a substrate, it comprises that a dielectric medium anti-reflecting layer is formed in this substrate, and one organic antireflection layer be formed on this dielectric medium anti-reflecting layer, above-mentioned dielectric medium anti-reflecting layer and organic antireflection layer be common to form above-mentioned multiple field anti-reflecting layer.
Another kenel of the present invention provides a kind of formation method of multiple field anti-reflecting layer, be applicable to a substrate, it may further comprise the steps: form a dielectric medium anti-reflecting layer in this substrate, and on this dielectric medium anti-reflecting layer, form an organic antireflection layer, make this dielectric medium anti-reflecting layer and this organic antireflection layer form a multiple field anti-reflecting layer.
In one embodiment of the invention, the dielectric medium anti-reflecting layer in the above-mentioned multiple field anti-reflecting layer is silicon oxynitride (SiON) layer, and the thickness of dielectric medium anti-reflecting layer is between 20nm～60nm, take 40nm as good; Above-mentioned organic antireflection layer is Polyimide (polyimide) or polysulfones (polysulfone), and the thickness of this organic antireflection layer is between 40nm～135nm, take 60nm or 95nm as good.The Thickness Ratio of above-mentioned dielectric medium anti-reflecting layer and organic antireflection layer is 1: 1～1: 5, take 1: 2.375 as good.
Another kenel of the present invention provides a kind of semiconductor making method that adopts above-mentioned multiple field anti-reflecting layer, is to comprise: a substrate is provided, a reflector is arranged on it; Form this multiple field anti-reflecting layer on this reflector, it comprises that a dielectric medium anti-reflecting layer is formed on this reflector, and an organic antireflection layer is formed on this dielectric medium anti-reflecting layer; On this multiple field anti-reflecting layer, form a patterning photoresist layer.Above-mentioned reflector can be oxide layer or conductive layer.
In one embodiment of the invention, the semiconductor making method of above-mentioned employing multiple field anti-reflecting layer more comprises a step: with this patterning photoresist this multiple field anti-reflecting layer and this reflector are carried out etching.When above-mentioned reflector was oxide layer, etching was to adopt the gas selected out among C5F8, C4F8 or the C4F6 and oxygen, carbon monoxide and argon as reacting gas; When above-mentioned reflector was conductive layer, etching was to adopt BC13, C12, HBr, oxygen, helium as reacting gas.
Description of drawings
Figure 1A～1B shows the photoresist structure profile of existing bottom layer anti-reflection layer (BARC); Wherein Figure 1A adopts organic film as bottom layer anti-reflection layer, and Figure 1B adopts dielectric material as anti-reflecting layer (DARC)
Fig. 2 A～2F is a series of profiles, shows in the preferred embodiment of the present invention, adopts the semiconductor making method of multiple field anti-reflecting layer
Fig. 3 shows the concrete outcome of comparative example of the present invention and embodiment
Description of reference numerals
10～substrate, 11～photoetching light
12～assembly, 14～bottom layer anti-reflection layer
The 20th～substrate of 16～photoresist layer
21～photoetching light, 22～assembly
24～bottom layer anti-reflection layer, 26～photoresist layer.
100～substrate, 102～the first dielectric layers
104～the second dielectric layers, 106～the first anti-reflecting layers
108～the second anti-reflecting layers, 110～photoresist layer
Photoresist layer 112～the etching program of 110a～patterning.
Embodiment
Below utilize a series of profiles of Fig. 2 A to Fig. 2 F, take suprabasil reflector as double-deck dielectric layer as example, describe in detail to adopt the embodiment of the semiconductor making method of multiple field anti-reflecting layer of the present invention.
Shown in Fig. 2 A, semiconductor substrate 100 is provided, be the semiconductor silicon substrate for example, comprise plural semiconductor subassembly on it, for simplicity, its assembly that comprises of icon not.Deposition the first dielectric layer 102 in substrate 100, for example with trimethyl borine acid esters (trimethylborate, TMB) and trimethyl phosphite (trimehtylphosphite, TMPI) as raw material, carry out chemical vapour deposition (CVD) (chemical vaporseposition, CVD) reaction, and the dielectric deposition of the boron-phosphorosilicate glass (Boron PhosphateSilciate Glass, BPSG) of formation doped with boron and phosphorus composition.Then, process the first dielectric layer 102 surfaces with hot reflux or cmp (chemicalmechanical polishing, CMP), make its planarization.
Next, shown in Fig. 2 B, forming the second dielectric layer 104 on the first dielectric layer 102, for example is the dielectric layer of tetraethyl orthosilicate ester (tetraethylorthosilicate, TEOS).Above-mentioned first and second dielectric layer can be used as interlayer dielectric layer (interlayer dielectric, ILD).
Then, shown in Fig. 2 C, form the first anti-reflecting layer 106 on the 2nd dielectric layer 104, for example the mode with chemical vapour deposition (CVD) deposits a silicon oxynitride (SiON) film, and thickness is between 20nm～60nm, take 40nm as good.
Then, shown in Fig. 2 D, on the first anti-reflecting layer 106, form the second anti-reflecting layer 108, for example form the film of polyimides (polyimide) or polysulfones (polysulfone) in the rotary coating mode, thickness is usually between 40nm～135nm, take 60nm or 95nm as good.The common formation of above-mentioned the 1st anti-reflecting layer and the 2nd anti-reflecting layer multiple field anti-reflecting layer of the present invention.
Secondly, shown in Fig. 2 E, on the 2nd anti-reflecting layer 108, form a photoresist layer 110.
At last, shown in Fig. 2 F, above-mentioned photoresist layer 110 is carried out exposure program, carry out developing programs with suitable solution again, to form required patterning photoresist 110a.In said procedure, because anti-reflecting layer of the present invention has the first anti-reflecting layer 106 of dielectric layer formation and the second anti-reflecting layer 108 of organic layer formation, the shortcomings such as the fences that can produce in the time of can preventing from only organic antireflection layer being arranged or streak, and can be in follow-up program as hard mask.Afterwards, can above-mentioned patterning photoresist layer 110a be mask, elder generation's etching anti-reflecting layer (106 and 108), again with patterning photoresist layer and anti-reflecting layer of the present invention jointly as mask, and a gas of selecting out in C5F8, C4F8 or the C4F6 and oxygen, carbon monoxide and argon are as reacting gas, etching (112) the above-mentioned the 1st and the 2nd dielectric layer, above-mentioned reacting gas has high selectivity for SiON.In addition, when the reflector was conductive layer, etching program also can adopt had BC13, C12, HBr, oxygen and the helium of high selectivity as reacting gas to SiON.Present embodiment only illustrates when the reflector is dielectric layer or conductive layer, further etching, yet, according to actual needs, except etching program, also may be to carry out Implantation, plasma treatment or other program, be not limited to etching program.
The effect of anti-reflecting layer of the present invention as shown in Figure 3, it is to be presented at as the TEOS thickness of dielectric layer not simultaneously, adopt multiple field anti-reflecting layer of the present invention, and change under the situation of thickness of the 1st layer of anti-reflecting layer (SiON) variation of critical size (namely photoresist characteristic width).Among the figure, the longitudinal axis is actual critical size (CD, or photoresist is levied width (Resist feature width)), and transverse axis is dielectric layer TEOS thickness, and the SiON thickness condition is as scheming shown in the right side, and the critical size shown in this figure is the width that adopts 165nm.The result shows, when SiON thickness is 0 (comparative example), photoresist characteristic width gap is very big, and when adopting the present invention to contain the multiple field anti-reflecting layer of SiON, photoresist characteristic width gap furthers, and namely more is not vulnerable to the impact that medium thickness changes.
The above results is added up as shown in table 1, table 1 is the critical size that shows comparative example (when SiON thickness is 0) and embodiment (when the thickness of SiON is 40nm), the mean value of comparative example is 167.33nm, the gap of maximum and minimum value is 24nm, overall uncertainty (3 σ) is 11.502, and the mean value of embodiment is 166.78nm, and the gap of maximum and minimum value reduces to 12 significantly, and overall uncertainty (3 σ) also reduces to 7.6806 significantly.Therefore, multiple field anti-reflecting layer of the present invention has splendid improvement to the homogeneity (uniformity) of critical size really.
Table 1
| Comparative example | Embodiment | |
| Maximum | 174 | 172 |
| Minimum value | 150 | 160 |
| Mean value | 167.33 | 166.78 |
| Maximum and |
24 | 12 |
| 3σ | 11.502 | 7.6806 |
Shown by above explanation and experimental result, when multiple field anti-reflecting layer of the present invention is applied to semiconductor making method, because the advantage of combination organic antireflection layer and dielectric medium anti-reflecting layer, the dielectric medium anti-reflecting layer is in substrate, can prevent from producing fences or streak in substrate, improve the homogeneity of critical size, not only can promote the allowance of photoetching manufacturing method, when the etching reflector, multiple field anti-reflecting layer of the present invention and photoresist layer are jointly as mask, also can improve etching mask thickness, above-mentioned various advantages also pulls together to promote the allowance of whole manufacture method.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention, any those who are familiar with this art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, thus the present invention protection range claims after looking attached be as the criterion.
Claims (27)
1. a multiple field anti-reflecting layer is applicable to a substrate, is to comprise:
One dielectric medium anti-reflecting layer is formed in this substrate; And
One organic antireflection layer is formed on this dielectric medium anti-reflecting layer, and wherein the Thickness Ratio of this dielectric medium anti-reflecting layer and organic antireflection layer was between 1: 1 to 1: 5.
2. multiple field anti-reflecting layer as claimed in claim 1, wherein this dielectric medium anti-reflecting layer is silicon oxynitride layer.
3. multiple field anti-reflecting layer as claimed in claim 1, wherein the thickness of this dielectric medium anti-reflecting layer is between 20nm～60nm.
4. multiple field anti-reflecting layer as claimed in claim 2, wherein this dielectric medium anti-reflecting layer is to form in the chemical vapour deposition (CVD) mode.
5. multiple field anti-reflecting layer as claimed in claim 3, wherein the thickness of this dielectric medium anti-reflecting layer is 40nm.
6. multiple field anti-reflecting layer as claimed in claim 1, wherein this organic antireflection layer is polyimides or polysulfones.
7. multiple field anti-reflecting layer as claimed in claim 1, wherein the thickness of this organic antireflection layer is between 40nm～135nm.
8. multiple field anti-reflecting layer as claimed in claim 6, wherein the thickness of this organic antireflection layer is 60nm.
9. multiple field anti-reflecting layer as claimed in claim 6, wherein the thickness of this organic antireflection layer is 95nm.
10. multiple field anti-reflecting layer as claimed in claim 6, wherein this organic antireflection layer is to form in the rotary coating mode.
11. multiple field anti-reflecting layer as claimed in claim 1, wherein the Thickness Ratio of this dielectric medium anti-reflecting layer and organic antireflection layer is 1: 2.375.
12. a semiconductor making method that adopts a multiple field anti-reflecting layer is to comprise the following step:
One substrate is provided, a reflector is arranged on it;
On this reflector, form this multiple field anti-reflecting layer, it comprises that a dielectric medium anti-reflecting layer is formed on this reflector, and one organic antireflection layer be formed on this dielectric medium anti-reflecting layer, wherein the Thickness Ratio of this dielectric medium anti-reflecting layer and organic antireflection layer was between 1: 1 to 1: 5;
On this multiple field anti-reflecting layer, form a patterning photoresist layer.
13. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 12, wherein this reflector is an oxide layer.
14. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 12, wherein this reflector is a conductive layer.
15. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 12, wherein this dielectric medium anti-reflecting layer is silicon oxynitride layer.
16. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 12, wherein the thickness of this dielectric medium anti-reflecting layer is between 20nm～60nm.
17. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 16, wherein the thickness of this dielectric medium anti-reflecting layer is 40nm.
18. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 12, wherein this dielectric medium anti-reflecting layer is to form in the chemical vapour deposition (CVD) mode.
19. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 12, wherein this organic antireflection layer is polyimides or polysulfones.
20. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 12, wherein the thickness of this organic antireflection layer is between 40nm～135nm.
21. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 20, wherein the thickness of this organic antireflection layer is 60nm.
22. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 20, wherein the thickness of this organic antireflection layer is 95nm.
23. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 12, wherein this organic antireflection layer is to form in the rotary coating mode.
24. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 13 more comprises a step: with this patterning photoresist this multiple field anti-reflecting layer and this reflector are carried out etching.
25. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 24, wherein this etching is to adopt the gas selected out among C5F8, C4F8 or the C4F6 and oxygen, carbon monoxide and argon as reacting gas.
26. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 14 more comprises a step: with this patterning photoresist this multiple field anti-reflecting layer and this reflector are carried out etching.
27. the semiconductor making method of employing one multiple field anti-reflecting layer as claimed in claim 26, wherein this etching is to adopt BC13, C12, HBr, oxygen and helium as reacting gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03141061 CN1567529B (en) | 2003-06-13 | 2003-06-13 | Multi-layer type anti-reflection layer and semiconductor process adopting the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03141061 CN1567529B (en) | 2003-06-13 | 2003-06-13 | Multi-layer type anti-reflection layer and semiconductor process adopting the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1567529A CN1567529A (en) | 2005-01-19 |
| CN1567529B true CN1567529B (en) | 2013-04-03 |
Family
ID=34470832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03141061 Expired - Lifetime CN1567529B (en) | 2003-06-13 | 2003-06-13 | Multi-layer type anti-reflection layer and semiconductor process adopting the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1567529B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094072B (en) * | 2011-11-01 | 2016-03-30 | 无锡华润上华科技有限公司 | Improve the method for gate lithography critical dimension uniformity on wafer |
| US9766652B2 (en) * | 2012-08-31 | 2017-09-19 | Lg Chem, Ltd. | Conductive structure and method for manufacturing same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6190955B1 (en) * | 1998-01-27 | 2001-02-20 | International Business Machines Corporation | Fabrication of trench capacitors using disposable hard mask |
-
2003
- 2003-06-13 CN CN 03141061 patent/CN1567529B/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6190955B1 (en) * | 1998-01-27 | 2001-02-20 | International Business Machines Corporation | Fabrication of trench capacitors using disposable hard mask |
Non-Patent Citations (1)
| Title |
|---|
| JP平2-244742A 1990.09.28 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1567529A (en) | 2005-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6316348B1 (en) | High selectivity Si-rich SiON etch-stop layer | |
| US6720256B1 (en) | Method of dual damascene patterning | |
| US6127262A (en) | Method and apparatus for depositing an etch stop layer | |
| US6342452B1 (en) | Method of fabricating a Si3N4/polycide structure using a dielectric sacrificial layer as a mask | |
| JPH07181688A (en) | Forming method of multilayer resist pattern | |
| US20010016414A1 (en) | Use of PE-SiON or PE-Oxide for contact or via photo and for defect reduction with oxide and w chemical-mechanical polish | |
| JP4776747B2 (en) | Contact formation method of semiconductor element | |
| KR20010032913A (en) | System and method for etching organic anti-reflective coating from a substrate | |
| US6103632A (en) | In situ Etching of inorganic dielectric anti-reflective coating from a substrate | |
| US20080132085A1 (en) | Silicon Rich Dielectric Antireflective Coating | |
| US6051369A (en) | Lithography process using one or more anti-reflective coating films and fabrication process using the lithography process | |
| US6867145B2 (en) | Method for fabricating semiconductor device using photoresist pattern formed with argon fluoride laser | |
| US6255717B1 (en) | Shallow trench isolation using antireflection layer | |
| US8101452B2 (en) | Image sensor and method for manufacturing the same | |
| US20100018944A1 (en) | Patterning method | |
| US7700493B2 (en) | Method for fabricating semiconductor device | |
| US6368906B1 (en) | Method of planarization using selecting curing of SOG layer | |
| US6930028B1 (en) | Antireflective structure and method | |
| CN1567529B (en) | Multi-layer type anti-reflection layer and semiconductor process adopting the same | |
| CN101937865B (en) | Method for forming groove | |
| CN101471284A (en) | Metal line in a semiconductor device and its manufacturing method | |
| KR20090067607A (en) | Method for forming micropattern in semiconductor device | |
| TWI223854B (en) | Multi-layer type anti-reflection layer and semiconductor process using this layer | |
| KR100283481B1 (en) | Dielectric mask for trench formation and manufacturing method thereof | |
| KR100454821B1 (en) | Method For Forming Metal Lines Of Semiconductor Devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130403 |