CN1567475A - Memory element with built-in error connecting function - Google Patents
Memory element with built-in error connecting function Download PDFInfo
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- CN1567475A CN1567475A CN 03146539 CN03146539A CN1567475A CN 1567475 A CN1567475 A CN 1567475A CN 03146539 CN03146539 CN 03146539 CN 03146539 A CN03146539 A CN 03146539A CN 1567475 A CN1567475 A CN 1567475A
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Abstract
It is a kind of semiconductor memory elements that with the built-in error-correction function. It consists of a primary array that with plural memory cells, a redundancy array that with at least one replacement cell, which is used for replacing at least one defective cell of the primary array. The defective cell can be identified by a control signal, which changed according to the different defective states of defective cell at different time. It also consists of a switching circuit that includes a reprogrammable logic array, which can be coupled with the primary array and redundancy array to receive the above mentioned control signal and switch the cell signal of defective cell to that of replacement cell.
Description
Technical field
The invention relates to a kind of semiconductor memery device, and particularly relevant for a kind of memory component with built-in error correcting ability and a kind of operational store element so that the method for built-in error correcting ability to be provided.
Background technology
For the design of semiconductor memery device, the redundant memory unit is made with memory array along the row (columns) of memory array or row (rows) usually.Redundant circuit utilizes one or more redundant memories unit to replace one or more fault memorizers unit of memory array in order to control.Even above-mentioned redundant memory unit is by memory component still normal operation when memory array is shown the fault memorizer unit.
Generally speaking, redundant circuit is connected to the redundant memory unit, and a corresponding row or column of selecting a row or column of redundant memory unit to replace the memory cell with one or more trouble units.Especially, redundant circuit replaces trouble unit to respond an address signal corresponding to the trouble unit of memory array (address signal) by access redundant memory unit.
Permanent fusible binding (fusible link) of replacing trouble unit is used in known redundant circuit design.Especially, above-mentioned redundant circuit dependency logic circuit produces and reaches the signal of replacing trouble unit.Above-mentioned logical circuit may be made up of a logic gate array that has fusible binding between its logic lock.Above-mentioned fusible binding design allows the electric connection between the logic lock become program design by big electric current to above-mentioned one or more bindings are provided to cut off fusible binding.Utilize the specific residue between the logic lock to connect to come the above-mentioned logical circuit of program design to operate above-mentioned redundant circuit so that utilize redundancy unit forever to replace trouble unit.
Yet if the redundant memory unit of being replaced becomes fault after a while, the permanent redundancy unit of being replaced that will hinder of above-mentioned redundant circuit is replaced again, so the reliability of limits storage element and elasticity.As a result, can only use known redundant circuit to be alternatively to the fault memorizer unit that manufacture process produces, and can't replace the memory cell that after memory component begins to operate, becomes fault after a while.
Summary of the invention
According to the present invention, provide a kind of memory component that comprises a main array, a redundant array and an on-off circuit at this.Above-mentioned main array comprises plurality of memory units, comprising one first trouble unit and one second trouble unit.Above-mentioned redundant array comprises at least one and replaces memory cell, in order to replace at least one trouble unit of above-mentioned main array.Receive one first control signal with the said switching circuit of above-mentioned main array and above-mentioned redundant array coupling and the cell signal of above-mentioned first trouble unit is switched to above-mentioned replacement unit, and receive one second control signal and the cell signal of above-mentioned second trouble unit is switched to above-mentioned replacement unit.In an embodiment, above-mentioned first and second control signal is discerned above-mentioned first and second trouble unit respectively, and wherein above-mentioned first and second control signal changes in the malfunction of different time according to above-mentioned first and second trouble unit.
Also, provide a kind of memory component with built-in error correcting ability at this according to the present invention.Above-mentioned memory component comprises a main array, a redundant array and an on-off circuit.Above-mentioned main array comprises plurality of memory units.Above-mentioned redundant array comprises at least one and replaces the unit, in order to replace at least one trouble unit of above-mentioned main array.One control signal is discerned above-mentioned trouble unit, and above-mentioned control signal changes according to the malfunction of above-mentioned trouble unit at different time.Said switching circuit comprises a program logic array again that is coupled with above-mentioned main array and above-mentioned redundant array, and the cell signal in order to receive above-mentioned control signal with above-mentioned trouble unit switches to above-mentioned replacement unit.
According to the present invention, provide a kind of operation one memory component so that the method for built-in error correcting ability to be provided in addition at this.The main array that provides one to comprise plurality of memory units is provided said method; Provide a redundant array that comprises a plurality of redundancy units, in order to replace at least one trouble unit of above-mentioned main array; Provide a control signal to discern above-mentioned trouble unit; Change above-mentioned control signal according to above-mentioned trouble unit in the malfunction of different time; And an on-off circuit is provided, the cell signal in order to receive above-mentioned control signal with above-mentioned trouble unit switches to above-mentioned replacement unit.
Above-mentioned general remark and following detailed description be all only in order to illustrate exemplary embodiments of the present invention, but not in order to limiting the present invention, so the scope of the present invention should be as the criterion with claims.
For above and other objects of the present invention, feature and advantage can be become apparent, its preferred embodiment cited below particularly, and conjunction with figs. elaborate.
Description of drawings
Fig. 1 is the calcspar as the described memory component of one embodiment of the invention.
Fig. 2 A is the calcspar as the replacement of the described memory cell of one embodiment of the invention.
Fig. 2 B is the replacement figure as the replacement of the described memory cell of one embodiment of the invention.
Fig. 3 illustrates the example of arranging as the described semi-conductor chip of one embodiment of the invention.
Fig. 4 is the calcspar as the described on-off circuit of one embodiment of the invention.
Fig. 5 illustrates as described sampling of one embodiment of the invention and holding circuit.
Fig. 6 illustrates as the described signal generator in order to the control store access of one embodiment of the invention.
Description of symbols
10 memory component 10B memory buss
The lock level end of 10C capacitor 10G transistor 10T
10T transistor 12 main arrays
14 redundant arrays, 16 on-off circuits
18 error detection elements, 20 central processing units (CPU)
30 system-on-a-chips (SOC) chip, 32 circuit system districts
34 memory module 34A master arrays
34B redundant array 34C control circuit
40 program logic arrays (RPLA) again
42 central processing units (CPU) 42B central processing units (CPU) bus
The lock level end of 42C capacitor 42G transistor 42T
44B central processing unit (CPU) bus 44C capacitor
The lock level end 44T transistor of 44G transistor 44T
46 central processing units (CPU) 46B central processing units (CPU) bus
The lock level end of 46C capacitor 46G transistor 46T
46T transistor 50 sampling and holding circuits
52G lock level is held 60 signal generators
A1～A5 memory cell C1～C6 memory cell
R1～R3 redundancy unit (replacement unit) R11～R16 redundancy unit (replacement unit)
T1～T4 cycle
Embodiment
The present invention will lift its preferred embodiment now, and with reference to appended graphic, more completely illustrate.Same reference numbers during difference is graphic is represented similar elements.
The invention provides the method for a kind of memory component and a kind of operational store element.And specifically the invention provides a kind of memory component and memory component method of operating that allows to replace one or more fault memorizers unit.Following joint at first will illustrate as the element of the described memory component of one embodiment of the invention and use the example of this memory component as the in-line memory element.Following joint will illustrate that then described use has the central memory component and the method thereof of system of multi-processor as one embodiment of the invention.
Fig. 1 is the calcspar as the described memory component of one embodiment of the invention.With reference to Fig. 1, memory component 10 comprises main array (or memory array) 12, redundant array 14 and on-off circuit 16.In an embodiment, memory component 10 may more comprise error detection element 18 and central processing unit (CPU) 20.Main array 12 comprises the plurality of memory units (not shown), the memory cell in order to store data as quickflashing (flash) memory cell or any other type.Above-mentioned memory cell is from one or more elements (as signal processor, computing machine, special applications treatment element) reception data and store the above-mentioned data that may be read after a while, override or erase.Redundant array 14 also comprises plurality of memory units.The above-mentioned memory cell of main array 12 and redundant array 14 is identical usually.For the present invention is described, so the memory cell of the main array 12 of supposition part is because the fault of manufacture view and/or other can temporarily or for good and all influence the factor of one or more operation of memory unit of main array 12 and fault.When picking out one or more trouble unit, may use the redundancy unit of redundant array 14 to replace above-mentioned trouble unit.The redundancy unit number that redundant array 14 is had is usually less than the number of unit of main array 12.The size of redundant array 14 may depend on various factors, as the size of main array 12, trouble unit possible number and cost consideration.
In order to replace trouble unit with redundancy unit, so receive the data of wanting to be stored in above-mentioned trouble unit, and the above-mentioned data of wanting to store be sent to above-mentioned redundancy unit and handle other signal or data with the on-off circuit 16 of main array 12 and redundant array 14 couplings simultaneously.Especially, on-off circuit 16 receives a control signal with the cell signal of the trouble unit that the switches main array 12 replacement unit to redundant array 14.The said units signal may comprise the information required as the access memory unit of address signal, and as the input and output data out of Memory.In an embodiment, the above-mentioned control signal that on-off circuit 16 received may be according to the malfunction of above-mentioned trouble unit and along with the time changes.In other words, but when available cell becomes fault or when trouble unit, become above-mentioned control signal of time spent and may change.The control signal of above-mentioned variation allows switch circuit 16 be selected to end original storer and replaces or set up new storer replacement.In an embodiment, on-off circuit 16 may be a logic array, as one again program logic array (reprogrammable logic array, RPLA).Especially, above-mentioned program logic array again (RPLA) may be coupled with multi-processor, allows above-mentioned multi-processor be able to access memory element 10, as by from these processor receiving element signals and delivery unit signal to these processors.
And except replacing the single failure memory cell, on-off circuit 16 may rely on the memory cell of replacing the affiliated particular block of a trouble unit, group or group to replace this trouble unit.Therefore, may use the replacement unit of a square, group or the group of redundant array to replace the memory cell of a particular block, group or the group of main array with one or more trouble units.Selecting to replace individually trouble unit or cluster ground, to replace trouble unit be according to many factors, as the type of the system of the application of the design of memory component and type, memory component, access memory element and even the fault of the memory component replaced or the type of mistake.
Generally speaking, memory component has two kinds of mistakes: permanent and temporary.It is irreversible that permanent error (being also referred to as rigid mistake (hard error)) means mistake.General permanent error occurs in during the manufacture process of memory component.It is temporary fault and this fault may change along with the time that temporary mistake (being also referred to as soft errors (soft error)) means memory cell.In other words, having the memory cell of temporary mistake may a fault length thereby only need be replaced during this specific fault.
In order to replace the temporary fault unit, so may be according to the malfunction of above-mentioned temporary fault unit and along with the time changes in order to the control signal of gauge tap circuit 16.The control signal of above-mentioned variation allows memory component more effectively be used redundant array, and the result makes that more redundancy units can be used for replacing extra trouble unit.
Fig. 2 A and Fig. 2 B provide a calcspar and a replacement figure to illustrate as the two kinds of mistakes of the described memory cell of one embodiment of the invention and the replacement of memory cell respectively.With reference to the replacement that has the memory cell of rigid mistake among Fig. 2 A, memory cell C1 to C6 is the memory cell of a memory array and redundancy unit R11 to R16 is the replacement unit of a redundant array.The function of memory cell C2, C4 and C5 is in specification limit, and memory cell C1, C3 and C6 then are permanent faults.Control signal indicator cock circuit is replaced trouble unit C1, C3 and C6 to replace unit R 11, R12 and R13 respectively, for example by respectively the cell signal of unit C1, C3 and C6 being switched to the cell signal of unit R 11, R12 and R13.
With reference to the replacement figure that has soft errors among Fig. 2 B, memory cell A1 to A5 is the memory cell of a main array and replace the memory cell that memory cell R1 to R3 is a redundant array.During the period T 4, the function of memory cell A1 is normal and memory cell A5 is a fault in period T 1.Memory cell A2 is a fault during period T 1, and is fault at period T 1 memory cell A3 during the period T 3.Memory cell A4 during the period T 4 is a fault in period T 2.Therefore, above-mentioned control signal is according to the malfunction of these temporary fault unit and change during these.
When operation, during period T 1, above-mentioned control signal indication said switching circuit is replaced unit A2 with redundancy unit R1, and replaces unit A3 with redundancy unit R2, and replaces unit A5 with redundancy unit R3.During period T 2 and period T 3, because unit A2 fault no longer, so change above-mentioned control signal to reverse a little earlier replacement instruction for unit A2.And,,, and replace unit A5 with redundancy unit R3 so the indication of above-mentioned control signal is replaced unit A3 with redundancy unit R1, and replaces unit A4 with redundancy unit R2 because redundancy unit R1 is available now.During period T 4, because unit A3 fault no longer, so change above-mentioned control signal to reverse a little earlier replacement instruction for unit A3.And, because redundancy unit R1 is available now, so the indication of above-mentioned control signal is replaced unit A4 and replaced unit A5 with redundancy unit R2 with redundancy unit R1.As a result, become now can be in order to replace other unit for redundancy unit R3.Therefore, in an embodiment, an on-off circuit may use one of a redundant array to replace a main array is replaced in the unit in different time different trouble unit in the malfunction of different time according to trouble unit.
As mentioned above, above-mentioned control signal may change according to the malfunction of one or more trouble units in different time.In order to detect the malfunction of memory cell, so the memory component 10 of Fig. 1 comprises the error detection element 18 with 14 couplings of main array 12 and redundant array, in order to periodically and/or detect the function of main array 12, redundant array 14 or both memory cells according to particular command.In an embodiment, error detection element 18 is unit testing devices, as an external test or a built-in self-test device (built-in self-tester, BIST).When using a built-in self-test device (BIST), it may become a part or a part that comprises the System on Chip/SoC of memory component 10 of memory component 10.
In addition, the memory component 10 as the described system of one embodiment of the invention may comprise in order to the central processing unit of a control signal to on-off circuit 16 (CPU) 20 to be provided.With reference to Fig. 1, central processing unit (CPU) 20 may be coupled with on-off circuit 16.In order to obtain the malfunction of memory cell, so central processing unit (CPU) 20 also may be coupled to receive the data of identification trouble unit, as the data by its Address Recognition trouble unit with error detection element 18.When change from the data of error detection element 18 with as the malfunction change of the memory component of main array 12 as a result the time, central processing unit (CPU) 20 will change above-mentioned control signal.The above-mentioned control signal of having upgraded is then suitably replaced indicator cock circuit 16 recently the unit of fault just and/or is cancelled the replacement of the unit of present restore funcitons.In an embodiment, control signal may be discerned said units by address or any other unit identification information.
Many modern semiconductors elements adopt system-on-a-chip (SOC) design.Yet, because memory cell is responsive more for mistake, no matter be rigid or soft errors, so system-on-a-chip (SOC) chip may only become fault because of a mistake of memory module easily.As a result, the memory module mistake may reduce yield significantly and increase system-on-a-chip (SOC) production cost of chip because of the high failure rate relevant with memory module.As mentioned above, embodiment can correct the memory error of said elements as described in the present invention, and have built-in error correcting (built-inerror-correction, BEC) memory component of ability or memory module is provided thus.In an embodiment, increase redundant array and follow circuit, only increase system-on-a-chip (SOC) chip area a little, but can improve the yield of manufacture order chip system (SOC) chip because of built-in error correcting (BEC) ability.
Especially, in an embodiment, redundant array may only increase system-on-a-chip (SOC) chip area about 1.25%.As described in one embodiment of the invention, the memory module 34 of Fig. 3 takies about 1/4th of system-on-a-chip (SOC) chip 30 whole zones.In memory module 34, main array 34A takies the only about half of zone of memory module 34, or the territory, about eighth of system-on-a-chip (SOC) chip 30.If increase its size and be about 1/10th the redundant array of main array 34A, as redundant array 34B, then the system-on-a-chip that is increased (SOC) chip area approximately is 1.25% (10% * 1/8), adds a shared extra tiny area of control circuit of following redundant array 34B.
Fig. 4 is the calcspar with the on-off circuits (as program logic array (RPLA) 40 again) of three central processing units (CPU) 42,44 and 46 couplings.Program logic array (RPLA) 40 also is coupled to allow data read and to write by central processing unit (CPU) 42,44 and 46 with memory component 10 again.As shown in the figure, program logic array (RPLA) 40 comprises one in order to receive clock pulse end CK and three control end A, B and C that come 10 accesses of control store element by central processing unit (CPU) 42,44 and 46 of clock signal again.The clock signal of program logic array (RPLA) 40 may be identical or synchronous with the clock signal of operation central processing unit (CPU) 42,44 and 46 again.In addition, program logic array (RPLA) 40 may have the processor of following of a central processing unit (CPU) 20 that is similar to Fig. 1 again, in order to produce the control signal of replacing the fault memorizer unit.In order to manage the storage access that possesses multi-processor, so may comprise a sampling and a holding circuit as the described program logic arrays again of one embodiment of the invention (RPLA) 40.Above-mentioned sampling and holding circuit may be worked with dissimilar system architectures, as synchronous system or streamlined disposal system.
Fig. 5 illustrates provides a group transistor and capacitor to memory bus 10B and the sampling of central processing unit (CPU) bus 42B, 44B and 46B and the example of holding circuit 50.Especially, transistor 10T and capacitor 10C and memory bus 10B coupling.Transistor 42T and capacitor 42C and central processing unit (CPU) bus 42B coupling.Transistor 44T and capacitor 44C and central processing unit (CPU) bus 44B coupling.Transistor 46T and capacitor 46C and central processing unit (CPU) bus 46B coupling.Generally speaking, each capacitor 10C, 42C, 44C and 46C are as a data storage unit, and each is followed transistor 10T, 42T, 44T and 46T then to control the storage of stored data and/or reads.
When operation, as lock level end (gate terminal) 10G of transistor 10T is to be during at the logic low level at lock level end 42G, the 44G of logic high levle and transistor 42T, 44T and 46T and 46G, and memory component 10 will transmit data via memory bus 10B.Therefore capacitor 10C stores above-mentioned data.After this, be during when one of lock level end 42G, 44G and 46G becomes logic high levle and lock level end 52G at the logic low level, will select one of central processing unit (CPU) bus 42B, 44B and 46B to read stored data.For example, if the voltage of lock level end 42G uprises, then stored data will be sent to capacitor 42C also may be via central processing unit (CPU) bus 42B by 42 accesses of central processing unit (CPU).Similarly, sampling and holding circuit 50 may be to operate in contrast to the order of selecting lock level end, as by providing the logic high levle, data is stored in memory component 10 from central processing unit (CPU) 42 via central processing unit (CPU) bus 42B transmission and via memory bus 10B to lock level end 42G and after a while to lock level end 10G.
Be sent to lock level end 42G, 44G or 46G with since the signal of control store access may produce by a signal generator.Fig. 6 illustrates as the described signal generator 60 of one embodiment of the invention.Lock level end 52G and three control end A, B, C may provide and input to signal generator 60.Signal generator 60 produces according to above-mentioned input in order to the access of control store element and exports lock level end 42G, 44G and 46G to.
The present invention also provides a kind of operational store element so that the method for built-in error correcting ability to be provided.A kind ofly comprise: a main array that comprises plurality of memory units is provided as the described method of one embodiment of the invention; Provide a redundant array that comprises a plurality of redundancy units to replace at least one trouble unit of above-mentioned main array; Provide a control signal to discern above-mentioned trouble unit; Change above-mentioned control signal according to above-mentioned trouble unit in the malfunction of different time; And provide an on-off circuit cell signal of above-mentioned trouble unit to be switched to the unit of being replaced to receive above-mentioned control signal.
And,, may use a treatment circuit that above-mentioned control signal is provided in an embodiment.Also may provide an error detection element and with the coupling of main array with the memory cell of detecting main array, the redundancy unit of redundant array or both malfunctions.Especially, in an embodiment, may use built-in self-test device (BIST) as above-mentioned error detection element.In another embodiment, said switching circuit may comprise one with the data, the data of write store element or both program logic arrays again that read from memory component more than the coupling of processor and management.In the middle of many application as described memory component of one embodiment of the invention and method, in an embodiment, above-mentioned memory component may be an in-line memory element of following the system of manufacturing on single semi-conductor chip.
Though the present invention with its preferred embodiment openly as above; right its is not in order to limit the present invention; anyly be familiar with this operator; under the situation that does not break away from spirit of the present invention; when can doing a little change and retouching, so the scope of the present invention is as the criterion when looking claims person of defining.
Claims (20)
1. a semiconductor memery device is characterized in that, this element comprises:
One main array comprises plurality of memory units, comprising one first trouble unit and one second trouble unit;
One redundant array comprises at least one and replaces memory cell, in order to replace at least one trouble unit of this main array; And
One on-off circuit, with this main array and the coupling of this redundant array, in order to receive one first control signal one of this first trouble unit cell signal is switched to this replacement unit, and receive one second control signal and one of this second trouble unit cell signal is switched to this replacement unit, wherein this first and this second control signal discern respectively this first and this second trouble unit, and this first and this second control signal according to this first and this second trouble unit change in one of different time malfunction.
2, semiconductor memery device as claimed in claim 1 is characterized in that, also comprise one with the coupling of this on-off circuit with provide this first and the treatment circuit of this second control signal.
3, semiconductor memery device as claimed in claim 1 is characterized in that, also comprise one with this main array coupling to detect the error detection element of this malfunction.
4, semiconductor memery device as claimed in claim 1 is characterized in that, no longer this replacement unit can be in order to replace this second trouble unit during fault for this first trouble unit of being replaced when this replacement unit.
5, semiconductor memery device as claimed in claim 1 is characterized in that, this on-off circuit comprises a program logic array again.
6, semiconductor memery device as claimed in claim 1 is characterized in that, this on-off circuit and the coupling of a plurality of processor.
7, semiconductor memery device as claimed in claim 1 is characterized in that, this malfunction is a rigid mistake.
8, semiconductor memery device as claimed in claim 1 is characterized in that, this malfunction is a soft errors.
9, semiconductor memery device as claimed in claim 1 is characterized in that, this semiconductor memery device is an in-line memory element.
10. the semiconductor memery device with built-in error correcting ability is characterized in that, this element comprises:
One main array comprises plurality of memory units;
One redundant array comprises at least one and replaces the unit, and in order to replace at least one trouble unit of this main array, wherein a control signal is discerned this trouble unit, and this control signal changes in one of different time malfunction according to this trouble unit; And
One on-off circuit comprises a program logic array again that is coupled with this main array and this redundant array, also a cell signal of this trouble unit is switched to this replacement unit in order to receive this control signal.
11, semiconductor memery device as claimed in claim 10 is characterized in that, also comprises a treatment circuit that this control signal is provided.
12, semiconductor memery device as claimed in claim 10 is characterized in that, also comprise one with the error detection element of this main array coupling with this malfunction of those memory cells of detecting this main array.
13, semiconductor memery device as claimed in claim 10 is characterized in that, this replacement unit according to those trouble units in those malfunctions of different time and replace the different faults unit of this main array at different time.
14, semiconductor memery device as claimed in claim 10 is characterized in that, this on-off circuit and the data that reads from this semiconductor memery device more than the coupling of processor and management with write one of data of this semiconductor memery device.
15, semiconductor memery device as claimed in claim 10 is characterized in that, this malfunction is a rigid mistake.
16, semiconductor memery device as claimed in claim 10 is characterized in that, this malfunction is a soft errors.
17. operation one memory component is characterized in that so that the method for built-in error correcting ability to be provided this method comprises:
A main array that comprises plurality of memory units is provided;
Provide a redundant array that comprises a plurality of redundancy units, in order to replace at least one trouble unit of this main array;
Provide a control signal to discern this trouble unit;
Change this control signal according to this trouble unit in a malfunction of different time; And
One on-off circuit is provided, and the cell signal in order to receive this control signal with this trouble unit switches to this replacement unit.
18, method as claimed in claim 17 is characterized in that, also comprising provides a treatment circuit so that this control signal to be provided.
19, method as claimed in claim 17 is characterized in that, comprise provide one with the error detection element of this main array coupling with this malfunction of those memory cells of detecting this main array.
20, method as claimed in claim 17 is characterized in that, provides this on-off circuit to comprise to provide a program logic array again.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031465390A CN100437814C (en) | 2003-07-04 | 2003-07-04 | Memory element with built-in error connecting function |
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| CNB031465390A CN100437814C (en) | 2003-07-04 | 2003-07-04 | Memory element with built-in error connecting function |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105550079A (en) * | 2016-01-27 | 2016-05-04 | 中国电子科技集团公司第五十八研究所 | Multilevel redundant structure of embedded memory |
| CN105740105A (en) * | 2016-01-27 | 2016-07-06 | 中国电子科技集团公司第五十八研究所 | Redundant structure of embedded memory |
| WO2022198494A1 (en) * | 2021-03-24 | 2022-09-29 | Yangtze Memory Technologies Co., Ltd. | Memory device with failed main bank repair using redundant bank |
| WO2022198829A1 (en) * | 2021-03-24 | 2022-09-29 | Yangtze Memory Technologies Co., Ltd. | Memory device with failed main bank repair using redundant bank |
| US11769569B2 (en) | 2021-03-24 | 2023-09-26 | Yangtze Memory Technologies Co., Ltd. | Memory device with failed main bank repair using redundant bank |
| US11862270B2 (en) | 2021-03-24 | 2024-01-02 | Yangtze Memory Technologies Co., Ltd. | Memory device with failed main bank repair using redundant bank |
| WO2024051058A1 (en) * | 2022-09-05 | 2024-03-14 | 长鑫存储技术有限公司 | Fault repairing method for internal memory and device |
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Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950004623B1 (en) * | 1992-12-07 | 1995-05-03 | 삼성전자주식회사 | Semiconductor memory device with improved redundancy efficiency |
| KR100247920B1 (en) * | 1996-12-31 | 2000-03-15 | 윤종용 | Row redundancy &repair scheme in semiconductor device |
| TW499686B (en) * | 2001-03-28 | 2002-08-21 | Winbond Electronics Corp | Semiconductor memory device and its redundancy output switch |
-
2003
- 2003-07-04 CN CNB031465390A patent/CN100437814C/en not_active Expired - Lifetime
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| CN105550079A (en) * | 2016-01-27 | 2016-05-04 | 中国电子科技集团公司第五十八研究所 | Multilevel redundant structure of embedded memory |
| CN105740105A (en) * | 2016-01-27 | 2016-07-06 | 中国电子科技集团公司第五十八研究所 | Redundant structure of embedded memory |
| CN105740105B (en) * | 2016-01-27 | 2018-10-19 | 中国电子科技集团公司第五十八研究所 | A kind of redundancy structure of in-line memory |
| WO2022198494A1 (en) * | 2021-03-24 | 2022-09-29 | Yangtze Memory Technologies Co., Ltd. | Memory device with failed main bank repair using redundant bank |
| WO2022198829A1 (en) * | 2021-03-24 | 2022-09-29 | Yangtze Memory Technologies Co., Ltd. | Memory device with failed main bank repair using redundant bank |
| US11726667B2 (en) | 2021-03-24 | 2023-08-15 | Yangtze Memory Technologies Co., Ltd. | Memory device with failed main bank repair using redundant bank |
| US11769569B2 (en) | 2021-03-24 | 2023-09-26 | Yangtze Memory Technologies Co., Ltd. | Memory device with failed main bank repair using redundant bank |
| US11862270B2 (en) | 2021-03-24 | 2024-01-02 | Yangtze Memory Technologies Co., Ltd. | Memory device with failed main bank repair using redundant bank |
| US11934281B2 (en) | 2021-03-24 | 2024-03-19 | Yangtze Memory Technologies Co., Ltd. | Memory device with failed main bank repair using redundant bank |
| WO2024051058A1 (en) * | 2022-09-05 | 2024-03-14 | 长鑫存储技术有限公司 | Fault repairing method for internal memory and device |
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| CN100437814C (en) | 2008-11-26 |
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