CN1558555A

CN1558555A - Phase detector

Info

Publication number: CN1558555A
Application number: CNA200410003248XA
Authority: CN
Inventors: 蔡乙仲
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2004-01-30
Filing date: 2004-01-30
Publication date: 2004-12-29
Anticipated expiration: 2024-01-30
Also published as: CN1301594C

Abstract

A phase detector is used to detect the phase difference between a data signal and a clock signal, and to export a first rising signal whose pulse width is between 1/2 times to 3/2 times of clock signal cycle, a first down signal having the same cycle as the clock signal, a second down signal and a second rising signal to a charging pump.

Description

Phase detectors

Technical field

The present invention relates to a kind of phase detectors (Phase Detector), particularly relate to the phase detectors of a kind of use in a phase-locked loop clock answering system (Phase-locked Loop Clock Recovery System).

Background technology

For general digital signal synchronous transmission (synchronous transmission), data signals is sent to receiving terminal (receivingunit) by transmitting terminal (transmitting unit) with fixed rate.Usually, receiving terminal uses a phase-locked loop clock answering system to detect the phase difference of the clock signal of received data signals and receiving terminal, and adjusts the phase place and the frequency of the clock signal of receiving terminal.So, the clock signal of receiving terminal will be able to have same phase and same frequency with received data signals, be beneficial to receiving terminal the data signal is taken a sample and demodulation (demodulate).

Please refer to Fig. 1, Fig. 1 shows the calcspar of traditional phase-locked loop clock answering system.Tradition phase-locked loop clock answering system 100 includes phase detectors 102, a charge pumping 104, a loop filter (Loop Filter) 106 and one voltage-controlled oscillator (Voltage ControlledOscillator, VCO) 108.Phase detectors 102 are in order to detecting the phase difference (Phase Difference) of a data signals DT and a clock signal CLK, and export one first rising signal (Upsignal) UP1, one first decline signal DN2 and one second decline signal DN3 and one second rising signal UP4 accordingly to charge pumping 104.Charge pumping 104 is exported a phase error signal (Phase errorsignal) PE accordingly to loop filter 106, and this phase error signal PE corresponds to the phase difference of data signals DT and clock signal CLK.106 pairs of phase error signals of loop filter (Phase errorsignal) PE carries out after the low-pass filtering treatment, produces output signal LFO.VCO 108 adjusts frequency and the phase place of the clock signal CLK that is exported, so that clock signal CLK has phase place and the frequency identical with data signals DT according to the voltage level of signal LFO.Wherein, when the first rising signal UP1 or the second rising signal UP4 were activation, the voltage of phase error signal PE will improve, and when the first decline signal DN2 or the second decline signal DN3 were activation, the voltage of phase error signal PE will reduce.

Please refer to Fig. 2, Fig. 2 shows the detailed circuit diagram of conventional phase detector 102.Phase detectors 102 include one first D-type latch (D-type latch), 202, second D-type latch 204, the 3rd D-type latch 206, the 4th D-type latch 208, the 5th D-type latch 210, first XOR gate (Exclusive-OR gate, XOR gate), 212, second XOR gate 214, the 3rd XOR gate 216 and the 4th XOR gate 218.

The input D1 of first D-type latch 202 receives data signals DT.When clock signal CLK was low level, data signals DT was sent to the output Q1 of first D-type latch 202.The input D2 of second D-type latch 204 receives the output signal of first D-type latch 202.When clock signal CLK was high level, the output signal of first D-type latch 202 was sent to the output Q2 of second D-type latch 204.The input D3 of the 3rd D-type latch 206 receives the output signal of second D-type latch 204.When clock signal CLK was low level, the output signal of second D-type latch 204 was sent to the output Q3 of the 3rd D-type latch 206.The input D4 of the 4th D-type latch 208 receives the output signal of the 3rd D-type latch 206.When clock signal CLK was high level, the output signal of the 3rd D-type latch 206 was sent to the output Q4 of the 4th D-type latch 208.The input D5 of the 5th D-type latch 210 receives the output signal of the 4th D-type latch 208.When clock signal CLK was high level, the output signal of the 4th D-type latch 208 was sent to the output Q5 of the 5th D-type latch 210.

First XOR gate 212 produces the first rising signal UP1 according to the output signal of the data signals DT and second D-type latch 204.Second XOR gate 214 produces the first decline signal DN2 according to the output signal of second D-type latch 204 and the output signal of the 3rd D-type latch 206.The 3rd XOR gate 216 produces the second decline signal DN3 according to the output signal of the 3rd D-type latch 206 and the output signal of the 4th D-type latch 208.The 4th XOR gate 218 produces the second rising signal UP4 according to the output signal of the 4th D-type latch 208 and the output signal of the 5th D-type latch 210.

Please refer to Fig. 3, Fig. 3 shows the signal waveform figure of the phase detectors 102 of Fig. 2.Suppose that with the high level signal be enable signal.The leading edge of the first rising signal UP1 will be along with the leading edge of data signals DT or trailing edge and is changed.When the leading edge of data signals DT or the positive edge (rising edge) of the leading clock signal CLK of trailing edge (or negative edge (falling edge)), the mean value of the phase error signal PE that charge pumping 104 is exported will rise, with the frequency of the clock signal that increases VCO 108 outputs and accelerate its phase place; And when the leading edge of data signals DT or trailing edge fell behind the positive edge of clock signal CLK or negative edge, the mean value of the phase error signal PE that charge pumping 104 is exported will descend, with frequency and its phase place that slows down of the clock signal that reduces VCO108 output.

The pulse duration of the first rising signal UP1 of traditional phase detectors 102 is 0 times to 1 times of cycle of clock signal CLK, and the pulse duration of the first decline signal DN2, the second decline signal DN3, the second rising signal UP4 only is 1/2 times of periodic width of clock signal CLK.When data signals DT falls behind clock signal CLK near cycle of 1/2 clock signal CLK, phase detectors 102 may take place on the contrary take for the leading clock signal CLK of data signals DT, and the pulse that produces the first a large amount of rising signal UP1, and accelerate the phase place of clock signal CLK and improve the frequency of clock signal CLK.So, cause phase-locked loop clock answering system 100 to lock most probably, or must spend the long time finish locking.This kind situation more often occurs under the initial state.Therefore, the phase locking scope of traditional phase-locked loop clock answering system 100 only is that phase difference circle is under the situation between 180 degree and-180 degree.

In addition, when the level conversion (transition) of data signals DT just produced with the same time point of the positive edge of clock signal CLK, traditional phase detectors 102 produced probably that phase error signal PE disperses and the situation that can't lock.Please refer to Fig. 4, Fig. 4 shows the signal waveform figure of the phase detectors 102 when the level conversion of data signals DT just produces with the same time point of the positive edge of clock signal CLK.At this moment, first XOR gate 212 may misjudgment, and makes the first rising signal UP1 constantly produce pulse.So, will make phase error signal PE continue rise and disperse, and make traditional phase-locked loop clock answering system 100 to lock or time of locking long.

Tradition phase-locked loop clock answering system 100 also may change its current potential because of unstable (jitter) or noise, and produce misoperation except above-mentioned shortcoming.Please refer to Fig. 5, Fig. 5 shows another oscillogram of conventional phase detector 102.When the width of the pulse 502 of data signals DT cycle less than a clock signal CLK, and when the positive edge of this pulse occurs in clock signal CLK and is high level, though first rising signal UP1 this moment produces pulse 504, the first decline signal DN2, the second decline signal DN3 accordingly and the second rising signal UP4 does not have corresponding pulse generation.So, may cause the drift that makes progress of the DC level of phase error signal PE, and may cause phase error signal PE to disperse and phase-locked loop clock answering system 100 can't be pinned.

Please refer to Fig. 6, Fig. 6 shows the another oscillogram of conventional phase detector 102.When clock signal CLK takes place and is high level in the negative edge 602A of the pulse 602 of data signals DT, and the positive edge 604A of the next pulse 604 of data signals DT and negative edge 602A are at a distance of the cycle less than 1/2 clock signal CLK, and when positive edge 604A occurs in clock signal CLK and is low level, similarly, though first rising signal UP1 this moment produces pulse 606, the first decline signal DN2, the second decline signal DN3 accordingly and the second rising signal UP4 does not have corresponding pulse generation.So, similarly may cause the drift that makes progress of the DC level of phase error signal PE, and may cause phase error signal PE to disperse and phase-locked loop clock answering system 100 can't be pinned.

Summary of the invention

In view of this, the purpose of this invention is to provide a kind of phase detectors, can solve traditional phase detectors causing the phase error signal to be dispersed effectively and problem that phase-locked loop clock answering system can't be pinned.

According to purpose of the present invention, a kind of phase detectors are proposed, comprise the one first to the 6th latch, first gate, reach one first to fourth SR type latch.Wherein, first latch has a first input end, in order to receive data signals.First latch is by first level institute activation of clock signal.Second latch has one second input, in order to receive the signal that first latch is exported.Second latch is by second level institute activation of clock signal.The 3rd latch has one the 3rd input, in order to receive the signal that second latch is exported.The 3rd latch is by first level institute activation of clock signal.Quad latch has a four-input terminal, and in order to receive the signal that the 3rd latch is exported, quad latch is by the second level institute activation of clock signal.The 5th latch has one the 5th input, in order to receive the signal that quad latch is exported.The 5th latch is by first level institute activation of clock signal.The 6th latch has one the 6th input, and in order to receive the signal that the 5th latch is exported, the 6th latch is by second level institute activation of clock signal.First gate is in order to handle the output signal of second latch and the output signal of the 3rd latch.The one SR type latch has one first and end and one first end of resetting is set receives the output signal of the data signals and first gate respectively, and exports the first rising signal.The 2nd SR type latch has one second and end and one second end of resetting is set receives the output signal of second latch and the output signal of quad latch respectively, and exports the first decline signal.Three S's R type latch has one the 3rd end and one the 3rd replacement end is set, and receives the output signal of the 3rd latch and the output signal of the 5th latch respectively, and exports the second decline signal.And the 4th SR type latch have one the 4th be provided with the end with a quadruple put end, receive the output signal of quad latch and the output signal of the 6th latch respectively, and export the second rising signal.

According to another object of the present invention, a kind of phase detectors are proposed, in order to detecting the phase difference of a data signals and a clock signal, and export the first rising signal, one first decline signal, one second decline signal and one second rising signal to a charge pumping.Charge pumping is exported a phase error signal accordingly, and the waveform of clock signal, data signals, the first rising signal, the first decline signal, the second decline signal and the second rising signal is the impulse form waveform with one first edge and one second edge.Phase detectors comprise one first rising signal generating circuit, the first decline signal generating circuit, the second decline signal generating circuit and the second rising signal generating circuit.The first rising signal generating circuit is in order to receive data signals and to produce the first rising signal.When data signals produced first edge, the first rising signal also produced first edge, and afterwards, when clock signal produced second edge, the first rising signal produced second edge.The first decline signal generating circuit is in order to produce the first decline signal, after the first rising signal produced first edge, when clock signal produced first edge, the first decline signal produced first edge, and at all after dates of a clock signal, the first decline signal produces second edge.

The second decline signal generating circuit is in order to produce the second decline signal.After the first decline signal produced first edge, when clock signal produced second edge, the second decline signal produced first edge, and at all after dates of a clock signal, the second decline signal produces second edge.The second rising signal generating circuit then is in order to produce the second rising signal.After the second decline signal produced first edge, when clock signal produced first edge, the second rising signal produced first edge, and at all after dates of a clock signal, the second rising signal produces second edge.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and formula is described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

Fig. 1 shows the calcspar of traditional phase-locked loop clock answering system;

Fig. 2 shows the detailed circuit diagram of conventional phase detector;

Fig. 3 shows the signal waveform figure of the phase detectors of Fig. 2;

Fig. 4 shows the signal waveform figure of the phase detectors when the level conversion of data signals just produces with the same time point of the positive edge of clock signal;

Fig. 5 shows another oscillogram of conventional phase detector;

Fig. 6 shows the another oscillogram of conventional phase detector;

Fig. 7 shows the circuit block diagram of the phase detectors of the first embodiment of the present invention;

Fig. 8 shows the signal waveform figure of the phase detectors of the present invention of Fig. 7;

Fig. 9 shows another signal waveform figure of phase detectors of the first embodiment of the invention of Fig. 7;

Figure 10 shows the circuit block diagram of the phase detectors of second embodiment of the invention; And

Figure 11 shows the signal waveform figure of phase detectors of the second embodiment of the invention of Figure 10.

The drawing reference numeral explanation

100: phase-locked loop clock answering system

102,700,1000: phase detectors

104: charge pumping

106: loop filter

108: voltage-controlled oscillator

202,204,206,208,210:D type latch

212,214,216,218: XOR gate

702,704,706,708,710,712,1002,1004: latch

720,722,724:726:SR type latch

730,1006: with gate

604A, 802,810,812,820,822,826,830,832,902B, 904A: positive edge

602A, 804,806,808,824,828,836,902A, 904A, 906: negative edge

502,504,602,604,606,814,816,818,902,904: pulse

1008: or gate

Embodiment

For overcoming the problem that causes the phase error signal to be dispersed phase-locked loop clock answering system can't be pinned of conventional phase detector, so the width of pulse of the first rising signal UP1 ' that makes phase detectors of the present invention in design is between 1/2 times of cycle to 3/2 times of clock signal CLK ', the width of the pulse of the first decline signal DN2 ', the second decline signal DN3 ', the second rising signal UP4 ' equals the cycle of clock signal CLK '.The pulse duration of the first rising signal UP1 will be along with the difference of the negative edge of clock signal CLK ' and data signals DT ' and is changed.In addition, the negative edge of the pulse of the first rising signal UP1 ' of the present invention will be aimed at the negative edge of clock signal CLK ', and the pulse of itself and data signals DT ' is irrelevant.

Phase detectors of the present invention only detect the positive edge of pulse of data signals DT ' or negative edge both one of, positive edge and negative edge that this and conventional phase detector shown in Figure 2 detect the pulse of data signals DT simultaneously are inequality.Following examples are that the positive edge that only detects the pulse of data signals DT ' with phase detectors of the present invention is the example explanation.If make phase detectors of the present invention only detect the negative edge of the pulse of data signals DT ', only need allow data signals DT ' earlier through behind the inverter, import phase detectors of the present invention again and can realize.

Phase detectors of the present invention can be applicable in the clock answering system of phase-locked loop.Phase-locked loop clock answering system comprises phase detectors, charge pumping, loop filter and the voltage-controlled oscillator as Fig. 1.We represent with distinct symbols at this, phase detectors for example of the present invention are in order to detecting the phase difference of data signals DT ' and clock signal CLK ', and export the first rising signal UP1 ', the first decline signal DN2 ', the second decline signal DN3 ' and the second rising signal UP4 ' according to this to charge pumping.Charge pumping is exported a phase error signal PE ' accordingly.Loop filter is in order to receiving phase error signal PE '.Voltage-controlled oscillator then is the output signal in order to the receiving loop filter, and output clock signal CLK '.Wherein, the waveform of clock signal CLK ', data signals DT ', the first rising signal UP1 ', the first decline signal DN2 ', the second decline signal DN3 ' and the second rising signal UP4 ' is has one first edge, it for example is positive edge, with one second edge, for example be negative edge, the impulse form waveform.And clock signal CLK ' has one first level branch (first level portion), for example is the low level branch, with one second level branch, for example is the high level branch.

Charge pumping has an electric capacity and a plurality of current source (current source), and when the first rising signal UP1 ' was activation with the second rising signal UP4 ', these current sources charged to electric capacity, to improve the voltage potential of phase error signal PE '.When the first decline signal DN2 ' was activation with the second decline signal DN3 ', these current sources systems were to capacitor discharge, to reduce the voltage potential of phase error signal PE '.

Embodiment one

Please refer to Fig. 7, Fig. 7 shows the circuit block diagram of the phase detectors of the first embodiment of the present invention.Phase detectors 700 of the present invention comprise one first latch 702, second latch 704, the 3rd latch 706, quad latch 708, the 5th latch 710, the 6th latch 712, first gate (logic gate), a SR type latch 720, the 2nd SR type latch 722, Three S's R type latch 724 and the 4th SR type latch 726.Wherein, first, second and third latch 702,704 and 706, first gate 730 and a SR type latch 720 are combined into the first rising signal generating circuit, and it receives data signals DT ' and clock signal CLK ', produces the first rising signal UP1 '.First to fourth latch 702 to 708 and the 2nd SR type latch 722 are to be combined into the first decline signal generating circuit, also receive data signals DT ' and clock signal CLK ', produce the first decline signal DN2 '.First to the 5th latch 702 to 710 and Three S's R type latch 724 are combined into the second decline signal generating circuit, also receive data signals DT ' and clock signal CLK ', produce the second decline signal DN3 '.And first to the 6th latch 702 to 712 and the 4th SR type latch 726 are combined into the second rising signal generating circuit, also receive data signals DT ' and clock signal CLK ', produce the first rising signal UP4 '.Wherein, first to the 6th latch 702 to 712 is a D-type latch, and first gate is and gate (AND gate) 730.

Each D-type latch has an input D, an output Q and an activation end E.Each SR type latch then has one end S, a replacement end R and an output Q is set.Clock signal CLK ' inputs to the activation end E of each D-type latch, with activation (enable) or each D-type latch of disabled (disable).When latch is enabled, the signal of importing from input D will directly be sent to output Q.And when latch during by disabled, the output signal of output Q will maintain the current potential before the disabled.In addition, the truth table of RS type latch (true table) is then as table one:

Table one

??S	??R	??Q
??S	??R	??Q	??0	??0	??Q
??0	??1	??0	??0	??0	??Q
??0	??1	??0	??1	??0	??1
??1	??1	??0	??1	??0	??1

First latch 702 has a first input end D1, in order to receiving data signals DT ', and by the low level institute activation of clock signal CLK '.Second latch 704 has one second input D2, in order to receiving the signal that first latch 702 is exported, and by the high level branch activation of clock signal CLK '.The 3rd latch 706 has one the 3rd input D3, in order to receiving the signal that second latch 704 is exported, and by the low level branch activation of clock signal CLK '.Quad latch 708 has a four-input terminal D4, in order to receiving the signal that the 3rd latch 706 is exported, and by the high level institute activation of clock signal CLK '.The 5th latch 710 has one the 5th input D5, in order to receiving the signal that quad latch 708 is exported, and by the low level institute activation of clock signal CLK '.The 6th latch 712 has one the 6th input D6, in order to receiving the signal that the 5th latch 710 is exported, and by the high level institute activation of clock signal CLK '.

Carry out and computing (AND operation) in order to output signal with gate 730 output signal of second latch 704 and the 3rd latch 706.The one SR type latch 720 has one first end Sa and one first replacement end Ra is set, and receives the output signal of data signals DT ' and gate 730 respectively, and exports the first rising signal UP1 '.The 2nd SR type latch 722 has one second end Sb and one second replacement end Rb is set, and receives the output signal of second latch 704 and the output signal of quad latch 708 respectively, and exports the first decline signal DN2 '.Three S's R type latch 724 has one the 3rd end Sc and one the 3rd replacement end Rc is set, and receives the output signal of the 3rd latch 706 and the output signal of the 5th latch 710 respectively, and exports the second decline signal DN3 '.The 4th SR type latch 726 has one the 4th and end Sd and a quadruple are set put end Rd, receives the output signal of quad latch 708 and the output signal of receipts the 6th latch 712 respectively, and exports the second rising signal UP4 '.

Please refer to Fig. 8, Fig. 8 shows the signal waveform figure of the phase detectors of the present invention of Fig. 7.Now represent first latch, 702 output signals respectively to quad latch 708 with signal Q1, Q2, Q3 and Q4, and with the output signal of signal Q2, Q3 representative with gate 730.When the phase-locked loop clock answering system as Fig. 1 locked, the present invention can be locked in the negative edge of clock signal CLK ' the positive edge part of data signals DT ' with the phase detectors among Fig. 7.For example shown in Figure 8, when the positive edge 802 of the negative edge 804 of clock signal CLK ' and data signals DT ' trimmed, phase-locked loop clock answering system was then finished locking.

When data signals DT ' produced positive edge, the first rising signal UP1 ' of above-mentioned first rising signal generating circuit output also produced positive edge.Afterwards, when edge was born in clock signal CLK ' generation, the first rising signal UP1 ' produced negative edge.Because the negative edge of the pulse of the first rising signal UP1 ' of the present invention will be aimed at the negative edge of clock signal CLK ', for example negative edge 806 is aimed at negative edge 808, and the positive edge of the pulse of the first rising signal UP1 ' is with the positive edge of aligned data signal DT ', for example positive edge 810 is aimed at positive edge 812, so the pulse duration of the first rising signal UP1 ' will be along with the difference of the negative edge of the positive edge of data signals DT ' and clock signal CLK ' and is changed, as pulse 814,816 and 818.

After the first rising signal UP1 ' produced positive edge 810, when clock signal CLK ' produced positive edge 820, the first decline signal DN2 ' of above-mentioned first decline signal generating circuit output produced positive edge 822.And at all after dates of a clock signal CLK ', the first decline signal DN2 ' produces negative edge 824.After the first decline signal DN2 ' produced positive edge 822, when edge 808 was born in clock signal CLK ' generation, the second decline signal DN3 ' of above-mentioned second decline signal generating circuit output produced positive edge 826.And at all after dates of a clock signal CLK ', the second decline signal DN3 ' produces negative edge 828.After the second decline signal DN3 ' produced positive edge 826, when clock signal CLK ' produced positive edge 830, the second rising signal UP4 ' of above-mentioned second rising signal generating circuit output produced positive edge 832.And at all after dates of a clock signal CLK ', the second rising signal UP4 ' produces negative edge 836.

The phase detectors 700 of the first embodiment of the present invention of Fig. 7 can solve the problem that may cause phase error signal PE to disperse of conventional phase detector 102 shown in Figure 6.Please refer to Fig. 9, Fig. 9 shows another signal waveform figure of phase detectors of the first embodiment of the invention of Fig. 7.Fig. 9 shows when the negative edge 902A of the pulse 902 of data signals DT ' takes place clock signal CLK ' for high level, and the positive edge 904A of the next pulse 904 of data signals DT ' and negative edge 902A be at a distance of less than cycle of 1/2 clock signal CLK ', and the situation of positive edge 904A when occurring in clock signal CLK ' for low level.

Operating principle according to the phase detectors 700 of the first embodiment of the present invention judges that the negative edge 906 of clock signal CLK ' should be locked to the positive edge 902B part of the pulse 902 of data signals DT ', and makes the pulse duration lengthening of the first rising signal UP1 '.Yet because the negative edge 902A of data signals DT ' is too short with the spacing of positive edge 904A, this kind situation is because noise or the unstable abnormal state that is caused mostly.Phase detectors 700 of the present invention utilize output signal Q2, the Q3 of signal and gate 730, be input to first of first latch 702 respectively with data signals DT ' end Sa and one first replacement end Ra are set, characteristic (Sa=0 with SR type latch, during Ra=1, UP1 ' keeps 0 output), and neglect the positive edge 904A of data signals DT ', and make the first rising signal UP1 ' under this situation, can not produce the pulse that corresponds to positive edge 904A, stable in the hope of phase error signal PE '.Cause the practice of phase error signal PE level drift to compare with conventional phase detector 102 in the pulse that still produces one first rising signal UP in such cases, the present invention can avoid the level drift of phase error signal PE effectively even disperse, and gets so that phase-locked loop clock answering system is able to quick lock in.

In order to solve another problem of conventional phase detector 102 as shown in Figure 5, can in the phase detectors 700 of first embodiment, add a compensating circuit, with obtain hereinafter described of the present invention second

The phase detectors of embodiment.

Embodiment two

Please refer to Figure 10, Figure 10 shows the circuit block diagram of the phase detectors of second embodiment of the invention.Different with the first embodiment phase detectors 700 is, the first rising signal generating circuit of the second embodiment phase detectors 1000 also has a compensating circuit, and this compensating circuit comprises one the 7th latch 1002, one the 8th latch 1004, one or gate 1008 and one second gate.Second gate is and gate 1006.

The 7th latch 1002 has one the 7th input D7, in order to receiving data signals DT ', and by the high level branch activation of clock signal CLK '.The 8th latch 1004 has one the 8th input D8, in order to receiving the output signal of the 7th latch 1002, and by the low level branch activation of clock signal CLK '.Carry out and logical operation in order to anti-phase signal with gate 1006 output signal of the output signal of the 8th latch 1004 and the 3rd latch 706.Wherein, data signals DT ' and with the output signal S of gate 1006 be import simultaneously or gate 1008 in, carry out or (OR) after the logical process, obtain signal DT " to input to the first input end D1 of first latch 702.

The compensating circuit of the phase detectors 1000 of second embodiment, the signal DT that produces "; replaces the pulse of too short data signals DT '; and do or (OR) logical process; to reach the pulse that prolongs too short data signals DT '; further produce pulse then, so that the first decline signal DN2 ', the second decline signal DN3 ', the second rising signal UP4 ' are produced corresponding pulse than the first rising signal UP1 ' of length by output signal S and data signals DT '.By this, the phase detectors 1000 of second embodiment of the invention can solve the problem that may cause phase error signal PE to disperse of conventional phase detector 102 shown in Figure 5.

Please refer to Figure 11, Figure 11 shows the signal waveform figure of phase detectors of the second embodiment of the invention of Figure 10.Signal Q1V ', Q2V ' and Q3V ' representative does not have first, second and third latch 702,704 of compensating circuit and 706 original output signal, and signal Q1V ", Q2V " and Q3V " representative adds first, second and third latch 702,704 after the compensating circuit and 706 output signal.Q7 and Q8 represent the output signal of the 7th and the 8th latch 1002 and 1004.When the width of the pulse 1102 of data signals DT ' cycle less than a clock signal CLK ', and when the positive edge 1102A of pulse 1102 occurs in clock signal CLK ' for high level, by compensating circuit, the first rising signal UP1 ' will produce width the pulse 1104 for grow of pulse duration than pulse 1102 accordingly, make the decline signal DN2 ' that wins, the second decline signal DN3 ' and the second rising signal UP4 ' be able to the

corresponding pulse

1106,1108 and 1110 that produces respectively.So, can avoid phase error signal PE ' to disperse and problem that phase-locked loop clock answering system can't be pinned.

The disclosed phase detectors of above-mentioned first embodiment of the present invention and second embodiment have the following advantages.At first, because the phase detectors 102 that the umber of pulse that rising signal UP1 ' of the present invention and UP4 ', decline signal DN2 ' and decline signal DN3 ' are produced is more traditional are few, so the change in voltage of the pairing phase error signal of the present invention is comparatively slow, also comparatively stable, simultaneously, more be not subjected to noise and unsettled influence yet.

Secondly, traditional phase detectors 102 are because relatively poor to unsettled tolerance, thus make rising signal UP1 and UP4 and decline signal DN2 and DN3 generation mistake easily, as Fig. 5 and shown in Figure 6.And phase detectors of the present invention have reinforcement to unsettled disposal ability, thereby avoid the level drift of phase error signal PE ' even the situation of dispersing, and get so that phase-locked loop clock answering system quick lock in.

In addition, because data signals DT ' separates timing at receiving terminal, tend to because the influence of manufacturing factor or external factor, and cause the positive edge of data signals DT ' and the negative edge can't balance (Non-balance), that is, the phase difference of the positive edge of data signals DT ' and the negative edge of clock signal is with the phase difference of the negative edge of the negative edge of data signals DT ' and clock signal and unequal.Such phenomenon is great tests for general phase detectors.Because phase detectors of the present invention only grasp the phase difference that one of the positive edge of data signals DT ' or negative edge detect the negative edge of itself and clock signal, so when data signals DT ' is subjected to the influence of all factors and makes pulse duration change, and cause the positive edge of data signals DT ' and negative edge can't balance the time, can't have influence on the normal running of phase detectors of the present invention.

And, since the pace of change of rising signal UP1 ' of the present invention and UP4 ' and decline signal DN2 ' and DN3 ' tradition slowly, and can save circuit area so that the value of the resistance capacitance of use required for the present invention can be more traditional is little.

In addition, the pulse duration of traditional rising signal UP1 and UP4 and decline signal DN2 and DN3 is about the cycle of 0-1 clock signal doubly.When pulse duration was narrower, pulse duration and phase difference had no longer included direct relation, but were subjected to the positive edge of data signals DT and the influence of negative edge.Therefore, the pulse duration of its rising signal UP1 and UP4 and decline signal DN2 and DN3 is uneven, and otherness is bigger.And the pulse duration of rising signal UP1 ' of the present invention and UP4 ' and decline signal DN2 ' and DN3 ' is bigger, the cycle that is about 1/2 times to 3/2 times clock signal, its influence that is subjected to the positive edge of data signals DT ' and negative edge is less, and the pulse duration of rising signal UP1 ' and UP4 ' and decline signal DN2 ' and DN3 ' is also comparatively approaching.Moreover, because the speed that rising signal UP1 ' and UP4 ' and decline signal DN2 ' and DN3 ' voltage level switch is more not frequent, so the present invention also has the advantage of comparatively power saving.

In sum; though the present invention discloses as above with a preferred embodiment; but it is not in order to limit the present invention; those skilled in the art under the premise without departing from the spirit and scope of the present invention; can be used for a variety of modifications and variations, so protection scope of the present invention is as the criterion with claim of the present invention.

Claims

1. phase detectors comprise:

One first latch has a first input end, and in order to receive a data signals, this first latch is the one first level institute activation by this clock signal;

One second latch has one second input, and in order to receive the signal that this first latch is exported, this second latch is the one second level institute activation by this clock signal;

One the 3rd latch has one the 3rd input, and in order to receive the signal that this second latch is exported, the 3rd latch is this first level institute activation by this clock signal;

One quad latch has a four-input terminal, and in order to receive the signal that the 3rd latch is exported, this quad latch is this second level institute activation by this clock signal;

One the 5th latch has one the 5th input, and in order to receive the signal that this quad latch is exported, the 5th latch is this first level institute activation by this clock signal;

One the 6th latch has one the 6th input, and in order to receive the signal that the 5th latch is exported, the 6th latch is this second level institute activation by this clock signal;

One first gate is in order to handle the output signal of this second latch and the output signal of the 3rd latch;

One the one SR type latch has one first end and one first replacement end is set, and receives the output signal of this data signals and this first gate respectively, and exports one first rising signal;

One the 2nd SR type latch has one second end and one second replacement end is set, and receives the output signal of this second latch and the output signal of this quad latch respectively, and exports one first decline signal;

One Three S's R type latch has one the 3rd end and one the 3rd replacement end is set, and receives the output signal of the 3rd latch and the output signal of the 5th latch respectively, and exports one second decline signal; And

One the 4th SR type latch, have one the 4th be provided with the end with a quadruple put end, receive the output signal of this quad latch and the output signal of the 6th latch respectively, and export one second rising signal.

2. phase detectors as claimed in claim 1, wherein this first level is a low level, this second level is a high level.

3. phase detectors as claimed in claim 1, wherein this first latch, this second latch, the 3rd latch, this quad latch, the 5th latch and the 6th latch are D-type latch.

4. phase detectors as claimed in claim 1, wherein this first gate is and gate.

5. phase detectors as claimed in claim 1, wherein these phase detectors also comprise:

One the 7th latch has one the 7th input, and in order to receive this data signals, the 7th latch is this second level institute activation by this clock signal;

One the 8th latch has one the 8th input, and in order to receive the output signal of the 7th latch, the 8th latch is this first level institute activation by this clock signal;

One second gate is handled in order to the anti-phase signal to the output signal of the output signal of the 8th latch and the 3rd latch; And

One or gate, receive the output signal of this data signals and this second gate, produce one and revise data signals, with first of this first input end that replaces this first latch that this data signals imported and a SR type latch end is set.

6. phase detectors as claimed in claim 5, wherein this second gate is and gate.