CN1556604A - Frame head detecting device of STM-1 structure in SDH system and method - Google Patents
Frame head detecting device of STM-1 structure in SDH system and method Download PDFInfo
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Abstract
The invention discloses a frame head detecting device and method for STM-1 structure in SDH system, which includes: data byte bit compound processing model, which is used for the recombination of byte bits, the b its width data in the device are shifted circularly into a 8 channels data flow; the frame head detecting mark model includes 8 branches, which are connected to 8 channel data, it sends out frame head pulse when detecting the frame head, it carries on frame head mark signal automatic reset when detecting the frame head mark reset signal pulse; and data frame head selecting model, which is used to select the frame head mark signal with frame head pulse and the correspondent branches' data flow output, at the same time, the unique of the frame head signal are detected, when receives several frame head mark signals, it sends out frame head mark reset signal. The invention can carry on frame head detection to STM-1 data flow after through the CDR clock restoration circuit, frequency dividing and speed conversion.
Description
Technical field
The present invention relates to the SDH transmission field of the communications field, relate in particular to the data frame head checkout gear and the detection method of STM-1 structure in the synchronous number system of a kind of SDH.
Background technology
The STM-1 data flow is with the transmission of a kind of form of frame, and the STM-1 data are carried out overhead processing and take out from the STM-1 data referring to that the clock data flow refers to that clock resolves and adjust, and at first must determine the border of frame, determines that the border need know the position at frame head place.In modern communications, be to realize the high-speed transfer of data, usually with data and clock signal from propagating with single line; When receiving signal, recover clock and data, carry out frequency division and rate transition again by clock recovery circuitry.For the speed of recovering to come out is the data flow of 155M, if 10 adjacent bits are b1, b2, b3, b4, b5, b6, b7, b8, b9, b10 arbitrarily, because the border of original byte can't be known by system, thereby originally b1, b2, b3, b4, b5, b6, b7, b8 were 8 bits of a byte; After 8 frequency division rate transition, b2, b3, b4, b5, b6, b7, b8, b9 may be exported as a byte, also b3, b4, b5, b6, b7, b8, b9, b10 may be exported as a byte.
Name is called in the U.S. Patent No. 5132991 of " Frame error detection system " and discloses a kind of SDH frame head detection system, can detect OC-3 and OC-12 parallel data stream, by detecting continuous specified byte, during as OC-3, have or not the A1A1A1A2A2A2 data to judge whether present frame is effective in the detection data flow.But the data flow byte border that this system does not consider does not into have in advance definite situation.
Yet in high-speed communication, the bitstream data of recovering out by clock recovery circuitry is after rate transition, because the border of byte in advance and do not know, possibility byte at this moment is made up of adjacent 8 bits of adjacent two bytes in original front and back, thereby not A1A1A1A2A2A2 data are gone up on the surface in the data flow at this moment, cause system to detect and fail.
Name is called in the U.S. Patent No. 5710774 of " Frame synchronizing device " and discloses a kind of frame synchronization equipment, detect the serial high speed stream of current arrival earlier according to time slot, have or not continuous 12 A1 and 12 A2 to discern frame head by detecting in the data flow.
But this device can't detect the in advance ignorant parallel STM-4 structured data stream of byte boundary, does not also detect STM-1 structured data stream.Briefly, this device can only detect the frame head of the STM-4 structured data of serial.Can't detect the frame head of the STM parallel data stream that CDR comes out.
In addition, after the optical fiber hot plug, enter the parallel data stream of frame head checkout gear, the bit combination of its byte may have new variation again.This detects the new problem brought to frame head, and promptly the frame head checkout gear must be known the bit combination of byte in the current parallel data stream at any time.In communication system, many times to carry out hot line job, system must possess the performance that can recover normal operating conditions after the hot plug automatically.General STM-1 frame head checkout gear has not satisfied these new needs.
In a word, after STM-1 data flow process CDR clock recovery circuitry, frequency division and the rate transition, the byte bit combination has randomness in the data flow, and the frame head checkout gear of existing STM-1 structure can not realize that frame head detects, can not after the optical fiber hot plug, recover its normal operating conditions automatically.
Summary of the invention
The technical problem to be solved in the present invention provides the frame head checkout gear of STM-1 structure in a kind of SDH system, can detect the frame head position that the byte bit combination has the STM-1 data flow of randomness.
In order to solve the problems of the technologies described above, the invention provides the frame head checkout gear of STM-1 structure in a kind of SDH system, it is characterized in that comprise: data byte bit compound processing model, frame head certification mark module, data frame head are selected module, wherein:
Described data byte bit compound processing model is used for reconfiguring of byte bit, and the datacycle displacement of 8 bit widths that enter this device is formed 8 circuit-switched data stream;
Described frame head certification mark module comprises 8 frame head certification mark branch roads, receives described 8 circuit-switched data stream respectively, produces corresponding frame head marking signal and data flow and exports together, and each frame head certification mark branch road comprises:
The frame head detecting unit is used for detecting current data and has or not frame head, and determines the frame head position;
The pulse-triggered unit is used for when detecting frame head, produces a frame head pulse in the frame head marking signal;
Described data frame head is selected module, comprising:
The branch road selected cell is used to receive the output of described 8 frame head certification mark branch roads, therefrom selects to have the frame head marking signal and the output of corresponding branch road data flow of frame head pulse.
Another technical problem that the present invention will solve provides the frame head checkout gear of STM-1 structure in a kind of SDH system, can be after the optical fiber hot plug normal operating conditions of automatic recovery system.
In order to address this problem, on the basis of said apparatus, select module to increase at the data frame head:
The hot plug detecting unit is used for when a more than marking signal has the frame head pulse, sending frame head sign reset signal at the frame head marking signal that detects described 8 frame head certification mark branch roads output;
Simultaneously, also increased at each frame head certification mark branch road:
Frame head marking signal reset unit is used for when receiving described frame head sign reset signal the frame head marking signal in the branch road being resetted.
Said apparatus also can have following characteristics: the frame head detecting unit has or not six continuous byte datas of A1A1A1A2A2A2 to determine to have or not frame head in the current data by detecting in the current data stream, and the pulse-triggered unit produces a frame head index pulse in last A2 byte of detected frame head.
Said apparatus also can have following characteristics: the data flow of described 8 bit widths is the data flow of 19M.
The another technical problem that the present invention will solve provides the frame head detection method of STM-1 structure in a kind of SDH system, can detect the frame head position that the byte bit combination has the STM-1 data flow of randomness.
In order to solve this technical problem, the invention provides the frame head detection method of STM-1 structure in a kind of SDH system, may further comprise the steps:
(a) 8 bit width data flow are carried out cyclic shift, produce 8 tunnel 8 bit width data flow;
(b) 8 circuit-switched data flow points do not enter 8 branch roads and carry out frame head and detect, if in the current data stream frame head identification byte is arranged, then send the frame head pulse in the frame head marking signal;
(c) the frame head marking signal and the data flow of each branch road are exported;
(d) select to have the frame head marking signal of frame head pulse and data flow output accordingly thereof.
Normal operating conditions for automatic recovery system after the optical fiber hot plug, above-mentioned frame head detection method step (b) and (c) between, also add step (b1): check to have or not frame head sign reset signal have then present frame leader will signal reset, otherwise directly carry out (c) to each branch road; Simultaneously, whether between described step (c) and step (d), also add step (c1): detecting to have in the frame head marking signal of each branch road has the frame head pulse on the more than one marking signal, if, then send frame head sign reset signal, and continue to detect, otherwise execution in step (d).
Said method also can have following characteristics: in described step (b), if in the current data stream continuous A1A1A1A2A2A2 byte is arranged, then the frame head marking signal corresponding to this successive byte in the position of last A2 byte send the frame head pulse.
Said method also can have following characteristics: it is characterized in that the data flow of 8 bit widths in the described step (a) is the STM-119M data flow after CDR clock recovery circuitry, frequency division and rate transition.
As from the foregoing, the present invention can solve the frame head detection of the STM-1 data flow after CDR clock recovery circuitry, frequency division and rate transition.Also available the device of STM-1 data flow that other byte bit combination is had randomness realizes that frame head detects.Install when in running order at this, plug optical fiber arbitrarily, normal operating conditions can both be recovered automatically by system, has the hot plug function.
Description of drawings
Fig. 1 is the applied environment schematic diagram of the embodiment of the invention;
Fig. 2 is the submodule figure of the embodiment of the invention;
Fig. 3 is the oscillogram of the embodiment of the invention;
Fig. 4 is the flow chart of embodiment of the invention method.
Embodiment
The applied environment of embodiment of the invention STM-1 frame head checkout gear as shown in Figure 1, fine line is represented clock signal among the figure, heavy line is represented data flow.The STM-1 bit data flow of the 155M that recovers out through CDR and 155M clock carry out 8 frequency divisions and obtain (CDR itself has the function of frequency division) the clock CLK_TI of 19M and the 19M data flow DATA_TI[7:0 of 8 bit widths], enter STM-1 frame head checkout gear.Header signal IFP that after this device is handled, detects and correct data flow RD[7:0] send into spending process module and carry out overhead processing etc.
As shown in Figure 2, the STM-1 frame head checkout gear of present embodiment comprises data byte bit compound processing model 11, frame head certification mark module 12, the selection of data frame head and hot plug processing module 13, wherein:
Data byte bit compound processing model 11 is used for reconfiguring of byte bit, and the 19M datacycle displacement of 8 bit widths that enter this device is formed 8 circuit-switched data stream;
Frame head certification mark module 12 comprises 8 frame head certification mark branch roads, receives described 8 circuit-switched data stream respectively, produces corresponding frame head marking signal and data flow and exports together, and each frame head certification mark branch road comprises:
The frame head detecting unit, be used for receiving respectively the 8 circuit-switched data stream of data byte bit compound processing model output, have or not A1, A1, A1, A2, continuous six data of A2, A2 in the current data stream of detection STM-1 structure, come to determine to have or not in the current data position at frame head and frame head place in view of the above;
The pulse-triggered unit is used for producing a frame head index pulse in last A2 byte of frame head when detecting current data stream and have continuous A1, A1, A1, A2, six data of A2, A2;
Frame head marking signal reset unit is used for when the frame head sign reset signal of receiving from the hot plug detecting unit frame head marking signal being resetted.
The data frame head is selected and hot plug processing module 13, comprises:
The branch road selected cell is used to receive data flow and the frame head marking signal that each frame head certification mark branch road is exported, and selects to have the frame head marking signal and the corresponding branch road data flow thereof of frame head pulse;
The hot plug detecting unit is used for after the optical fiber hot plug, if detect a plurality of frame head marking signals that have the frame head pulse, sends frame head sign reset signal.
Based on said apparatus, 19M data flow to be detected enters data byte bit compound processing model and carries out reconfiguring of byte bit, obtain 8 circuit-switched data, enter frame head certification mark module and carry out frame head and detect and after detecting frame head, send the frame head index pulse, at last data and testing result are sent into that the data frame head is selected and the hot plug processing module carries out that the data frame head is selected and the hot plug processing.Below in conjunction with specific algorithm above-mentioned flow chart of data processing is elaborated.
Enter the 19M data flow of STM-1 frame head checkout gear, at first enter data byte bit compound processing model.In each byte data that conversion comes, the border of 8 Bit datas of fetching from 155M is uncertain.Because a byte has only 8 bits, thereby the border of 8 Bit datas of fetching from the 155M data flow that CDR recovers out also has only 8 kinds of possibilities.Therefore, data processing obtains 8 different data with per 8 bits of the data of receiving cyclic shift successively, wherein must have data identical with actual number.In view of the above, data byte bit compound processing model obtains the data flow DATA1......DATA8 of 8 road 19M, 8 bit widths by the bit cyclic shift to the front and back adjacent byte.Import 8 frame head certification mark modules respectively, carry out frame head and detect.
Suppose that adjacent two bytes bit architecture from low to high that enters STM-1 frame head checkout gear is:
b11、b12、b13、b14、b15、b16、b17、b18
b21、b22、b23、b24、b25、b26、b27、b28
Then the Dui Ying clock recovery circuitry 155M data flow recovering out is:
b11、b12、b13、b14、b15、b16、b17、b18、b21、b22、b23、b24、b25、b26、b27、b28、b31、......。
And original real byte may start from the optional position among this bit stream b11, b12, b13, b14, b15, b16, b17, the b18.Therefore the bit cyclic shift to adjacent byte can obtain following 8 kinds of possible data flow altogether:
b11、b12、b13、b14、b15、b16、b17、b18、b21、b22、......
b12、b13、b14、b15、b16、b17、b18、b21、b22、b23、......
b13、b14、b15、b16、b17、b18、b21、b22、b23、b24、......
b14、b15、b16、b17、b18、b21、b22、b23、b24、b25、......
b15、b16、b17、b18、b21、b22、b23、b24、b25、b26、......
b16、b17、b18、b21、b22、b23、b24、b25、b26、b27、......
b17、b18、b21、b22、b23、b24、b25、b26、b27、b28、......
b18、b21、b22、b23、b24、b25、b26、b27、b28、b31、......
Like this, any time is sent into the data flow of 19M 8 bit widths of STM-1 frame head checkout gear, the 8 tunnel different data flow of coming out after data byte bit compound processing model wherein must have one the tunnel to be correct data flow, and A1A1A1A2A2A2 also can only be present in wherein a certain road.
Frame head detecting unit in each branch road of frame head certification mark module checks that in the current data stream whether continuous 6 bytes being arranged is A1A1A1A2A2A2, if have, then the current location of current data stream is the frame head position of correct data flow, the pulse-triggered unit produces a frame head index pulse in the IFPi signal, point to last A2 byte of current data stream frame head; If no, then the frame head marking signal of IFPi output is low level all the time;
Then, come out data and frame head marking signal of each branch road sent into the data frame head and selected and the hot plug processing module, select correct frame head IFP and data RD[7:0] export.8 circuit-switched data stream after data byte bit compound processing model is handled, have only one the tunnel to be correct data flow, therefore, after frame head detects, has only one tunnel frame head marking signal that comes out correct, according to this point, have the data flow and the frame head output of the branch road of frame head pulse in the branch road selected cell selection frame head marking signal.
Suppose that from the data flow that 8 branch roads come out be RD1[7:0], IFP1, RD2[7:0], IFP2, RD3[7:0], IFP3, RD4[7:0], IFP4, RD5[7:0], IFP5, RD6[7:0], IFP6, RD7[7:0], IFP7, RD8[7:0], IFP8.Wherein branch road 2 is correct branch roads, and promptly the signal that comes out through this device is RD2[7:0], IFP2;
Yet, when hot plug, system reworks, variation may take place in the data sequence of newly receiving, active traffic may be exported from other branch road, and system is still selected by original frame head marking signal, at this moment, system can detect a plurality of frame head marking signals (current data frame is abandoned) that have the frame head pulse, thereby will send frame head sign reset signal by the hot plug detecting unit.After hot plug detecting unit in the frame head certification mark module receives frame head sign reset signal, frame head marking signal in each frame head detection branch is resetted, restart the work that frame head detects, just can recover normal operating conditions, thereby make system have the performance of hot plug operate as normal.
Go up example for another example, pull out plug again behind the optical fiber after, correct data flow may be any branch road, supposes at this moment to have more than one of the marking signal of pulse, that is:
IFP1+IFP2+IFP3+IFP4+IFP5+IFP6+IFP7+IFP8＞1
In view of the above, the hot plug detecting unit sends reset signal, and IFP1, IFP2, IFP3, IFP4, IFP5, IFP6, IFP7, IFP8 in each branch road frame head is detected reset, and detect frame head again.Normal operating conditions can be recovered by system.
As shown in Figure 3, wherein DATA_TI is the data flow (f6 is corresponding to A1, and 28 corresponding to A2) that enters the frame head checkout gear, and RD is the data flow of coming out from the frame head checkout gear, that select is the data flow and the IFP of second branch road (DATA1), and IFP is the frame head marking signal that detects.
As shown in Figure 4, the inventive method may further comprise the steps:
Step 100 is carried out cyclic shift to 8 bit width 19M data flow, produces 8 tunnel 8 bit width 19M data flow;
Step 150 is sent frame head sign reseting pulse signal, returns step 140 (abandoning current data frame);
Step 160 selects to have the frame head marking signal of frame head pulse and the data flow output of respective branch thereof.
In sum, the present invention after the STM-1 data that clock recovery circuitry is recovered are out carried out 8 frequency divisions, has automatic frame head measuring ability except that the frame head of supporting general STM-1 structured data stream detects, select branch road automatically, need not other configuration or control signal; Support the optical fiber hot plug.But clearly, apparatus and method of the present invention can realize that also the frame head that other byte bit combination is had the STM-1 data flow of randomness detects.
Claims (8)
1, the frame head checkout gear of STM-1 structure in a kind of SDH system is characterized in that, comprising: data byte bit compound processing model, frame head certification mark module, data frame head are selected module, wherein:
Described data byte bit compound processing model is used for reconfiguring of byte bit, and the datacycle displacement of 8 bit widths that enter this device is formed 8 circuit-switched data stream;
Described frame head certification mark module comprises 8 frame head certification mark branch roads, receives described 8 circuit-switched data stream respectively, produces corresponding frame head marking signal and data flow and exports together, and each frame head certification mark branch road comprises:
The frame head detecting unit is used for detecting current data and has or not frame head, and determines the frame head position;
The pulse-triggered unit is used for when detecting frame head, produces a frame head pulse in the frame head marking signal;
Described data frame head is selected module, comprising:
The branch road selected cell is used to receive the output of described 8 frame head certification mark branch roads, therefrom selects to have the frame head marking signal and the output of corresponding branch road data flow of frame head pulse.
2, frame head checkout gear as claimed in claim 1 is characterized in that, described data frame head selects module also to comprise:
The hot plug detecting unit is used for when a more than marking signal has the frame head pulse, sending frame head sign reset signal at the frame head marking signal that detects described 8 frame head certification mark branch roads output;
Simultaneously, described each frame head certification mark branch road also comprises:
Frame head marking signal reset unit is used for when receiving described frame head sign reset signal the frame head marking signal in the branch road being resetted.
3, frame head checkout gear as claimed in claim 1 or 2, it is characterized in that, described frame head detecting unit has or not six continuous byte datas of A1A1A1A2A2A2 to determine to have or not frame head in the current data by detecting in the current data stream, and described pulse-triggered unit produces a frame head index pulse in last A2 byte of detected frame head.
4, frame head checkout gear as claimed in claim 1 is characterized in that, the data flow of described 8 bit widths is the data flow of 19M.
5, the frame head detection method of STM-1 structure in a kind of SDH system may further comprise the steps:
(a) 8 bit width data flow are carried out cyclic shift, produce 8 tunnel 8 bit width data flow;
(b) 8 circuit-switched data flow points do not enter 8 branch roads and carry out frame head and detect, if in the current data stream frame head identification byte is arranged, then send the frame head pulse in the frame head marking signal;
(c) the frame head marking signal and the data flow of each branch road are exported;
(d) select to have the frame head marking signal of frame head pulse and data flow output accordingly thereof.
6, frame head detection method as claimed in claim 5 is characterized in that, in described step (b) with (c), also comprises:
Step (b1): check to have or not frame head sign reset signal have then present frame leader will signal reset, otherwise directly carry out (c) to each branch road;
Simultaneously, between described step (c) and step (d), also comprise:
Whether step (c1): detecting to have in the frame head marking signal of each branch road has the frame head pulse on the more than one marking signal, if, then send frame head sign reset signal, and continue to detect, otherwise execution in step (d).
7, as claim 5 or 6 described frame head detection methods, it is characterized in that, in described step (b), if in the current data stream continuous A1A1A1A2A2A2 byte is arranged, then the frame head marking signal corresponding to this successive byte in the position of last A2 byte send the frame head pulse.
As claim 5 or 6 described frame head detection methods, it is characterized in that 8, the data flow of 8 bit widths in the described step (a) is the STM-119M data flow after CDR clock recovery circuitry, frequency division and rate transition.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101141236B (en) * | 2007-03-20 | 2010-08-04 | 中兴通讯股份有限公司 | In-frame method for synchronous transmission system |
| CN102404067A (en) * | 2011-11-28 | 2012-04-04 | 曙光信息产业(北京)有限公司 | System for detecting STM-64 (Synchronous Transfer Mode-64) frame head of SDH (Synchronous Digital Hierarchy) network |
| CN101145863B (en) * | 2007-03-21 | 2012-07-18 | 中兴通讯股份有限公司 | Device and method for detecting system frame header deviation |
| CN104751088A (en) * | 2015-03-13 | 2015-07-01 | 昆腾微电子股份有限公司 | Frame header detection device and method |
| CN101702642B (en) * | 2009-11-13 | 2015-08-12 | 曙光信息产业(北京)有限公司 | The detection method of SDH frame head |
| CN106100878A (en) * | 2016-06-08 | 2016-11-09 | 深圳市梧桐世界科技股份有限公司 | A kind of method realizing intel x86 router analog reset button |
| WO2016184291A1 (en) * | 2015-05-21 | 2016-11-24 | 中兴通讯股份有限公司 | Frame header detection method and device |
| CN108650047A (en) * | 2017-12-29 | 2018-10-12 | 北京时代民芯科技有限公司 | A kind of Serial data receiving real-time synchronization observation circuit and monitoring method |
| CN112230879A (en) * | 2020-10-23 | 2021-01-15 | 成都航天通信设备有限责任公司 | Byte and bit data processing and sending method based on FPGA |
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- 2003-12-30 CN CN 200310116071 patent/CN1290289C/en not_active Expired - Lifetime
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101141236B (en) * | 2007-03-20 | 2010-08-04 | 中兴通讯股份有限公司 | In-frame method for synchronous transmission system |
| CN101145863B (en) * | 2007-03-21 | 2012-07-18 | 中兴通讯股份有限公司 | Device and method for detecting system frame header deviation |
| CN101702642B (en) * | 2009-11-13 | 2015-08-12 | 曙光信息产业(北京)有限公司 | The detection method of SDH frame head |
| CN102404067A (en) * | 2011-11-28 | 2012-04-04 | 曙光信息产业(北京)有限公司 | System for detecting STM-64 (Synchronous Transfer Mode-64) frame head of SDH (Synchronous Digital Hierarchy) network |
| CN104751088A (en) * | 2015-03-13 | 2015-07-01 | 昆腾微电子股份有限公司 | Frame header detection device and method |
| WO2016184291A1 (en) * | 2015-05-21 | 2016-11-24 | 中兴通讯股份有限公司 | Frame header detection method and device |
| CN106100878A (en) * | 2016-06-08 | 2016-11-09 | 深圳市梧桐世界科技股份有限公司 | A kind of method realizing intel x86 router analog reset button |
| CN106100878B (en) * | 2016-06-08 | 2019-06-28 | 深圳市梧桐世界科技股份有限公司 | A method of realizing intel x86 router analog reset key |
| CN108650047A (en) * | 2017-12-29 | 2018-10-12 | 北京时代民芯科技有限公司 | A kind of Serial data receiving real-time synchronization observation circuit and monitoring method |
| CN108650047B (en) * | 2017-12-29 | 2020-02-21 | 北京时代民芯科技有限公司 | Serial data receiving real-time synchronous monitoring circuit and monitoring method |
| CN112230879A (en) * | 2020-10-23 | 2021-01-15 | 成都航天通信设备有限责任公司 | Byte and bit data processing and sending method based on FPGA |
| CN112230879B (en) * | 2020-10-23 | 2022-05-17 | 成都航天通信设备有限责任公司 | Byte and bit data processing and sending method based on FPGA |
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Application publication date: 20041222 Assignee: Xi'an Chris Semiconductor Technology Co.,Ltd. Assignor: SANECHIPS TECHNOLOGY Co.,Ltd. Contract record no.: 2019440020036 Denomination of invention: Frame Header Detection Device and Method Based on STM-1 Structure in SDH System Granted publication date: 20061213 License type: Common License Record date: 20190619 |
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