CN1556476A - Method of realizing conversion between PCI bus and CPU bus - Google Patents
Method of realizing conversion between PCI bus and CPU bus Download PDFInfo
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- CN1556476A CN1556476A CNA2003101103825A CN200310110382A CN1556476A CN 1556476 A CN1556476 A CN 1556476A CN A2003101103825 A CNA2003101103825 A CN A2003101103825A CN 200310110382 A CN200310110382 A CN 200310110382A CN 1556476 A CN1556476 A CN 1556476A
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Abstract
The invention relates to a method of implementing conversion between buses, concretely a method of using PCI configuration commands to implement the access a PCI bus to a CPU bus. It configures the register number of the address period in accessing as read/write address information of a CPU bus to respond to that the PCI configures read and write operations and initializing device selecting signals, according to the bus command code of the address period, generates a read/write signal, using a device number to generate a chip strobe signal so as to 'translate' the PCI bus information into the CPU bus. Compared with existing techniques, it is simple to implement and needs extremely a few resources, need not take a subcard as a complete PCI device for processing and allocate an address space to the subcard, reduces working burden for the system because the subcard does not respond any PCI operation but the configuration commands, and at the same time, has a few requests for programmable devices, and cab be implemented by a smaller CPLD.
Description
Technical field
The present invention relates to a kind of method of changing between the bus of realizing, be specifically related to the conversion between the pci bus and cpu bus in communication or the computer system, specifically is a kind of PCI of utilization configuration order, realizes the method for pci bus visit cpu bus.
Background technology
In many computer systems or communication system, has only pci bus interface between subcard or interface board and the CPU, but there is chip need carry out read-write operation on subcard or the interface board again based on the cpu bus visit, by in the past way is to utilize bus converter of programming device structure, to be mapped to the memory space or the IO space of pci bus based on the address space of cpu bus access chip, read as the memory of initiator (PCI operation initiator) by PCI by CPU then or the memory write operation conducts interviews.This bus converter need be handled as a complete PCI equipment, and it must realize following function:
The realization of device identification number: must virtual DeviceID (device number), VendorID (manufacturer's identifier), RevisionID fields such as (version numbers) is as device identification number, which type of available devices driver just can determine to exist on the pci bus like this.
Realize that a read-write base address register is used to distribute address space, want the response that can realize that configuration is read and write to PCI simultaneously.
Because the complete PCI slave unit that has been virtual, according to different drive softwares, also should be in configuration space realization state and command field so that system software is determined the status information of current available PCI equipment.
Want to read or the memory write operation carries out correct address decoding to the memory of pci bus, and the response of making.
Want and the register mappings based on the cpu bus visit can be arrived the PCI address space.
CPU needs following operation for antithetical phrase sticks into row access:
During the pci bus initialization bus converter on the subcard is configured, distributes address space.
CPU reads as the memory of initiator by PCI or the memory write operation conducts interviews.
In sum, not only complicated but also need very big resource space based on the design proposal of this conventional thought.
Summary of the invention
The object of the present invention is to provide a kind of method of changing between the bus of realizing, particularly a kind of PCI configuration order of utilizing realizes the method for pci bus visit cpu bus.To overcome the too complicated shortcoming of implementation method in the prior art, solve the existing too many technical matters of implementation consumption of natural resource.
The present invention is achieved in that
A kind of method of changing between pci bus and the cpu bus of realizing comprises the steps: at least
Initialization step is used for the read-write operation address information of the register number of configuration access address phase as cpu bus;
The choice of equipment step is used for PCI configuration is read to respond with configurable write, and initialization apparatus selection signal is responded;
Data transmission step is according to the bus line command decoding generation read-write of address phase;
The data latching step utilizes device number to produce chip selection signal.
In the described initialization step:
Only realize manufacturer's identifier of a register by bus conversion module, and it is made as complete 1, be expressed as FFFF with 16 systems, according to the PCI standard, if manufacturer's identifier is FFFF, then drive software will think that this device number place does not have PCI equipment when scanning PCI equipment, and all operations to PCI equipment all will skip over.
In the described choice of equipment step:
If certain register of chip on the subcard is conducted interviews, directly send the order that a PCI configuration reads or writes by driver, drive pci bus.
In the described data transmission step:
Initiator by the PCI operation initiatively initiates the PCI operation, in the address phase, utilize register number and keep the address information of position as cpu bus, utilize of the indication of the command field of pci bus as the cpu bus read-write operation, in the data phase, utilize high 16 data of transmitting cpu bus of data bus.
In the described data transmission step:
The Bus number of address phase bus, function number, configuration access type all must be carried out fully decoded in the address phase of PCI operation.
In the described data transmission step:
In the data phase of pci bus, the data transmission response signal of utilizing the cpu bus access slave is as the excitation that produces slave unit response signal in the pci bus operation, promptly have only after the data transmission response signal is effective, just produce the response signal of slave unit in the pci bus operation, otherwise pci bus is in waiting status, is used for guaranteeing maloperation can not occur.
In the described data latching step:
Be to utilize the operation response signal of the delay of slave unit response signal in the pci bus operation, to satisfy the sequential requirement of cpu bus operation at a slow speed as cpu bus.
The delay of slave unit response signal is the retry mechanism that utilizes in the PCI standard in the described pci bus operation, promptly send stop signal by slave unit, do not have surpassing certain limiting time in the operation of data response pci bus after the slave unit response signal, slave unit sends stop signal, main equipment is cancelled the pci bus operation, again identical operations is carried out in same address after bus arbitration arrival next time.
A kind of method of changing between pci bus and the cpu bus of realizing comprises the steps:
First step, only realize manufacturer's identifier of a register by bus conversion module, and it is made as complete 1, be expressed as FFFF with 16 systems, according to the PCI standard, if manufacturer's identifier is FFFF, then drive software will think that this device number place does not have PCI equipment when scanning PCI equipment, and all operations to PCI equipment all will skip over.
Second step is divided into two parts with the definition of pci bus in the data phase, low 16 only be in the address 00 o'clock meaningful, and value is ffff, high 16 data that conduct is latched into from cpu bus, or will write the data value of cpu bus, avoid bus to produce conflict;
Third step, the choice of equipment signal of bus conversion module is connected on the AD line of a certain pci bus that can be used as choice of equipment, in the address phase, in case deciphering bus line command, bus converter reads or writes for configuration, will judge to send the device responds signal according to the choice of equipment signal;
The 4th step if certain register of chip on the subcard is conducted interviews, is directly sent the order that a PCI configuration reads or writes by driver, drives pci bus;
The 5th step, visit based on cpu bus is asynchronous operation, read still is that write operation must wait for that all the data transmission response signal of chip effectively could begin the data phase of PCI, utilize of the excitation of data transmission response signal as slave unit response signal in the pci bus operation, it is effective that the response signal of slave unit is kept a pci clock cycle in the pci bus operation, cancels afterwards;
The 6th step, the device responds signal is effective in the next clock period of address phase and then, illustrates that slave unit responds, and pci bus is in waiting status;
The 7th step, utilize the retry mechanism in the PCI standard, promptly send stop signal by slave unit, do not have surpassing certain limiting time in the operation of data response pci bus after the slave unit response signal, slave unit sends stop signal, main equipment is cancelled the pci bus operation, again identical operations is carried out in same address after bus arbitration arrival next time.
The configuration order that the present invention proposes a kind of PCI of utilization realizes the method for pci bus visit cpu bus, realizes that compared with prior art simply resource requirement is few, has significantly reduced the complexity of system.Do not need subcard is handled as a complete PCI equipment, do not need to distribute address space for subcard, except configuration order, subcard does not respond any PCI operation, reduced the work load of system, to the requirement of programming device also seldom, utilize the less CPLD of a slice to realize simultaneously.
Description of drawings
What Fig. 1 provided is the sequential chart that carries out the cpu bus operation in the motorola mode;
What Fig. 2 provided is the format chart of PCI configuration access in the address phase;
What Fig. 3 provided is bus conversion module and the outside synoptic diagram that is connected;
What Fig. 4 provided is the state exchange process flow diagram of the method for the invention.
Embodiment
Basic thought of the present invention is: the information " translation " of pci bus is arrived cpu bus, and concrete thinking is as follows:
Manufacturer's identifier (VendorID) of this PCI equipment number being made as complete 1, is FFFF when representing with 16 systems, by pci bus standard agreement, will skip over this PCI equipment at the pci bus initial phase.
Except that PCI configuration read with the configurable write operation, other all PCI operations responds, do not need to set base address register, IDSEL (initialization apparatus selection signal) is responded.
Initiator initiatively initiates the PCI operation, in the address phase, utilizes register number and keeps the address information of position as cpu bus, utilizes the indication of the command field of pci bus as the cpu bus read-write operation.Utilize high 16 data of transmitting cpu bus of data bus in the data phase.
Utilize the operation response signal of the delay of TRDY (response signal of slave unit in the pci bus operation), to satisfy the sequential requirement of cpu bus operation at a slow speed as cpu bus.
The invention provides a kind of PCI of utilization configuration order and finish the method for pci bus visit cpu bus:
1, the register number of address phase if address width surpasses 6, then can be utilized the highest several the address bits as a high position that keep the position as the read-write operation address information of cpu bus in the configuration access;
2, the pci bus command decoder according to the address phase produces read-write;
3, utilize device number to produce chip selection signal:
In the data phase of pci bus, the DTA (data transmission response signal) that utilizes the cpu bus access slave is as the excitation that produces PCI slave unit trdy signal, promptly have only after DTA is effective just to produce trdy, otherwise pci bus is in waiting status, can guarantee so maloperation can not occur.
The configuration operation of pci bus is a kind of relatively special P CI operation, in the address phase, bus line command (CBE#[3:0]) is " 1010 (reading) " or " 1011 (writing) ", the meaning that 32 bit data on this moment bus are comprised as shown in Figure 2, the type of minimum two bit representation configuration operations; The register number of the 2nd to the 7th bit representation configuration operation, we are with the address information of this register number as cpu bus.
Below in conjunction with accompanying drawing the present invention is described in further detail:
Fig. 1 shows the sequential chart of motorola mode cpu bus operation.Cpu bus will be finished read-write operation, must DS (data strobe, the data selection), CS# (chip select, the sheet choosing, # represents that low level is effective), the DTA# (dataacknowledgment, data response signal) on R/W (read-write) and the data line, the ADDRESS signals such as (address signal, A0-A6 totally 7 address wires) on the address wire simultaneously effectively, simultaneously, also will export a response signal DTA (data transmission response) as the slave unit of a cpu bus visit.Data bus is divided into two kinds of forms of read and write, the data bus when wherein " D0-D7 READ " represents read operation; Data bus during " D0-D7WRITE " expression write operation.VALID DATA represents the term of validity of data.
Among Fig. 2: the type of minimum two bit representation configuration operations; The register number of the 2nd to the 7th bit representation configuration operation, we keep the position and can be used as high-order address information with the address information of this register number as cpu bus.
Among Fig. 3: be connected by pci bus between cpu bus browse master and the bus conversion module, be connected by cpu bus between cpu bus access slave and the bus conversion module.Wherein, AD[31:0] be the data and the address bus of pci bus; C/BE[3:0] # is pci bus order/byte useful signal (# represents that low level is effective); FRAME# is the frame period signal; IRDY# is that main equipment is ready to signal; IDSEL is that initialization apparatus is selected signal; TRDY is the response signal of slave unit in the PCI operation, and the data of expression slave unit are ready to; DELSEL is the response signal of slave unit in the PCI operation, and the expression slave unit responds; PLD is a programmable logic device (PLD).
Among Fig. 4: whole flow process is by the beginning that resets, all state machines are in init state (401), bus conversion module enters choice of equipment state (402) after deciphering, and then the bus conversion enters data transmission state (403), in case the DTA signal of slave unit is (404) effectively, just enter data latching state (405), put TRDY simultaneously for effective, a pci bus EO reenters init state (401).
The specific descriptions that realize technical scheme are as follows:
1, bus conversion module is only realized a register VendorID, and VendorID is made as FFFF, according to the PCI standard, if VendorID is FFFF, then drive software will think that this device number place does not have PCI equipment when scanning PCI equipment, and all operations to PCI equipment all will skip over.
2, because the register address of VendorID is 00, produce conflict on the bus in order not make, pci bus is divided into two parts in the definition of data phase, low 16 only be in the address 00 o'clock meaningful, and value is ffff, high 16 data that conduct is latched into from cpu bus, or will write the data value of cpu bus.
3, the IDSEL of bus conversion module is connected on a certain pci bus AD line that can be used as choice of equipment,, reads or writes for configuration, will judge to send the device responds signal according to IDSEL in case bus converter is deciphered bus line command in the address phase.
4 if conduct interviews to certain register of chip on the subcard, directly sends the order that a PCI configuration reads or writes by driver, drives pci bus.Operating system has different function calls, and the order of PCI configuration read-write is under VxWorks:
Configuration is read:
PciConfigInLong(BusNumber，DeviceNumber，Function，RegAddr，Paddr)；
Configurable write:
PciConfigOutLong(BusNumber，DeviceNumber，Function，RegAddr，Data)；
Wherein BusNumber is used to refer to Bus number; DeviceNumber is used to refer to device number, if IDSEL and PADn connect together on the subcard, then DeviceNumber just should be made as n; Function deixis number; Paddr is a storage addresses after data are read; The data of Data for writing; Low two of RegAddr are made as 00 or 01 by 0 class configuration access or 1 class configuration access, and high 6 of RegAddr is used to refer to the register address that will visit.Bus number, function number, configuration access type all must be carried out fully decoded in the address phase of PCI operation, so just can expand technical scheme of the present invention by the PCI bridge.
5, the visit based on cpu bus generally all is asynchronous operation, read still is that write operation must wait for that all the DTA response signal of chip effectively could begin the data phase of PCI, therefore utilize of the excitation of DTA signal in the present invention as TRDY, it is effective that TRDY keeps a pci clock cycle, cancels afterwards.
As the device responds signal, DEVSEL (choice of equipment signal) is effective in the next clock period of address phase and then, illustrate that slave unit responds, but because this moment, TRDY was in disarmed state, so pci bus is in a kind of waiting status, by the pci bus standard, this waiting status can be long arbitrarily, but the response time as fruit chip is long especially, will respond the efficient of pci bus, in this case, can utilize the retry mechanism in the PCI standard, promptly send the STOP signal by slave unit, do not have surpassing certain limiting time after the data response TRDY, slave unit sends the STOP signal, and main equipment is cancelled the pci bus operation, again identical operations is carried out in same address after bus arbitration arrival next time.
Claims (9)
1, a kind of method of changing between pci bus and the cpu bus of realizing comprises the steps: at least
Initialization step is used for the read-write operation address information of the register number of configuration access address phase as cpu bus;
The choice of equipment step is used for PCI configuration is read to respond with configurable write, and initialization apparatus selection signal is responded;
Data transmission step is according to the bus line command decoding generation read-write of address phase;
The data latching step utilizes device number to produce chip selection signal.
2, realize the method changed between pci bus and the cpu bus according to claim 1, it is characterized in that in the described initialization step:
Only realize manufacturer's identifier of a register by bus conversion module, and it is made as complete 1.
3, realize the method changed between pci bus and the cpu bus according to claim 1, it is characterized in that in the described choice of equipment step:
If certain register of chip on the subcard is conducted interviews, directly send the order that a PCI configuration reads or writes by driver, drive pci bus.
4, realize the method changed between pci bus and the cpu bus according to claim 1, it is characterized in that in the described data transmission step:
Initiator by the PCI operation initiatively initiates the PCI operation, in the address phase, utilize register number and keep the address information of position as cpu bus, utilize of the indication of the command field of pci bus as the cpu bus read-write operation, in the data phase, utilize high 16 data of transmitting cpu bus of data bus.
5, realize the method changed between pci bus and the cpu bus according to claim 1, it is characterized in that in the described data transmission step:
The Bus number of address phase bus, function number, configuration access type all must be carried out fully decoded in the address phase of PCI operation.
6, the method as changing between realization pci bus as described in claim 4 or 5 and the cpu bus is characterized in that in the described data transmission step:
In the data phase of pci bus, the data transmission response signal of utilizing the cpu bus access slave is as the excitation that produces slave unit response signal in the pci bus operation, promptly have only after the data transmission response signal is effective, just produce the response signal of slave unit in the pci bus operation, otherwise pci bus is in waiting status, is used for guaranteeing maloperation can not occur.
7, realize the method changed between pci bus and the cpu bus according to claim 1, it is characterized in that in the described data latching step:
Be to utilize the operation response signal of the delay of slave unit response signal in the pci bus operation, to satisfy the sequential requirement of cpu bus operation at a slow speed as cpu bus.
8, the method as changing between realization pci bus as described in the claim 7 and the cpu bus is characterized in that:
The delay of slave unit response signal is the retry mechanism that utilizes in the PCI standard in the described pci bus operation, promptly send stop signal by slave unit, do not have surpassing certain limiting time in the operation of data response pci bus after the slave unit response signal, slave unit sends stop signal, main equipment is cancelled the pci bus operation, again identical operations is carried out in same address after bus arbitration arrival next time.
9, a kind of method of changing between pci bus and the cpu bus of realizing comprises the steps:
First step is only realized manufacturer's identifier of a register by bus conversion module, and it is made as complete 1.
Second step is divided into two parts with the definition of pci bus in the data phase, low 16 only be in the address 00 o'clock meaningful, and value is ffff, high 16 data that conduct is latched into from cpu bus, or will write the data value of cpu bus, avoid bus to produce conflict;
Third step, the choice of equipment signal of bus conversion module is connected on the AD line of a certain pci bus that can be used as choice of equipment, in the address phase, in case deciphering bus line command, bus converter reads or writes for configuration, will judge to send the device responds signal according to the choice of equipment signal;
The 4th step if certain register of chip on the subcard is conducted interviews, is directly sent the order that a PCI configuration reads or writes by driver, drives pci bus;
The 5th step, visit based on cpu bus is asynchronous operation, read still is that write operation must wait for that all the data transmission response signal of chip effectively could begin the data phase of PCI, utilize of the excitation of data transmission response signal as slave unit response signal in the pci bus operation, it is effective that the response signal of slave unit is kept a pci clock cycle in the pci bus operation, cancels afterwards;
The 6th step, the device responds signal is effective in the next clock period of address phase and then, illustrates that slave unit responds, and pci bus is in waiting status;
The 7th step, utilize the retry mechanism in the PCI standard, promptly send stop signal by slave unit, do not have surpassing certain limiting time in the operation of data response pci bus after the slave unit response signal, slave unit sends stop signal, main equipment is cancelled the pci bus operation, again identical operations is carried out in same address after bus arbitration arrival next time.
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| CNB2003101103825A CN100401278C (en) | 2003-12-30 | 2003-12-30 | Method of realizing conversion between PCI bus and CPU bus |
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| CNB2003101103825A CN100401278C (en) | 2003-12-30 | 2003-12-30 | Method of realizing conversion between PCI bus and CPU bus |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202690B (en) * | 2006-12-11 | 2010-05-12 | 上海华虹Nec电子有限公司 | System structure of multi-IP modules and method for reading data of multi-IP modules |
| CN103092798B (en) * | 2012-12-28 | 2016-05-25 | 华为技术有限公司 | The method of the access means under SOC(system on a chip) and bus |
| CN112416824A (en) * | 2020-12-03 | 2021-02-26 | 上海集成电路研发中心有限公司 | Efuse read-write controller, chip, electronic equipment and control method |
| CN113868179A (en) * | 2021-09-10 | 2021-12-31 | 中国航空工业集团公司西安航空计算技术研究所 | LPC _ DPRam communication device and data conversion method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19580707C2 (en) * | 1994-06-28 | 2003-10-30 | Intel Corp | PCI-to-ISA interrupt protocol converter and selection mechanism |
| CN1223944C (en) * | 2001-07-12 | 2005-10-19 | 威盛电子股份有限公司 | PCI data reading system and reading method using reading demand conduit |
| JP2003316725A (en) * | 2002-04-19 | 2003-11-07 | Youxun Sci & Technol Co Ltd | Circuit for using element accepted by pc card bus standard for electronic device employing pci bus standard, and its method |
| CN1234079C (en) * | 2002-10-31 | 2005-12-28 | 浙江大学 | High-speed information safety processor |
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2003
- 2003-12-30 CN CNB2003101103825A patent/CN100401278C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202690B (en) * | 2006-12-11 | 2010-05-12 | 上海华虹Nec电子有限公司 | System structure of multi-IP modules and method for reading data of multi-IP modules |
| CN103092798B (en) * | 2012-12-28 | 2016-05-25 | 华为技术有限公司 | The method of the access means under SOC(system on a chip) and bus |
| US9489328B2 (en) | 2012-12-28 | 2016-11-08 | Huawei Technologies Co., Ltd. | System on chip and method for accessing device on bus |
| CN112416824A (en) * | 2020-12-03 | 2021-02-26 | 上海集成电路研发中心有限公司 | Efuse read-write controller, chip, electronic equipment and control method |
| CN112416824B (en) * | 2020-12-03 | 2024-02-09 | 上海集成电路研发中心有限公司 | efuse read-write controller, chip, electronic equipment and control method |
| CN113868179A (en) * | 2021-09-10 | 2021-12-31 | 中国航空工业集团公司西安航空计算技术研究所 | LPC _ DPRam communication device and data conversion method |
| CN113868179B (en) * | 2021-09-10 | 2024-04-02 | 中国航空工业集团公司西安航空计算技术研究所 | Communication device of LPC-DPRam and data conversion method |
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