CN1553576A - Differential comparison circuit system - Google Patents

Differential comparison circuit system Download PDF

Info

Publication number
CN1553576A
CN1553576A CNA031424279A CN03142427A CN1553576A CN 1553576 A CN1553576 A CN 1553576A CN A031424279 A CNA031424279 A CN A031424279A CN 03142427 A CN03142427 A CN 03142427A CN 1553576 A CN1553576 A CN 1553576A
Authority
CN
China
Prior art keywords
voltage
differential
circuit
receiving circuit
voltage range
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA031424279A
Other languages
Chinese (zh)
Other versions
CN1257611C (en
Inventor
印瑞德
王锡源
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Winbond Electronics Corp
Original Assignee
Winbond Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Winbond Electronics Corp filed Critical Winbond Electronics Corp
Priority to CN 03142427 priority Critical patent/CN1257611C/en
Publication of CN1553576A publication Critical patent/CN1553576A/en
Application granted granted Critical
Publication of CN1257611C publication Critical patent/CN1257611C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

The invention is a differential comparison circuit system, which is used to receive all input signals of a voltage range, and output an output voltage after amplifying, wherein the voltage range is divided into a first part with higher voltage and a second part with lower voltage, the system comprises: a first differential comparator for receiving a first portion of the input signal in the voltage range and amplifying the received voltage to generate the output voltage; a detection circuit, electrically connected to the first differential comparison circuit, for generating a trigger signal when detecting that the first differential comparison circuit cannot operate because the voltage of the input signal is lower than the first part of the voltage range; and a second differential comparator connected to the detection circuit, receiving the input signal of the second part in the voltage range corresponding to the driving of the trigger signal, and amplifying the received voltage to generate the output voltage.

Description

差动比较电路系统Differential comparison circuit system

(1)技术领域(1) Technical field

本发明是为一种比较电路系统，尤指一种适用于通用串行总线(UniversalSerial Bus，USB)界面传输端的差动比较电路系统。The present invention relates to a comparison circuit system, in particular to a differential comparison circuit system suitable for a universal serial bus (Universal Serial Bus, USB) interface transmission terminal.

(2)背景技术(2) Background technology

通用串行总线(Universal Serial Bus，USB)是一种周边设备界面，它是由七家软硬件制造商所共同制定的，这种界面的传输速率有1.5Mbps与12Mbps两种形式，最多可以连接到127部周边设备。Universal Serial Bus (USB) is a peripheral device interface, which is jointly developed by seven hardware and software manufacturers. The transmission rate of this interface has two forms: 1.5Mbps and 12Mbps. To 127 peripheral devices.

由于通用串行总线界面(USB)对于能够接收输入信号的电压值Vin范围规定得非常严格，必须满足于特定范围(0.8～2.2V)间的所有输入电压都能够接收。Since the universal serial bus interface (USB) has very strict regulations on the range of the voltage value Vin that can receive input signals, it must be satisfied that all input voltages within a specific range (0.8-2.2V) can be received.

请参阅图1(a)及(b)，其是传统用来接收输入信号的电路，其中图1(a)是使用N型金属氧化半导体晶体管(NMOS)来接收输入电压值，其只能接收较高电压范围的传输信号。图1(b)是使用P型金属氧化半导体晶体管(PMOS)来接收输入信号，其特性与N型金属氧化半导体晶体管(NMOS)完全相反，只能接收较低输入电压范围的信号。由于图1(a)及(b)能接收的输入电压Vin局限于较高或是较低的电压，且能接收的电压范围亦较小。Please refer to Figure 1(a) and (b), which are traditional circuits used to receive input signals, where Figure 1(a) uses N-type metal oxide semiconductor transistors (NMOS) to receive input voltage values, which can only receive Transmission signals in the higher voltage range. Figure 1(b) uses a P-type metal-oxide-semiconductor transistor (PMOS) to receive input signals. Its characteristics are completely opposite to those of an N-type metal-oxide-semiconductor transistor (NMOS), and it can only receive signals in a lower input voltage range. Since the acceptable input voltage Vin in Fig. 1 (a) and (b) is limited to higher or lower voltage, and the acceptable voltage range is also smaller.

但是，现今对于通用串行总线界面(USB)所能接收输入信号的电压范围要求越来越大，传统的电路已经不符需求，因此业者都想尽办法将P型金属氧化半导体晶体管(PMOS)与N型金属氧化半导体晶体管(NMOS)结合在一起，用以扩大通用串行总线界面(USB)所能接收输入信号的电压范围。However, nowadays, the voltage range that the universal serial bus interface (USB) can receive input signals is increasingly required, and the traditional circuit no longer meets the requirements. N-type metal-oxide-semiconductor transistors (NMOS) are combined to extend the voltage range that the universal serial bus interface (USB) can receive input signals.

请参阅图2，其是结合P型金属氧化半导体晶体管(PMOS)与N型金属氧化半导体晶体管(NMOS)，来扩大所能接收的电压范围的接收电路。当输入电压属于较低电压时，由P型金属氧化半导体晶体管M5及M6接收该输入电压，并传送至1∶1的尾端电流晶体管(tail-current transistor)20，用以产生并输出一尾端电流值(tail current)。至于，当输入电压属于较高电压时，改由N型金属氧化半导体晶体管M1及M2接收该输入电压，并藉由同样的1∶1的尾端电流晶体管(tail-current transi stor)21产生并输出所需的尾端电流值(tailcurrent)。Please refer to FIG. 2 , which is a receiving circuit that combines a P-type metal oxide semiconductor transistor (PMOS) and an N-type metal oxide semiconductor transistor (NMOS) to expand the voltage range that can be received. When the input voltage is a relatively low voltage, the input voltage is received by PMOS transistors M5 and M6 and sent to a 1:1 tail-current transistor (tail-current transistor) 20 for generating and outputting a tail-current transistor. Terminal current value (tail current). As for, when the input voltage belongs to a higher voltage, the input voltage is received by the N-type metal oxide semiconductor transistors M1 and M2, and is generated by the same 1:1 tail-current transistor (tail-current transistor) 21 and Output the desired tail current value (tailcurrent).

虽然图2的电路能够达到扩大接收的输入电压范围，但是，该尾端电流晶体管(tail-current transistor)20，21两者永远导通，不会随着所对应的PMOS或是NMOS的开关状态而动态改变，因此不管PMOS或是NMOS在接收传输信号时，都会有某个尾端电流晶体管(tail-current transistor)处于导通状态，但却没有运作，进而增加电源的损耗。Although the circuit in FIG. 2 can expand the received input voltage range, the tail-current transistors (tail-current transistor) 20 and 21 are always turned on, and will not follow the corresponding PMOS or NMOS switching state. However, it changes dynamically, so no matter whether PMOS or NMOS is receiving the transmission signal, there will be a tail-current transistor that is in the conduction state, but it does not operate, thereby increasing the loss of the power supply.

况且，当输入电压属于中间电压时，PMOS和NMOS会同时导通，而造成输出的尾端电流过大，进而浪费电源。Moreover, when the input voltage is at an intermediate voltage, the PMOS and NMOS will be turned on at the same time, resulting in excessive current at the output tail, thereby wasting power.

(3)发明内容(3) Contents of the invention

本发明的主要目的是为提供一种差动比较电路系统，藉由该检测电路的控制使该差动电路比较系统中只有一个差动比较器负责接收信号，另一差动比较器则完全关闭，可获得所需的输出电压，又不会有浪费电源的情形产生。The main purpose of the present invention is to provide a differential comparator circuit system, through the control of the detection circuit, only one differential comparator in the differential circuit comparator system is responsible for receiving signals, and the other differential comparator is completely closed , the desired output voltage can be obtained without wasting power.

根据本发明一方面的差动比较电路系统，用以接收一电压范围的所有输入信号，并加以放大后输出一输出电压，其中该电压范围是分为较高电压的第一部份及较低电压的第二部份，该系统是包含：一第一差动比较器，用以接收该电压范围中第一部份的输入信号，并将所接收的电压加以放大，用以产生该输出电压；一检测电路，电连接于该第一差动比较器，当检测到该第一差动比较电路因输入信号的电压低于该电压范围的第一部份而无法运作时，产生一触发信号；以及一第二差动比较器，电连接于该检测电路，相应该触发信号的驱动，而接收该电压范围中第二部份的输入信号，并将所接收的电压加以放大，用以产生该输出电压。A differential comparator circuit system according to an aspect of the present invention is used to receive all input signals in a voltage range, amplify them and output an output voltage, wherein the voltage range is divided into a first part of a higher voltage and a lower part. The second part of the voltage, the system includes: a first differential comparator, used to receive the input signal of the first part in the voltage range, and amplify the received voltage to generate the output voltage ; A detection circuit, electrically connected to the first differential comparator, when it is detected that the first differential comparator cannot operate because the voltage of the input signal is lower than the first part of the voltage range, a trigger signal is generated ; and a second differential comparator, electrically connected to the detection circuit, corresponding to the driving of the trigger signal, and receiving the input signal of the second part in the voltage range, and amplifying the received voltage to generate the output voltage.

根据上述构想，系统中该差动比较电路系统可适用于一通用串行总线(USB)界面的传输端。According to the above idea, the differential comparison circuit system in the system can be applied to the transmission end of a Universal Serial Bus (USB) interface.

根据上述构想，系统中该第一差动比较器包含：一第一差动接收电路，用以接收该电压范围中第一部份的输入信号；以及一第一运算放大电路，电连接于该第一差动接收电路，用以将该第一差动接收电路所接收的电压加以放大，使产生该输出电压。According to the above idea, the first differential comparator in the system includes: a first differential receiving circuit for receiving the input signal of the first part in the voltage range; and a first operational amplifier circuit electrically connected to the The first differential receiving circuit is used for amplifying the voltage received by the first differential receiving circuit to generate the output voltage.

根据上述构想，系统中该第二差动比较器包含：一第二差动接收电路，电连接于该检测电路，相应该触发信号的驱动，而接收接收该电压范围中第二部份的输入信号；以及一第二运算放大电路，电连接于该第二差动接收电路，用以将该第二差动接收电路所接收的电压加以放大，使产生该输出电压。According to the above idea, the second differential comparator in the system includes: a second differential receiving circuit, electrically connected to the detection circuit, corresponding to the driving of the trigger signal, and receiving the input of the second part in the voltage range signal; and a second operational amplifier circuit electrically connected to the second differential receiving circuit for amplifying the voltage received by the second differential receiving circuit to generate the output voltage.

根据上述构想，系统中该差动比较电路系统可包含一输出电路，用以输出该输出电压。According to the above idea, the differential comparison circuit system in the system may include an output circuit for outputting the output voltage.

根据上述构想，系统中该第二差动比较器于该第一差动比较器运作时可处于关闭状态，用以避免产生漂浮(floating)和加乘效果。According to the above idea, the second differential comparator in the system can be in a closed state when the first differential comparator is operating, so as to avoid floating and multiplication effects.

根据上述构想，系统中该第一差动比较器于该第二差动比较器于该第二差动比较器运作时可处于关闭状态。According to the above idea, the first differential comparator in the system can be in an off state when the second differential comparator is in operation.

根据本发明另一方面的差动比较电路系统，用以接收一电压范围的所有输入信号，并加以放大后输出一输出电压，其中该电压范围是分为较高电压的第一部份及较低电压的第二部份，该系统包含：一第一差动接收电路，用以接收该电压范围中第一部份的输入信号；一第一运算放大电路，电连接于该第一差动接收电路，用以将该第一差动接收电路所接收的电压加以放大，使产生该输出电压；一检测电路，电连接于该第一差动接收电路，当检测到该第一差动接收电路因输入信号的电压低于该电压范围的第一部份而无法运作时，产生一触发信号；一第二差动接收电路，电连接于该检测电路，相应该触发信号的驱动，而接收接收该电压范围中第二部份的输入信号；以及一第二运算放大电路，电连接于该第二差动接收电路，用以将该第二差动接收电路所接收的电压加以放大，使产生该输出电压。According to another aspect of the present invention, a differential comparator circuit system is used for receiving all input signals of a voltage range, amplifying them and outputting an output voltage, wherein the voltage range is divided into a first part of a higher voltage and a higher voltage part. The second part of the low voltage, the system includes: a first differential receiving circuit, used to receive the input signal of the first part in the voltage range; a first operational amplifier circuit, electrically connected to the first differential The receiving circuit is used to amplify the voltage received by the first differential receiving circuit to generate the output voltage; a detection circuit is electrically connected to the first differential receiving circuit, and when the first differential receiving circuit is detected When the circuit cannot operate because the voltage of the input signal is lower than the first part of the voltage range, a trigger signal is generated; a second differential receiving circuit is electrically connected to the detection circuit, corresponding to the driving of the trigger signal, and receives receiving the input signal of the second part in the voltage range; and a second operational amplifier circuit electrically connected to the second differential receiving circuit for amplifying the voltage received by the second differential receiving circuit so that produces this output voltage.

根据上述构想，系统中该差动比较电路系统包含一输出电路，用以输出该输出电压。According to the above idea, the differential comparison circuit system in the system includes an output circuit for outputting the output voltage.

根据上述构想，系统中该第二差动接收电路于该第一差动接收电路及该第一运算放大电路运作时可处于关闭状态，用以避免产生漂浮(floating)和加乘效果。According to the above idea, the second differential receiving circuit in the system can be in a closed state when the first differential receiving circuit and the first operational amplifier circuit are in operation, so as to avoid floating and multiplication effects.

根据上述构想，系统中该第一差动接收电路及该第一运算放大电路于该第二差动接收电路及该第二运算放大电路运作时可处于关闭状态。According to the above idea, the first differential receiving circuit and the first operational amplifier circuit in the system can be in an off state when the second differential receiver circuit and the second operational amplifier circuit are in operation.

根据本发明又一方面提供一种信号接收系统，用以接收一电压范围的所有输入信号，其中该电压范围是分为较高电压的第一部份及较低电压的第二部份，该系统是包含：一第一差动接收电路，用以接收该电压范围中较高电压的第一部份的输入信号；一检测电路，电连接于该第一差动接收电路，当检测到该第一差动接收电路因输入信号的电压低于该电压范围的第一部份而无法运作时，产生一触发信号；以及一第二差动接收电路，电连接于该检测电路，相应该触发信号的驱动，而接收属于较低电压的第二部份的输入信号，俾使达到接收该电压范围的所有输入信号的功效。According to yet another aspect of the present invention there is provided a signal receiving system for receiving all input signals of a voltage range, wherein the voltage range is divided into a first part of a higher voltage and a second part of a lower voltage, the The system includes: a first differential receiving circuit, used to receive the input signal of the first part of the higher voltage in the voltage range; a detection circuit, electrically connected to the first differential receiving circuit, when detecting the When the first differential receiving circuit cannot operate because the voltage of the input signal is lower than the first part of the voltage range, a trigger signal is generated; and a second differential receiving circuit is electrically connected to the detection circuit, correspondingly triggering The signal is driven, and the input signal belonging to the second part of the lower voltage is received, so as to achieve the effect of receiving all input signals in the voltage range.

(4)附图说明(4) Description of drawings

为使本发明的上述目的、特点和优点能更明显易懂，下文特举一较佳实施例，并配合附图进行详细说明：In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, a preferred embodiment is specifically cited below and described in detail in conjunction with the accompanying drawings:

图1(a)(b)是现有的用以接收输入信号的电路。Figure 1(a)(b) is an existing circuit for receiving an input signal.

图2是现有的结合P型金属氧化半导体晶体管(PMOS)与N型金属氧化半导体晶体管(NMOS)的接收信号电路示意图。FIG. 2 is a schematic diagram of a conventional receiving signal circuit combining a P-type metal-oxide-semiconductor transistor (PMOS) and an N-type metal-oxide-semiconductor transistor (NMOS).

图3是本发明较佳实施例的电路方块示意图。FIG. 3 is a schematic circuit block diagram of a preferred embodiment of the present invention.

图4是本发明较佳实施例的详细电路图。Fig. 4 is a detailed circuit diagram of a preferred embodiment of the present invention.

(5)具体实施方式(5) specific implementation

本发明的差动比较电路系统，将可由以下的实施例说明而得到充分的了解，使得熟悉本技术的人士可据以完成的，然而本发明的实施并非可由下列实施例而被限制其实施型态。The differential comparator circuit system of the present invention can be fully understood from the description of the following embodiments, so that those skilled in the art can complete it accordingly. However, the implementation of the present invention cannot be limited by the following embodiments. state.

请参阅图3及图4，其是本发明较佳实施例的电路方块图及详细电路结构示意图。Please refer to FIG. 3 and FIG. 4 , which are circuit block diagrams and detailed circuit structure diagrams of a preferred embodiment of the present invention.

本发明的差动接收比较电路系统可适用于通用串行总线(USB)界面的传输端，用来接收0～Vdd(约0～3.3伏特)的电压范围的所有输入信号，并加以放大后输出一输出电压，其中该电压范围可细分为较高电压的第一部份(约2～3.3伏特)及较低电压的第二部份(约0～2伏特)，该系统可包含：一检测电路30、一第一差动比较器31、一第二差动比较器32及一输出电路33。The differential receiving and comparing circuit system of the present invention can be applied to the transmission end of the Universal Serial Bus (USB) interface, and is used to receive all input signals in the voltage range of 0 ~ Vdd (about 0 ~ 3.3 volts), and output them after amplifying An output voltage, wherein the voltage range can be subdivided into a first part of a higher voltage (about 2-3.3 volts) and a second part of a lower voltage (about 0-2 volts), the system may include: a The detection circuit 30 , a first differential comparator 31 , a second differential comparator 32 and an output circuit 33 .

该第一差动比较器31可藉由第一差动接收电路311来接收输入电压约为2～3.3伏特的输入信号，再利用电连接于该第一差动接收电路311的第一运算放大电路312将所接收的电压加以放大，使产生一输出电压，并经由该输出电路33传送出去。The first differential comparator 31 can use the first differential receiving circuit 311 to receive an input signal with an input voltage of about 2-3.3 volts, and then use the first operational amplifier electrically connected to the first differential receiving circuit 311 The circuit 312 amplifies the received voltage to generate an output voltage, which is sent out through the output circuit 33 .

该检测电路30电连接于该第一差动接收电路311，主要用来检测该第一差动接收电路311的运作状态(即检测图4所示的a点处)。当该第一差动接收电路311处于接收状态时，产生一截止信号来将第二差动比较器32关闭，以避免电源损耗。当检测到该第一差动接收电路311因输入信号的电压是属于0～2伏特的电压范围而无法处于关闭状态时，产生一触发信号来驱动该第二差动比较器32接收输入信号。The detection circuit 30 is electrically connected to the first differential receiving circuit 311, and is mainly used to detect the operating state of the first differential receiving circuit 311 (ie, detect the point a shown in FIG. 4 ). When the first differential receiving circuit 311 is in the receiving state, it generates an off signal to turn off the second differential comparator 32 to avoid power loss. When detecting that the first differential receiving circuit 311 cannot be turned off because the voltage of the input signal belongs to the voltage range of 0-2 volts, a trigger signal is generated to drive the second differential comparator 32 to receive the input signal.

至于该第二差动比较器32相应该驱动信号的控制后，主要藉由第二差动接收电路321来接收输入电压约为0～2伏特的输入信号，再利用电连接于该第二差动接收电路321的第二运算放大电路322，将所接收的电压加以放大，使产生一输出电压，并经由该输出电路33传送出去。After the second differential comparator 32 is controlled by the driving signal, it mainly receives the input signal with an input voltage of about 0-2 volts through the second differential receiving circuit 321, and then electrically connects to the second differential comparator 321. The second operational amplifier circuit 322 of the dynamic receiving circuit 321 amplifies the received voltage to generate an output voltage and transmits it through the output circuit 33 .

其中该第一差动接收电路311是由N型金属氧化半导体晶体管(NMOS)所组成，可包含二接收端(IN+及IN-)，当IN+＞IN-时，该输出电压则输出高电位Vdd。当IN+＜IN-时，该输出电压则输出低电位0。上述的输出电压会随着对于IN+与IN-的大小不同的定义而有所改变。The first differential receiving circuit 311 is composed of N-type metal oxide semiconductor transistors (NMOS), and can include two receiving terminals (IN+ and IN-). When IN+>IN-, the output voltage outputs a high potential Vdd . When IN+<IN-, the output voltage outputs low potential 0. The above-mentioned output voltage will vary with different definitions of IN+ and IN-.

当然，该第二差动接收电路321是由一组N型金属氧化半导体晶体管(NMOS)和一组P型金属氧化半导体晶体管(PMOS)所组成，有避免漂浮(floating)及加乘效果，可包含二组接收端(IN+及IN-)及一电压转换电路(level shift circuit)3211，当PMOS的IN+＞IN-时，该输出电压则可输出高电位Vdd。当PMOS的IN+＜IN-时，该输出电压依不同的需求则可输出低电位0。上述的输出电压会随着对于IN+与IN-的大小不同的定义而有所改变。Of course, the second differential receiving circuit 321 is composed of a group of N-type metal oxide semiconductor transistors (NMOS) and a group of P-type metal oxide semiconductor transistors (PMOS), which can avoid floating and multiplication effects, and can It includes two sets of receiving terminals (IN+ and IN-) and a voltage conversion circuit (level shift circuit) 3211. When IN+>IN- of the PMOS, the output voltage can output a high potential Vdd. When IN+<IN- of PMOS, the output voltage can output low potential 0 according to different requirements. The above-mentioned output voltage will vary with different definitions of IN+ and IN-.

且该第二差动接收电路321会于PMOS的IN+及IN-接收电压太高时，则自动关闭该第二差动接收电路321。其中该电压转换电路3211可用以将所接收的输入信号先进行初步放大，并于该检测电路30产生该截止信号时，将该二组信号接收端关闭。And the second differential receiving circuit 321 automatically turns off the second differential receiving circuit 321 when the receiving voltages of IN+ and IN− of the PMOS are too high. Wherein the voltage conversion circuit 3211 can be used to preliminarily amplify the received input signal, and when the detection circuit 30 generates the cut-off signal, the two sets of signal receiving ends are turned off.

综合上面所述，本发明的差动比较电路系统藉由检测电路能够确保不用以接收信号的差动比较器能够完全关闭，进而解决现有技术会浪费电源的问题，且能够接收的电压范围(Common Mode Range)为0～Vdd，解析度(resolution)可达到50～200mV(目前USB 1.1版规定为200mV)，而最大的延迟时间为7ns，由上述的实际模拟结果可知，其结果较USB 1.1版所订的规格要好上很多，因此具产业价值，进而达到发展本发明的发明目的。Based on the above, the differential comparator circuit system of the present invention can ensure that the differential comparator that is not used to receive signals can be completely turned off through the detection circuit, thereby solving the problem of wasting power in the prior art, and the acceptable voltage range ( Common Mode Range) is 0~Vdd, the resolution can reach 50~200mV (the current version 1.1 of USB is 200mV), and the maximum delay time is 7ns. From the above actual simulation results, the result is better than that of USB 1.1 The specification set by the version is much better, so it has industrial value, and then reaches the purpose of developing the invention of the present invention.

Claims (12)

1. back output one output voltage in order to receiving all input signals of a voltage range, and is amplified in differential comparison circuit system, wherein this voltage range be divided into high voltage first partly and low voltage second partly, this system comprises:
One first differential comparator in order to receiving in this voltage range first partly the input signal, and is amplified the voltage that is received, and is produced this output voltage;
One testing circuit is electrically connected on this first differential comparator, when detecting the voltage of this first differential comparison circuit because of input signal and be lower than first of this voltage range and partly can't operate, produces a triggering signal; And
One second differential comparator is electrically connected on this testing circuit, driving that mutually should triggering signal, and receive in this voltage range second partly the input signal, and the voltage that is received is amplified, in order to produce this output voltage.
2. the system as claimed in claim 1 is characterized in that, this differential comparison circuit system is the transmission ends that is applicable to a general serial bus interface.
3. the system as claimed in claim 1 is characterized in that, this first differential comparator comprises:
One first differential receiving circuit is in order to receive the input signal of first part in this voltage range; And
One first operational amplification circuit is electrically connected on this first differential receiving circuit, is amplified in order to the voltage that this first differential receiving circuit is received, and makes to produce this output voltage.
4. the system as claimed in claim 1 is characterized in that, this second differential comparator comprises:
One second differential receiving circuit is electrically connected on this testing circuit, driving that mutually should triggering signal, and receive in this voltage range second partly the input signal; And
One second operational amplification circuit is electrically connected on this second differential receiving circuit, is amplified in order to the voltage that this second differential receiving circuit is received, and makes to produce this output voltage.
5. the system as claimed in claim 1 is characterized in that, this differential comparison circuit system comprises an output circuit, in order to export this output voltage.
6. the system as claimed in claim 1 is characterized in that, this second differential comparator is to be in closed condition when the running of this first differential comparator, and is floating in order to avoid producing.
7. the system as claimed in claim 1 is characterized in that, this first differential comparator is to be in closed condition when this second differential comparator running.
8. back output one output voltage in order to receiving all input signals of a voltage range, and is amplified in differential comparison circuit system, wherein, this voltage range be divided into high voltage first partly and low voltage second partly, this system comprises:
One first differential receiving circuit is in order to receive the input signal of first part in this voltage range;
One first operational amplification circuit is electrically connected on this first differential receiving circuit, is amplified in order to the voltage that this first differential receiving circuit is received, and makes to produce this output voltage;
One testing circuit is electrically connected on this first differential receiving circuit, when detecting the voltage of this first differential receiving circuit because of input signal and be lower than first of this voltage range and partly can't operate, produces a triggering signal;
One second differential receiving circuit is electrically connected on this testing circuit, driving that mutually should triggering signal, and receive in this voltage range second partly the input signal; And
One second operational amplification circuit is electrically connected on this second differential receiving circuit, is amplified in order to the voltage that this second differential receiving circuit is received, and makes to produce this output voltage.
9. system as claimed in claim 8 is characterized in that, this differential comparison circuit system comprises an output circuit, in order to export this output voltage.
10. system as claimed in claim 8 is characterized in that, this second differential receiving circuit is to be in closed condition when the running of this first differential receiving circuit and this first operational amplification circuit, and is floating in order to avoid producing.
11. system as claimed in claim 8 is characterized in that, this first differential receiving circuit and this first operational amplification circuit are to be in closed condition when this second differential receiving circuit and the running of this second operational amplification circuit.
12. a receiving system, in order to receive all input signals of a voltage range, wherein, this voltage range is to be divided into first part of high voltage and second part of low voltage, and this system comprises:
One first differential receiving circuit is in order to receive the input signal of first part of high voltage in this voltage range;
One testing circuit is electrically connected on this first differential receiving circuit, when detecting the voltage of this first differential receiving circuit because of input signal and be lower than first of this voltage range and partly can't operate, produces a triggering signal; And
One second differential receiving circuit is electrically connected on this testing circuit, driving that mutually should triggering signal, and receive second partly the input signal that belongs to low voltage, to reach all input signals that receive this voltage range.
CN 03142427 2003-06-06 2003-06-06 Differential comparison circuit system Expired - Fee Related CN1257611C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 03142427 CN1257611C (en) 2003-06-06 2003-06-06 Differential comparison circuit system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 03142427 CN1257611C (en) 2003-06-06 2003-06-06 Differential comparison circuit system

Publications (2)

Publication Number Publication Date
CN1553576A true CN1553576A (en) 2004-12-08
CN1257611C CN1257611C (en) 2006-05-24

Family

ID=34324009

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 03142427 Expired - Fee Related CN1257611C (en) 2003-06-06 2003-06-06 Differential comparison circuit system

Country Status (1)

Country Link
CN (1) CN1257611C (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103430453A (en) * 2011-01-27 2013-12-04 高通股份有限公司 High voltage tolerant differential receiver
CN107909786A (en) * 2017-06-15 2018-04-13 国网浙江省电力公司湖州供电公司 M BUS inputs micropower wirelessly exports doubling converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103430453A (en) * 2011-01-27 2013-12-04 高通股份有限公司 High voltage tolerant differential receiver
CN107909786A (en) * 2017-06-15 2018-04-13 国网浙江省电力公司湖州供电公司 M BUS inputs micropower wirelessly exports doubling converter

Also Published As

Publication number Publication date
CN1257611C (en) 2006-05-24

Similar Documents

Publication Publication Date Title
JP6683407B2 (en) Overcurrent protection circuit for row display circuit of display panel and its array substrate
US10177764B2 (en) Input/output circuit
TWI408638B (en) Driver circuit system and method of elevating slew rate of operational amplifier
US7768296B2 (en) Electronic device and method
CN105845068B (en) A kind of power supply circuit of source drive module, display panel and display device
CN104348469A (en) Voltage level converting circuit
CN110098830B (en) Substrate switching circuit and level conversion circuit of transistor
CN102622024A (en) level conversion circuit
US20190089356A1 (en) Level Shifter Capable of Outputting Positive and Negative Voltages
CN107633798B (en) Potential conversion circuit and display panel
JP2006197541A (en) Push-pull buffer amplifier and source driver
US11770120B2 (en) Bootstrap circuit supporting fast charging and discharging and chip
CN1553576A (en) Differential comparison circuit system
CN105897252A (en) Level shifter circuit applied to display device
CN101739963A (en) Drive circuit system and method for improving slew rate of operational amplifier
CN100555397C (en) Level shifter and panel display device having the same
US20200212905A1 (en) Square Wave Generating Method and Square Wave Generating Circuit
CN106788493B (en) Low-speed transmitter circuit
CN1167188C (en) Amplifier
US6292030B1 (en) Pre-charged high-speed comparator
CN100466033C (en) Source driver output stage circuit, buffer circuit and voltage modulation method thereof
US7679421B1 (en) Level shift circuit
US9537469B2 (en) CMOS level shifter with reduced high voltage transistor count
TW200408188A (en) Differential comparison circuit system
CN102891672A (en) Grid voltage bootstrapped switch with low on-resistance and substrate bias effect elimination method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20060524

CF01 Termination of patent right due to non-payment of annual fee