CN1553485A - Method for lowering resistance value of cobalt disilicide layer of semiconductor devices - Google Patents
Method for lowering resistance value of cobalt disilicide layer of semiconductor devices Download PDFInfo
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- CN1553485A CN1553485A CNA031386954A CN03138695A CN1553485A CN 1553485 A CN1553485 A CN 1553485A CN A031386954 A CNA031386954 A CN A031386954A CN 03138695 A CN03138695 A CN 03138695A CN 1553485 A CN1553485 A CN 1553485A
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Abstract
In the invention, first a layer of metal cobalt is formed on silicon substrate. Next, two times of annealing treatment are carried out. First annealing treatment turns layer of metal cobalt to layer of cobalt silicide (CoSi). Then, a covering layer in thickness of 1000-3000 Angstrom is formed to cover the layer of metal cobalt in order to restrain regrowth of crystal grain of cobalt silicide in following procedure. Finally, second annealing treatment is carried out to turn the layer of cobalt silicide to layer of disilcobalt (CoSi2).
Description
Technical field
The present invention relates to a kind of manufacturing method of semiconductor module, and be particularly related to a kind of method that reduces the resistance value of cobalt disilicide in the assembly (CoSi2) layer.
Background technology
In the technology of semiconductor subassembly, how for example in grid, source electrode or the drain electrode, form cobalt disilicide (CoSi2) layer of low resistance at the internal electrical tie point.Generally speaking, the manufacture method of cobalt disilicide is earlier metallic cobalt (Co) layer to be formed on the siliceous substrate, through twice annealing in process (annealingtreatment) cobalt is transformed into cobalt disilicide again.Wherein, primary annealing in process is that shilling cobalt is diffused in the siliceous substrate, to form a cobalt silicide (CoSi) layer.Secondary annealing in process then is the cobalt disilicide that silicon cobalt substrate is transformed into low resistance, uses the resistance value that reduces assembly.
With reference to Figure 1A to 1D, it illustrates the classical production process of cobalt disilicide layer in a kind of semiconductor subassembly.At first, provide a silicon substrate 10, shown in Figure 1A.Formed regions and source 12 on the silicon substrate 10, grid 14, grid oxic horizon 16 and sidewall resilient coating 18.
Then, with sputtering way one layer of metal cobalt (cobalt layer) 20 is formed on the silicon substrate 10, shown in Figure 1B.Afterwards, titanium or titanium nitride layer can be deposited on layer of metal cobalt top (not shown) again, avoid oxidation with the protection metallic cobalt.
Then, carry out the annealing in process first time, make the layer of metal cobalt 20 of part be transformed into cobalt silicide (CoSi) layer 22, shown in Fig. 1 C.All the other unreacted cobalts then are denoted as 20A.Wherein, for the first time the enforcement temperature of annealing in process between 450 ℃ to 550 ℃ scopes.After first time annealing in process, remove unreacted cobalt 20A.
Then, carry out the annealing in process second time, its temperature of implementing the temperature ratio annealing in process first time is taller, between 750 ℃ to 880 ℃ scopes, so that cobalt silicide (CoSi) layer 22 is transformed into cobalt disilicide (CoSi2) layer 23.Wherein, the resistance of cobalt disilicide (CoSi2) layer 23 is very low, therefore can reduce the resistance as grid, source electrode or drain electrode.
Yet, when the second time of high temperature, annealing in process was carried out, the crystal grain meeting regrowth (re-grow) of original cobalt silicide (CoSi) layer 22, and form bigger crystal grain.And have the cobalt disilicide (CoSi2) of large scale crystal grain, can easier regrowth under the thermal pressure of follow-up high-temperature process.This kind phenomenon is " caking phenomenon " known (agglomeration).Therefore, according to above-mentioned traditional method, can make cobalt disilicide layer produce caking phenomenon, and cause the defective of assembly.For example shown in Fig. 1 D, formed cobalt disilicide layer 23 surfaces are very coarse, or the bulky crystal grain of cobalt disilicide 232 passes regions and source 12 and contacts with silicon substrate 10, or can't form continuous cobalt disilicide layer 23 after the crystal grain regrowth and produce a discontinuity zone 231.
In Fig. 1 D,, and then influence the flatness of subsequent deposition in the layer of top because the rough surface of cobalt disilicide layer that caking phenomenon causes 23 can reduce the flatness of cobalt disilicide layer 23.Unevenness herein (unevenness) also has the unevenness at the interface of cobalt disilicide layer 23 and regions and source 12 except referring to the appearance of cobalt disilicide layer 23.If form a contact hole (not shown) in an intermediate insulating layer, and cobalt disilicide layer 23 is carried out etching, then uneven cobalt disilicide layer 23 can make etching Be Controlled accurately, and silicon substrate 10 is had by the possibility of over etching.In case contact hole contacts with silicon substrate 10, between contact hole and silicon substrate 10, will produce the situation of electric leakage.Moreover, if the bulky crystal grain 232 of cobalt disilicide passes regions and source 12 and contacts with silicon substrate 10,, also can cause electric leakage when voltage one is applied on the semiconductor subassembly.In addition, the discontinuity zone 231 that is produced because of the crystal grain regrowth can increase the resistance value of cobalt disilicide layer 23, and the performance of assembly is impacted.And above-mentioned defective is after the annealing in process of the follow-up a succession of high temperature of cobalt disilicide layer 23 experience, and it is more serious to become.
Therefore, how to make the cobalt disilicide layer of formation more smooth, in fact the important goal of making great efforts for the research staff.
Summary of the invention
In view of this, the purpose of this invention is to provide the manufacture method of cobalt disilicide layer in a kind of semiconductor subassembly, with the flatness of increase cobalt disilicide layer, and the resistance value of reduction cobalt disilicide layer.
According to purpose of the present invention, a kind of manufacture method that reduces the resistance value of cobalt disilicide layer in the semiconductor subassembly is proposed.At first, provide a silicon substrate, and form a layer of metal cobalt on silicon substrate.Then, by the annealing in process first time, form a cobalt silicide (CoSi) layer, the unreacted metal cobalt then removes in the selective etch mode.Then, form a cover layer in the silicon cobalt substrate top, to suppress the regrowth in follow-up high-temperature process of cobalt silicide crystal grain.Then, by the annealing in process second time, silicon cobalt substrate is transformed into cobalt disilicide (CoSi2) layer.According to the present invention, cover layer for example is one deck silicon oxide layer or one deck silicon nitride layer.And tectal thickness is between 1000 to 3000 scopes.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below
Description of drawings
Figure 1A to 1D illustrates the classical production process of cobalt disilicide layer in a kind of semiconductor subassembly; And
Fig. 2 A to 2E illustrates the manufacture method according to the resistance value of cobalt disilicide layer in the reduction semiconductor subassembly of the preferred embodiment of the present invention.
Wherein, graphic description of symbols is as follows:
10: silicon substrate 12: regions and source
14: grid 16: grid oxic horizon
18: sidewall resilient coating 20: metallic cobalt (Co)
20A: unreacted cobalt 22: cobalt silicide (CoSi) layer
23,26: cobalt disilicide (CoSi2) layer 24: cover layer
232: big cobalt disilicide crystal grain 231: the discontinuity zone of cobalt disilicide layer
Embodiment
With reference to Fig. 2 A to 2E, it illustrates the manufacture method according to the resistance value of cobalt disilicide layer in the reduction semiconductor subassembly of the preferred embodiment of the present invention.Shown in Fig. 2 A, provide a silicon substrate 10 earlier.Regions and source 12 is formed at silicon substrate 10 places according to conventional method, to define a channel region.Grid 14, main material is a polysilicon, is formed at channel region, and is positioned at the top of a grid oxic horizon 16.And sidewall resilient coating 18, material for example is a silica, can be formed on the two side of grid 14.
Then, shown in Fig. 2 B, on silicon substrate 10, form a layer of metal cobalt 20, and layer of metal cobalt 20 and cover gate 14.Layer of metal cobalt can form by sputtering way.Afterwards, a titanium layer or titanium nitride layer can be deposited on the top (not shown) of layer of metal cobalt 20, avoid oxidation with the protection metallic cobalt.
Then, shown in Fig. 2 C, carry out the annealing in process first time, make the layer of metal cobalt 20 of part be transformed into cobalt silicide (CoSi) layer 22.The ground that comprises the silicon composition as silicon substrate 10 and grid 14, can consume a part of silicon with the metallic cobalt reaction.All the other unreacted cobalts then are denoted as 20A.Wherein, for the first time the enforcement temperature of annealing in process between 450 ℃ to 550 ℃ scopes, about 30 seconds to 90 seconds of the time of carrying out.
Then, remove unreacted cobalt 20A, and carry out an important step of the present invention.Shown in Fig. 2 D, form a cover layer 24 in the top of silicon cobalt substrate 22.This cover layer can be one deck silicon oxide layer or one deck silicon nitride layer.And tectal thickness is about between 1000 to the 3000 scopes, preferably is about 2000 .
Then, shown in Fig. 2 E, carry out the annealing in process second time, make cobalt silicide (CoSi) layer 22 be transformed into cobalt disilicide (CoSi2) layer 26.The enforcement temperature of annealing in process compares the enforcement temperature height of annealing in process for the first time for the second time, between 750 ℃ to 880 ℃ scopes, and about 30 seconds to 90 seconds of enforcement time.After forming cobalt disilicide (CoSi2) layer 26, cover layer can be removed or stay, and decides on process requirements, is not particularly limited.
Among the present invention, physically suppress cobalt silicide (CoSi) crystal grain, make it even assembly experiences the thermal pressure of follow-up a succession of high-temperature process, also be not easy regrowth in the second time of regrowth (re-grow) during annealing in process with cover layer 24.Therefore, not only have very smooth appearance according to the formed cobalt disilicide of manufacture method of the present invention (CoSi2) layer, the interface of cobalt disilicide layer and regions and source is also very smooth, and solves the problem of traditional handicraft smoothly.For example: shaggy cobalt disilicide layer or excessive cobalt disilicide crystal grain pierce through regions and source and contact with silicon substrate 10 or the crystal grain regrowth after make many defectives such as cobalt disilicide layer is discontinuous, all can be avoided.
In addition, the manufacture method of reduction cobalt disilicide resistance of the present invention can be applicable to any technology that need form cobalt disilicide in a siliceous substrate.Below promptly the assembly after making is carried out the resistance test.
The resistance test
Test suite comprises two groups of samples, and (sheet resistance, measurement Rs) is listed in table one to sheet resistance.Wherein, sample A is according to the sample of manufacture method of the present invention (shown in Fig. 2 A to 2E) made, contains cover layer.Sample B is according to the sample of traditional manufacture method (shown in Figure 1A to 1D) made, does not have cover layer.
Table one
At first, sample A (shown in Fig. 2 E) and sample B (shown in Fig. 1 D) under 950 ℃ high temperature, were annealed 360 seconds.Then, measure its sheet resistance value respectively.Measurement shows: the average sheet resistance value of sample A (having cover layer) has only half (7.88:14.630) of the average sheet resistance value of sample B (not tectate) approximately.Therefore, test result proves that according to the sample A of the inventive method made, its cover layer can effectively suppress the rising of sheet resistance value really.
In addition, have tectal sample A when the annealing of also not carrying out 950 ℃, 360 seconds, measure its sheet resistance value earlier, be about 6.6.Compare with the average sheet resistance value 7.88 behind the high annealing, how many sheet resistance value of annealing back sample A do not increase.Therefore, according to manufacture method of the present invention, has the thermal stability that tectal sample A can increase cobalt disilicide layer really.
In sum; though the present invention is with by preferred embodiment openly as above, so it is not in order to limiting the present invention, and those skilled in the art without departing from the spirit and scope of the present invention; can do various changes and improvement, so protection scope of the present invention is as the criterion when looking claims.
Claims (24)
1. manufacture method that reduces the resistance value of cobalt disilicide layer in the semiconductor subassembly comprises that step is as follows:
One silicon substrate is provided;
Form a layer of metal cobalt on this silicon substrate;
By an annealing in process for the first time, form a cobalt silicide (CoSi) layer in the intersection of this silicon substrate and this layer of metal cobalt, wherein, a unreacted metal cobalt layer residues in above this silicon cobalt substrate;
Remove this unreacted metal cobalt layer in the selective etch mode;
Form a cover layer in this silicon cobalt substrate top; And
By an annealing in process for the second time, this silicon cobalt substrate is transformed into one deck cobalt disilicide (CoSi2) layer.
2. manufacture method as claimed in claim 1, wherein this cover layer is one deck silicon oxide layer.
3. manufacture method as claimed in claim 1, wherein this cover layer is one deck silicon nitride layer.
4. manufacture method as claimed in claim 1, wherein this tectal thickness is about between 1000 to the 3000 scopes.
5. manufacture method as claimed in claim 4, wherein this tectal thickness preferably is about 2000 .
6. manufacture method as claimed in claim 1, wherein this second time annealing in process the enforcement temperature be higher than the enforcement temperature of this of annealing in process first time.
7. manufacture method as claimed in claim 1, wherein this first time annealing in process carry out temperature between 450 ℃ to 550 ℃ scopes.
8. manufacture method as claimed in claim 7, wherein for the first time the enforcement time of annealing in process about between 30 seconds to 90 seconds scopes.
9. manufacture method as claimed in claim 1 wherein is somebody's turn to do the enforcement temperature of the annealing in process second time between 750 ℃ to 880 ℃ scopes.
10. manufacture method as claimed in claim 8, wherein for the second time the enforcement time of annealing in process about between 30 seconds to 90 seconds scopes.
11. manufacture method as claimed in claim 1 wherein implementing this for the first time before the annealing in process, forms a titanium layer earlier above this layer of metal cobalt.
12. manufacture method as claimed in claim 1 wherein implementing this for the first time before the annealing in process, forms one deck titanium nitride layer earlier above this layer of metal cobalt.
13. manufacture method as claimed in claim 1 wherein after this silicon cobalt substrate is transformed into this cobalt disilicide layer, removes this cover layer.
14. a semiconductor subassembly that utilizes the described manufacture method gained of claim 1 comprises:
One silicon substrate;
One deck cobalt disilicide (CoSi2) layer is formed on this silicon substrate; And
One cover layer is formed at this cobalt disilicide layer top, and this tectal thickness is about between 1000 to the 3000 scopes, and this tectal material is silica or silicon nitride.
15. a manufacture method that reduces the resistance value of cobalt disilicide layer in the semiconductor subassembly comprises that step is as follows:
One silicon substrate is provided;
Form a layer of metal cobalt on this silicon substrate;
Under one first heating-up temperature,, make this layer of metal cobalt be transformed into one deck cobalt silicide (CoSi) layer to this assembly heating;
In the selective etch mode, remove a unreacted metal cobalt layer that residues in this silicon cobalt substrate top;
Form a cover layer in this silicon cobalt substrate top, this tectal thickness is about between 1000 to the 3000 scopes, and this tectal material is silica or silicon nitride; And
Under one second heating-up temperature,, make this silicon cobalt substrate be transformed into one deck cobalt disilicide (CoSi2) layer to this assembly heating.
16. manufacture method as claimed in claim 15, wherein this tectal thickness preferably is about 2000 .
17. manufacture method as claimed in claim 15, wherein this second heating-up temperature is higher than this first heating-up temperature.
18. manufacture method as claimed in claim 15, wherein this first heating-up temperature is between 450 ℃ to 550 ℃ scopes.
19. manufacture method as claimed in claim 18 wherein is transformed into this layer of metal cobalt the heating steps of this silicon cobalt substrate, carries out about 30 seconds to 90 seconds.
20. manufacture method as claimed in claim 15, wherein this second heating-up temperature is between 750 ℃ to 880 ℃ scopes.
21. manufacture method as claimed in claim 20 wherein is transformed into this silicon cobalt substrate the heating steps of this cobalt disilicide layer, carries out about 30 seconds to 90 seconds.
22. manufacture method as claimed in claim 15 wherein after the step that forms this layer of metal cobalt, more forms a titanium layer or one deck titanium nitride layer above this layer of metal cobalt.
23. manufacture method as claimed in claim 15 wherein after this silicon cobalt substrate is transformed into this cobalt disilicide layer, removes this cover layer.
24. a semiconductor subassembly that utilizes the described manufacture method gained of claim 15 comprises:
One silicon substrate;
One deck cobalt disilicide (CoSi2) layer is formed on this silicon substrate; And
One cover layer is formed at this cobalt disilicide layer top.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031386954A CN1307694C (en) | 2003-06-03 | 2003-06-03 | Method for lowering resistance value of cobalt disilicide layer of semiconductor devices |
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| CNB031386954A CN1307694C (en) | 2003-06-03 | 2003-06-03 | Method for lowering resistance value of cobalt disilicide layer of semiconductor devices |
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| CN1553485A true CN1553485A (en) | 2004-12-08 |
| CN1307694C CN1307694C (en) | 2007-03-28 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100334686C (en) * | 2004-12-09 | 2007-08-29 | 上海交通大学 | Method for increasing CoSi2 film heat stability |
| CN100437916C (en) * | 2005-04-25 | 2008-11-26 | 恩益禧电子股份有限公司 | Method for manufacturing semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3545084B2 (en) * | 1995-03-20 | 2004-07-21 | 富士通株式会社 | Method for manufacturing semiconductor device |
| JP4137182B2 (en) * | 1995-10-12 | 2008-08-20 | 株式会社東芝 | Sputter target for wiring film formation |
| JP3554514B2 (en) * | 1999-12-03 | 2004-08-18 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
| CN1388572A (en) * | 2002-06-20 | 2003-01-01 | 上海华虹（集团）有限公司 | Method of preparing cobalt silicide |
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2003
- 2003-06-03 CN CNB031386954A patent/CN1307694C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100334686C (en) * | 2004-12-09 | 2007-08-29 | 上海交通大学 | Method for increasing CoSi2 film heat stability |
| CN100437916C (en) * | 2005-04-25 | 2008-11-26 | 恩益禧电子股份有限公司 | Method for manufacturing semiconductor device |
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