CN1549436A - Middle voltage dc-to-ac converter with unit active bypass function and bypass control method thereof - Google Patents
Middle voltage dc-to-ac converter with unit active bypass function and bypass control method thereof Download PDFInfo
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Abstract
The present invention discloses a medium voltage inverter with unit active by-pass function and its by-pass control method. The described equipment includes main transformer and main control system formed from main control software system and main control hardware system, also includes inverter unit main circuit connected on one secondary winding of main transformer, it includes a three-phase full-bridge rectifier circuit, a single-phase full-bridge inverter circuit and a by-pass circuit. Said unit control system utilizes the unit fault receiving and detection module to make fault sampling and classification coding and utilizes the coordination of main control software and unit control logic module to make operation and logic control, and can output the control signal for controlling switching time of power device and by-pass control signal.
Description
Technical field
The present invention relates to a kind of inverter bypass realization technology, relate in particular to a kind of have the unit initiatively middle pressure inverter and the by-pass governing method thereof of bypass function, belong to Motor Control Field.
Background technology
Middle pressure inverter is the important motivity equipment in the factory system, and the application aspect industrial energy saving is very extensive.Because motor is an inductive element, operating reactive power loss can cause the waste of power system capacity, so seal in the device of capacitive---inverter, can improve the power factor of power consumption equipment, improve the performance of power supply grid, and play energy-conservation, as to reduce environmental pollution effect.The high-quality waveform output of especially output unit series connection, waveform reorganization voltage source inverter makes the frequency conversion application of common high-voltage motor and even old high-voltage motor become possibility.
The middle inverter of pressing owing to inverter unit series connection quantity is more, if shut down because of individual elements breaks down, can make the reliability of complete machine be affected.In order to overcome this shortcoming, some producers adopt inverter unit bypass technology, promptly when certain unit breaks down with the trouble unit by-pass operation, system equipment still can be moved by bringing onto load under the situation that a few inverter unit damages continuously, guarantee the safety of system.
In the existing bypass technology, the inverter unit main circuit adopts switch contact as the by-pass governing switch, and the unit enters by-pass operation after this closing of contact; Master control system software carries out waveform computing adjustment the same period, makes equipment by-pass operation under symmetric mode.The strategy of bypass is that employing system active bypass mode realizes by-pass operation, and promptly before implementing bypass, master control system initiatively stops to send pwm signal, motor freedom of entry dead ship condition to the unit; After treating that the bypass processing is ready, send pwm signal to the residue unit again again, enter by-pass operation.
The defective of prior art is, adopts when switch contact is closed connects bypass resistance, and bypass cock closes a floodgate needs certain hour, is generally the hundreds of millisecond; When employing system active bypass mode is switched, also be designed to the hundreds of millisecond switching time.This handoff delay is 250ms in the common engineering design.Equipment must initiatively stop output waveform between transfer period, causes unit bus overvoltage even hardware damage otherwise trouble unit can be recharged.After arriving switching time, send pwm pulse to the unit once more, the restorer operation.Directly recover the PWM operation by former mode and can cause long electric transient process owing to the reason on the circuit, can't use.Be head it off, must cooperate in the former bypass technology and adopt the driving start-up technique to realize by-pass operation.But still there is tangible transient process in this technical scheme in recovering the by-pass operation process, bigger current fluctuation can occur, and the bypass success rate is lower, causes disorderly closedown easily.
Summary of the invention
The objective of the invention is at the deficiencies in the prior art; a kind of have the unit initiatively middle pressure inverter and the by-pass governing method thereof of bypass function are proposed; adopt the method for total digitalization and software to realize by-pass governing; make motor not realizing the switching of unperturbed bypass under the stopped status; greatly improve the success rate of bypass, and improved the running quality of electrical network.
Middle pressure inverter with unit active bypass function of the present invention comprises main transformer, and the master control system by main control software system and master control hardware system constitute also comprises:
The inverter unit main circuit, be connected on secondary winding of main transformer, it comprises a three-phase bridge rectification circuit, a single-phase full bridge inverter circuit and a bypass resistance, by receiving power device control signal switching time of described unit control system output, the output pulse width modulation signal is given load motor, when cell failure occurring, the by-pass governing signal that the receiving element control system is sent falls this unit main circuit bypass.
Unit control system carries out fault sampling and sorting code number by cell failure reception and detection module; Fit into row operation and logic control by main control software and unit controls logic module, control signal and the by-pass governing signal of output power controlling devices switch time.
Described unit control system comprises:
Fault sampling and coding module are classified, encode, are reported fault;
The bypass Logic control module according to the locking signal of master control system, is carried out the drive controlling to power switch pipe IGBT and controllable silicon SCR; Initiatively handle to master control system application bypass, the permission bypass command that sends to the unit according to master control system is carried out the also by-pass operation state of monitoring means main circuit, and failure is dealt with and reported master control system to bypass;
The next optical fiber communication coding/decoding module will location mode be sent to master control system behind the coding, and delivers to the bypass logic control element behind the unit controls information decoding that master control system is sent here.Adopt the full duplex serial communication mode to carry out information interaction between this unit and the master control system, adopt special-purpose communication protocol to shake hands.
Described inverter unit main circuit comprises:
The three-phase bridge rectification circuit of forming by Dz1～Dz6 and C1; Be connected on the inversion full-bridge circuit of forming by high-power switch tube Z1, Z2, Z3, Z4 thereafter, the bypass full-bridge circuit of forming by by-pass diode Da, Db, Dc, Dd, the output of inversion full-bridge circuit is connected with the input of bypass full-bridge circuit, on two arms of described bypass full-bridge circuit, bypass controllable silicon X1 also in parallel; High-power switch tube Z1, Z2, Z3, Z4 receive and carry out normal pulse-width modulation from the drive control signal of described unit control system, the control end of bypass controllable silicon X1 receives the by-pass governing signal, so that the output of the inverter unit main circuit that breaks down is by bypass.
Described master control system comprises master control hardware system and main control software system.Wherein the master control hardware system comprises CPU module, PWM logic processing module, upper optical fiber communication coding/decoding module, I/O interface module, power module.The CPU module realizes calculating and logic judging function; The PWM logic processing module realizes output PWM voltage waveform logical process; Upper optical fiber communication coding/decoding module is realized the bidirectional serial communication function between master control system and the unit; The I/O interface module is realized the interface of inverter and external user system; Power module is used for the master control system power supply.
The main control software system is the application software of inverter, realizes the various functions of inverter.Comprise the by-pass governing function that realizes inverter in the present invention.
The unit of the middle pressure inverter that the present invention proposes is the by-pass governing method initiatively, comprises the steps:
The first step, the fault of unit control system sampling coding module detect and are reported to the bypass Logic control module after fault takes place, carry out filtering wave by prolonging time and failure modes after, fault is initiatively reported master control system;
Second step after master control system receives the fault-signal that reports, judged whether to carry out bypass and handles, if then bypass is allowed signal to send to unit control system by the optical fiber communication mode, otherwise send the bypass inhibit signal;
In the 3rd step, whether master control system successfully detects bypass, if the bypass success continues to keep the by-pass operation state, if bypass is unsuccessful, carries out for the 4th step;
In the 4th step, block the output of unit control system and send out failure alarm signal to master control system.
Unit recited above is the by-pass governing method initiatively, also comprise, after unit control system receives bypass permission/inhibit signal, control signal is delivered to the bypass Logic control module, send the by-pass governing signal by the bypass Logic control module to the driving pulse generation module when allowing by-pass operation, the bypass controllable silicon in the driver element main circuit is realized the unit by-pass operation; When forbidding bypass, then block the output of unit control system and send out failure alarm signal to master control system.
Unit recited above initiatively by-pass governing method comprises that also after the bypass success, master control system monitors the operation of bypass state, if bypass failure in unit is blocked the output of unit control system and sent out failure alarm signal to master control system.
Initiatively in the by-pass governing method, system allows the number and the mode of trouble unit to preestablish for unit recited above, when breaking down more than the unit that allows number in the system, handles according to the bypass failure.
System adopts unperturbed bypass algorithm during by-pass operation, promptly keeps before and after the by-pass operation, and the voltage magnitude of system's output keeps consistent continuously with phase place.Concrete way is: behind the by-pass operation, adopt totally digitilized software approach to handle exporting the PWM waveform, output voltage amplitude adopts automatic method for improving, and the output voltage phase place adopts directly computational methods continuously, realizes the continuous of output voltage amplitude and phase place.In the time can't realizing that amplitude is consistent fully continuously, output voltage amplitude adopts greatest limit to promote computational methods.
The present invention adopts special sequential logic to realize bypass switching controls and Stateful Inspection; When certain certain unit of layer breaks down, the unit carries out fault alarm to master control system immediately, initiatively enters the by-pass operation state after the signal of receiving master control system approval bypass, and reports that to master control system bypass successfully; Master control system enters bypass permission judgement after receiving alarm signal immediately, if master control system allows by-pass operation then ratify this element immediately to enter the by-pass operation state, shuts down otherwise report to the police.Behind the by-pass operation running status is monitored any time bypass failure shutdown of all reporting to the police.Adopt three symmetrical output waveforms after the bypass, the present invention can realize the bypass of any number of stages.
Description of drawings
Fig. 1 is a unit bypass sequential chart;
Fig. 2 is a master control system bypass sequential chart;
Fig. 3 is the inverter system structure chart;
Fig. 4 is unit main circuit structure figure;
Fig. 5 is the unit control system structure chart;
Fig. 6 is the master control system structure chart;
Fig. 7 is unit output voltage waveforms when normally moving;
Output voltage waveforms when Fig. 8 is the unit by-pass operation;
Fig. 9 is a unit by-pass governing flow chart;
Figure 10 is a master control system bypass logical flow chart.
Embodiment
Unit bypass sequential has been described among Fig. 1, master control system bypass sequential has been described among Fig. 2.By-pass governing method of the present invention is exactly according to above-mentioned two sequential charts, cooperates by unit and the two-part sequential of master control system and realizes.Be specifically described below in conjunction with Fig. 1 and Fig. 2.
Carry out information interaction according to the sequential logic of stipulating among Fig. 1, Fig. 2 between unit and the master control system, time point t0, t1 among two figure, t2, t3, t4, tk are corresponding mutually, and each time point carries out corresponding event according to following description to be handled.
Each time point and event handling are explained as follows:
T0. fault-signal is received in the unit, and time-delay τ 1 does not report any fault message during this period
T1. expire after the τ 1, fault still exists, and this unit reports fault type and carries out following different processing:
The unit latches fault type also reports master control system, turn-offs 4 power switch pipe IGBT simultaneously; This unit begins τ 2 time-delays simultaneously, waits for the bypass approval of master control system to this unit.
T2. expire after τ 2 time-delays, judge that the bypass that this moment master control system is sent allows whether control signal is " 1 ":
If it be " 0 " (be considered as master control system and do not allow this unit bypass) that this bypass constantly allows control signal, the unit continues latch fault encodes, and to keep 4 power switch pipe IGBT be off state.
If it is " 1 " (being considered as the approval of master control system to this unit bypass) that this bypass constantly allows control signal, the unit continues the latch fault state and keeps 4 power switch pipe IGBT is off state, simultaneously send bypass drive signal (SCR trigger pulse string) to bypass resistance, and begin new time-delay τ 3, wait for that the bypass that bypass success detection module sends becomes function signal.Bypass success detection module is that low level shows the bypass success by detecting bypass controllable silicon both end voltage output unit bypass state, detecting voltage, and voltage is that high level shows the bypass failure.
T3. expire τ 3 time-delays and wait for, judge whether bypass is successful:
Become function signal if receive the bypass that bypass resistance sends, will report the fault type code conversion of master control system by the bypass Logic control module is that bypass is successfully encoded, and latchs the bypass success status, and keeping 4 power switch pipe IGBT simultaneously is off state.
Silicon controlled trigger signal if do not receive that bypass becomes function signal, stops SCR trigger pulse after sending out τ 3 full, continues the latch fault coding, and to keep 4 power switch pipe IGBT be off state.
T4. after the unit bypass detected and finishes, master control system was carried out bypass and is successfully detected, if system's bypass success, then system continues to move according to the bypass mode, otherwise the unit carries out fault alarm to master control system, and shutdown was handled after master control system received fault-signal.
Tk. after the success of system's bypass, the unit is seen by fault sampling coding module monitor unit by-pass operation state and is kept the bypass success whether always.The voltage condition that this module detects bypass controllable silicon two ends judges whether the bypass success, is the bypass success if remain low level always, the bypass failure if voltage becomes high level.The bypass unit cancellation by-pass operation of failing then appears in any time tk, recovers fault alarm, and 4 power switch pipe IGBT are off state.
After master control system was shut down, bypass allowed control signal to become low level, and trouble unit is a malfunction coding with bypass success code conversion immediately, continues simultaneously to trigger controllable silicon, makes it keep conducting state; The normal cell orderly closedown, stop element output.
What Fig. 3 provided is the system configuration schematic diagram of inverter of the present invention, wherein:
The whole n level circuit structure that adopts of inverter, transformer is input as three-phase, is output as 3n and isolates three phase windings, receive 3n unit input side, n unit output series connection forms a phase, constitutes A, B, C three phase windings altogether, three winding neutral points are exported three-phase and are connected to three phase electric machine altogether.
Transformer 1 adopts the phase shifting transformer structure, the 60 °/n of each secondary winding phase phasic difference in the output winding on the homophase, and each is exported winding and is connected to each unit main circuit 2.Its corresponding relation connects the A1 unit according to the order A1 winding that indicates among Fig. 3, and the B1 winding connects the B1 unit, and the C1 winding connects the C1 unit ... the An winding connects the An unit, and the Bn winding connects the Bn unit, and the Cn winding connects the Cn unit.
Unit main circuit 2 is for adopting the main circuit of bypass mode, three-phase bridge rectification circuit work output DC bus-bar voltage when normally moving, four IGBT high-power switch tube work output PWM waveforms, bypass controllable silicon conducting realization by-pass operation during cell failure.The control signal of unit main circuit 2 receiving element control system 3 realizes the operation control and the fault detect of unit.Unit output is linked in sequence according to shown in Fig. 3, A, B, C be every to go up n the unit output synthetic new phase voltage that joins end to end mutually, one end of three-phase is joined together to form neutral point, and other three ends constitute new three-phase alternating current potential source and are connected to motor 5, with drive motors.Each unit main circuit output PWM waveform during normal the operation, the stack of n level forms the many level PWM outputs of multipleization, and harmonic content is less than 2%.The structure of unit main circuit as shown in Figure 4.
The control signal that unit control system 3 receives from master control system 4 is carried out logic synthesis and is handled back output PWM drive signal to unit main circuit 2, realizes normally operation.The fault-signal fault that receives from unit main circuit 2 when fault is arranged reports to master control system 4, and shuts down, moves processing according to the requirement of master control system.Unit control system 3 has initiatively bypass function, and after breaking down, initiatively to master control system 4 application by-pass operations, output bypass drive signal is to unit main circuit 2 behind the confirmation request, and the unit enters by-pass operation, as not granted, then report to the police and shuts down.Communicate by optical fiber telecommunications line A1COM, B1COM, C1COM...AnCOM, BnCOM, CnCOM among Fig. 3 between unit and the master control system 4, be used for transfer control signal and fault message, full duplex mode is adopted in communication.The structure of unit control system 3 as shown in Figure 5.
Master control system 4 is exported multistage multiple chemical control system signal to the unit according to software logic, realizes the normal operation of pulse-width modulation PWM; When fault was arranged, the fault that receiving element control system 3 is sent was carried out bypass judgement, by-pass operation calculating, by-pass operation supervision, bypass failure and is shut down processing.The structure of master control system 4 as shown in Figure 6.
Motor 5 is general asynchronous or synchronous machines, and the three-phase out-put supply after the stack of inverter plural serial stage is adopted in power supply.
Provide the schematic diagram of unit main circuit 2 among Fig. 3 among Fig. 4.Dz1～Dz6 is the three phase full wave rectification bridge among Fig. 4; C1 is a bus capacitor; Z1, Z2, Z3, Z4 are main power device IGBT; D1, D2, D3, D4 are the inverse parallel diode; Da, Db, Dc, Dd are by-pass diode, and X1 is the bypass controllable silicon; BPCTRL is the bypass triggering signal.
During normal operation in the circuit Dz1～Dz6 and capacitor C 1 form a three-phase bridge rectification circuit, output dc voltage; Z1, Z2, Z3, Z4, D1, D2, D3, D4 realize unit PWM output according to different on-off modes; During by-pass operation, realize the unit by-pass operation by Da, Db, Dc, Dd, X1, because the X1 conducting, this unit output is equivalent to short-circuit condition.
The mode that switching tube cooperates during bypass is as follows:
After detecting cell failure, disconnect four main power device IGBT Z1, Z2, Z3, Z4 in the main circuit;
X1 sends out Continuity signal to the bypass controllable silicon, the bypass resistance conducting; The unit enters bypass state; Among Fig. 4, during BPCTRL=0, not conducting of bypass controllable silicon X1, during BPCTRL=1, bypass controllable silicon X1 conducting, the unit enters the by-pass operation state;
Whether the unit detects bypass by the sampling of the fault among Fig. 5 coding module 53 successful: the bypass success then enters bypass state, reports bypass to become function signal to mainboard; Bypass signal BPCTRL is then blocked in the bypass failure immediately, and bypass controllable silicon X1 disconnects, and the unit is to the master control system fault alarm;
Unit controls circuit monitors by-pass operation state.Any time the bypass failure occurs and blocks bypass signal BPCTRL immediately, makes bypass controllable silicon X1 disconnect, and the unit is to the master control system fault alarm.
What Fig. 5 provided is the structural representation of unit control system 3 among Fig. 3.Adopt special-purpose integrated circuit to realize functions such as optical fiber communication encoding and decoding, fault sampling coding, bypass logic control, driving pulse generation among the present invention.Comprise above each functional module of enumerating in this circuit.
Fault sampling coding module 53 is used for the fault-signal of receiving element main circuit, gives bypass Logic control module 51 behind the coding;
Bypass Logic control module 51 is delayed time to the malfunction coding signal that receives under fault case, latch fault during fault, initiatively reports master control system and apply for that bypass handles.Bypass permission/the inhibit signal of sending here according to master control system forms IGBT and silicon controlled drive signal again.Module is carried out the also by-pass operation of monitoring means main circuit, and failure is dealt with and reported master control system to bypass.Under normal state, receive the control signal that the optical fiber communication coding/decoding module is sent here, pwm control signal is carried out logical process, form final IGBT drive signal.After the module completion logic is comprehensive IGBT and silicon controlled triggering signal are delivered to driving pulse generation module 54.
The next optical fiber communication coding/decoding module 52, be used for adopting between this unit and the master control system full duplex serial communication mode to carry out information interaction, adopt special-purpose communication protocol to shake hands and to be sent to master control system behind the location mode coding, and deliver to bypass Logic control module 51 behind the unit controls information decoding that master control system is sent here.
Driving pulse generation module 54 is converted into actual drive signal with the device control signal that receives, and gives the unit each element, realizes normal operation and by-pass operation controlled function.
Fig. 6 is the schematic diagram of master control system 4 among Fig. 3.Master control system comprises master control hardware system and main control software system.Wherein the master control hardware system comprises CPU module 61, PWM logic processing module 62, upper optical fiber communication coding/decoding module 63, I/O interface module 64, power module 65.CPU module 61 realizes calculating and logic judging function; PWM logic processing module 62 realizes output PWM voltage waveform logical process; The bidirectional serial communication function that upper optical fiber communication coding/decoding module 63 is realized between master control system and the unit; I/O interface module 64 is realized the interface of inverter and external user system; Power module 65 is used for the master control system power supply.
Main control software system 66 is the application software of inverter, realizes the various functions of inverter.Comprise the by-pass governing function that realizes inverter in the present invention.
Master control hardware system and main control software system match among the present invention, adopt total digitalization and software approach to realize that the PWM waveform calculates and logic judging function.
Fig. 7 is unit output voltage waveforms when normally moving, and inverter circuit work in unit when normally moving is output as the PWM waveform.
Output voltage waveforms when Fig. 8 is the unit by-pass operation; During by-pass operation, unit bypass resistance work, the unit during by bypass output be equivalent to short-circuit condition.
Fig. 9 is a by-pass governing flow chart in unit of the present invention.This flow process is used for the by-pass governing logic that realizes that Fig. 1 designs.
The first step: all kinds of faults of electrical clean-up on the unit, the unit operate as normal also monitors all kinds of faults;
Second step: the unit receives fault alarm, time-delay τ 1, if fault disappearance circulation monitor unit fault, fault does not disappear and carried out for the 3rd step;
The 3rd step: the latch units fault, and report fault type to master control system; After close IGBT, beginning τ 2 time-delay.Judge whether master control system allows the unit by-pass operation after delaying time, allow then to send the bypass drive output signal and make the unit enter the by-pass operation state, and beginning τ 3 time-delays; Then carry out fault alarm to master control system immediately when not allowing by-pass operation, and wait for and shutting down;
In the 4th step, whether by-pass operation time-delay τ 3 is successful to back judging unit bypass, changes the cell failure coding into bypass during the bypass success and successfully encodes, and latchs this coding and reports master control system, and monitor unit bypass state then circulates; The bypass failure is then carried out fault alarm to master control system immediately, waits for and shutting down.
Figure 10 is a master control system bypass logical flow chart of the present invention.This flow process is used for the master control system bypass sequential that realizes that Fig. 2 designs.
The first step: master control system powers on and normally moves, and monitors running status and all kinds of fault;
Second step: after master control system received fault-signal, time-delay τ 4 carried out for the 3rd step if fault still exists, and fault disappears then to the fault supervision that circulates;
The 3rd step: read failure Coded Analysis fault type, send bypass to the unit and allow signal, calculate the by-pass operation parameter, calculate and export the pwm pulse of bypass mode by the bypass mode, carried out for the 4th step behind the time-delay τ k;
The 4th step: detection system bypass state after by-pass operation is delayed time, whether bypass is successful to judge system.Continue by-pass operation, continuous monitoring bypass state during the bypass success; Bypass failure receives fault-signal immediately and reports to the police to shut down and handle.
Claims (10)
1, a kind of middle pressure inverter with unit active bypass function comprises main transformer, and the master control system by main control software system and master control hardware system constitute is characterized in that, also comprises:
The inverter unit main circuit, be connected on the secondary winding of main transformer, it comprises a three-phase bridge rectification circuit, a single-phase full bridge inverter circuit and a bypass resistance, by receiving power device control signal switching time of described unit control system output, the output pulse width modulation signal is given load motor, when breaking down, the by-pass governing signal that the receiving element control system is sent initiatively falls this main circuit bypass;
Unit control system carries out fault sampling and sorting code number by cell failure reception and detection module; Fit into row operation and logic control by main control software and unit controls logic module, control signal and the by-pass governing signal of output power controlling devices switch time.
2, the middle inverter of pressing according to claim 1 is characterized in that described unit control system comprises:
Fault sampling coding module receives, classifies, encodes, reports cell failure;
The bypass Logic control module according to the locking signal of master control system, is carried out the drive controlling to power switch pipe IGBT and controllable silicon SCR; Initiatively handle to master control system application bypass, the permission bypass command that sends to the unit according to master control system is carried out the also by-pass operation state of monitoring means main circuit, and failure is dealt with and reported master control system to bypass;
The next optical fiber communication coding/decoding module, be used for adopting between this unit and the master control system full duplex serial communication mode to carry out information interaction, adopt special-purpose communication protocol to shake hands and to be sent to master control system behind the location mode coding, and deliver to the bypass Logic control module behind the unit controls information decoding that master control system is sent here.
3, the middle inverter of pressing according to claim 1 and 2 is characterized in that described inverter unit main circuit comprises:
The three-phase bridge rectification circuit of forming by Dz1～Dz6 and C1; Be connected on the inversion full-bridge circuit of forming by high-power switch tube Z1, Z2, Z3, Z4 thereafter; The bypass full-bridge circuit of forming by by-pass diode Da, Db, Dc, Dd; The output of inversion full-bridge circuit is connected with the input of bypass full-bridge circuit; On two arms of described bypass full-bridge circuit, bypass controllable silicon X1 also in parallel; High-power switch tube Z1, Z2, Z3, Z4 receive and carry out normal pulse-width modulation from the drive control signal of described unit control system, the control end of bypass controllable silicon X1 receives the by-pass governing signal, so that the output of the inverter unit main circuit that breaks down is by bypass.
4, the middle inverter of pressing according to claim 1 and 2 is characterized in that described master control hardware system comprises CPU module, PWM logic processing module, upper optical fiber communication coding/decoding module, I/O interface module, power module; The CPU module matches with the PWM logic processing module, realizes that the PWM waveform calculates and logic judging function; The PWM logic processing module realizes output PWM voltage waveform logical process; Upper optical fiber communication coding/decoding module is realized the bidirectional serial communication function between master control system and the unit; The I/O interface module is used for the interface of inverter and external user system; Power module is used to the master control system power supply; Master control hardware system and main control software system match, and adopt total digitalization and software approach to realize that the PWM waveform calculates and logic judging function.
5, a kind of middle unit active by-pass governing method of pressing inverter is characterized in that, comprises the steps:
The first step, the fault of unit control system sampling coding module detect and are reported to the bypass Logic control module after fault takes place, carry out filtering wave by prolonging time and failure modes after, fault is initiatively reported master control system;
Second step after master control system receives the fault-signal that reports, judged whether to carry out bypass and handles, if then bypass is allowed signal to send to unit control system by the optical fiber communication mode, otherwise send the bypass inhibit signal;
In the 3rd step, whether master control system successfully detects bypass, if the bypass success continues to keep the by-pass operation state, if bypass is unsuccessful, carries out for the 4th step;
In the 4th step, block the output of unit control system and send out failure alarm signal to master control system.
6, active by-pass governing method in unit according to claim 5, it is characterized in that, after unit control system receives bypass permission/inhibit signal, control signal is delivered to the bypass Logic control module, send the by-pass governing signal by the bypass Logic control module to the driving pulse generation module when allowing by-pass operation, the bypass controllable silicon in the driver element main circuit is realized the unit by-pass operation; When forbidding bypass, block the output of unit control system and send out failure alarm signal to master control system.
7, according to claim 5 or 6 described unit active by-pass governing methods, it is characterized in that, also comprise, after the bypass success, master control system monitors the operation of bypass state, if bypass failure in unit is blocked the output of unit control system and sent out failure alarm signal to master control system.
8, according to claim 5 or 6 described unit by-pass governing methods initiatively, it is characterized in that system allows the number and the mode of trouble unit to preestablish, when breaking down more than the unit that allows number in the system, handle according to the bypass failure.
9, according to claim 5 or 6 described unit active by-pass governing methods, it is characterized in that, after by-pass operation, adopt totally digitilized software approach that output PWM waveform is handled, output voltage amplitude adopts automatic method for improving, the output voltage phase place adopts directly computational methods continuously, realizes the continuous of output voltage amplitude and phase place.
10, active by-pass governing method in unit according to claim 9 is characterized in that, in the time can't realizing that amplitude is consistent fully continuously, output voltage amplitude adopts greatest limit lifting computational methods.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097925A (en) * | 2010-12-21 | 2011-06-15 | 国电南京自动化股份有限公司 | Concatenated high voltage frequency converter bypassing processing method |
| CN102263489B (en) * | 2006-08-22 | 2013-04-10 | 株式会社日立制作所 | Electric power switching device and its abnormal test method |
| CN112394713A (en) * | 2021-01-20 | 2021-02-23 | 杭州飞仕得科技有限公司 | Fault classification method and fault classification system |
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2003
- 2003-05-08 CN CNA031287417A patent/CN1549436A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263489B (en) * | 2006-08-22 | 2013-04-10 | 株式会社日立制作所 | Electric power switching device and its abnormal test method |
| CN102097925A (en) * | 2010-12-21 | 2011-06-15 | 国电南京自动化股份有限公司 | Concatenated high voltage frequency converter bypassing processing method |
| CN102097925B (en) * | 2010-12-21 | 2013-04-10 | 国电南京自动化股份有限公司 | Concatenated high voltage frequency converter bypassing processing method |
| CN112394713A (en) * | 2021-01-20 | 2021-02-23 | 杭州飞仕得科技有限公司 | Fault classification method and fault classification system |
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