CN1549327A - Bit line forming method - Google Patents
Bit line forming method Download PDFInfo
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- CN1549327A CN1549327A CNA031365507A CN03136550A CN1549327A CN 1549327 A CN1549327 A CN 1549327A CN A031365507 A CNA031365507 A CN A031365507A CN 03136550 A CN03136550 A CN 03136550A CN 1549327 A CN1549327 A CN 1549327A
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Abstract
The method for forming bit line includes the following steps: firstly, providing a semiconductor substrate on which a transistor is formed, said transistor has gate, source and drain region, forming first dielectric layer with contact window on the semiconductor substrate, said contact window exposes the surface of source drain region, forming a conductive layer in contact window, and back etching the first dielectric layer to that the top surface of the first dielectric layer is a certain distance lower than top surface of the conductive layer, then oxidating conductive layer whose surface is exposed to form an oxide layer on the conductive layer, removing oxide layer to form a conductive layer whose top width is reduced, and forming second dielectric layer on conductive layer and first dielectric layer, etching second dielectric layer to expose conductive layer and form several bit line grooves, and forming bit line in bit line groove.
Description
Technical field
The invention relates to a kind of formation method of bit line, particularly relevant for a kind of by the formation method of the top width that reduces bit line contact with the bit line that reduces the short circuit probability.
Background technology
In recent years, in the design of semiconductor circuit, the status of capacitor is increasingly important, and has become a no interchangeable circuit unit.For example be extensive use of DRAM (Dynamic Random Access Memory) (DRAM:dynamic random access memory), oscillator (oscillator), time delay circuit (time delay circuitry), analog/digital or digital/analog converter (AD/DA converter) and many other application circuits of capacitor at present.Therefore, a kind of stacking-type electric capacity (STC:stacked capacitor cell) or groove type capacitance (trenched capacitor cell) are being developed in the storage device closely, it utilizes the superjacent air space of access device in the Silicon Wafer or substrate below to form capacitive electrode plates, the advantage of this kind structure is to have low soft error note rate (SER:soft error rate), and can be in conjunction with the insulating barrier of tool high-k (high dielectricconstant); Simultaneously, need between memory cell and bit line be connected with contact hole.
As Fig. 1 a to Fig. 1 c, Fig. 2 and shown in Figure 3, Fig. 1 a shows the known schematic diagram that is formed with the transistorized semiconductor-based end, Fig. 1 b to Fig. 1 c is the schematic diagram of formation method of known bit line of the AA tangent plane of displayed map 1a, Fig. 2 is the schematic diagram that shows known bit line aligning mistake, and Fig. 3 is the perspective view of displayed map 2.
As shown in Figure 1a, at first, semiconductor substrate 101 is provided, be formed with a brake-pole dielectric layer 102 in regular turn at semiconductor-based the end 101, be formed with a gate 103 and a curtain layer of hard hood 104 on the brake-pole dielectric layer 102, and be formed with a clearance wall 105 at the sidewall of said modules, thus, promptly form a gate module.
Then, on the semiconductor-based end 101 that is formed with said modules, form a dielectric layer 106 and and have the patterning photoresist layer (not shown) of opening, the surface of opening meeting exposed portions serve dielectric layer 106.Then, be etch mask with the patterning photoresist layer, etching dielectric layer 106 is till expose gate module, to form an opening 107 at dielectric layer 106.
Shown in Fig. 1 b, Fig. 1 b is the AA sectional drawing of Fig. 1 a.
Shown in Fig. 1 c, on dielectric layer 106, form a polysilicon layer, and polysilicon layer is carried out the etch-back step staying the polysilicon layer 108 in the opening 107, and the polysilicon layer 108 both take the altitude of surface one that need be lower than dielectric layer 106; Wherein, polysilicon layer 108 is bit line contact (CB).
Then, on dielectric layer 106, form one and have the patterning photoresist layer (not shown) of opening, the surface that opening can exposed portions serve dielectric layer 106, and be etch mask with the patterning photoresist layer, etching dielectric layer 106 to the one set degree of depth are to form groove at dielectric layer 106; Next, after the patterning photoresist layer removed, form a barrier layer and a tungsten metal level in regular turn on dielectric layer 106, the tungsten metal level can fill up groove and opening 107.Then, the semiconductor substrate is carried out cmp to stay barrier layer 109 and tungsten metal level 110a, the 110b in the groove; Wherein, tungsten metal level 110a, 110b are bit line (MO).
Owing to be established on the same plane with tungsten metal level 110a, 110b as the bit line as the polysilicon layer 108 of bit line contact, and both positions are quite approaching, therefore once aligning mistake (mis-align), will be easily on the processing procedure of bit line and bit line contact because too near and be affected, and may cause short circuit, shown in the dotted line 111 of Fig. 2 and Fig. 3.
Summary of the invention
The object of the present invention is to provide a kind of formation method of bit line, mainly is to carry out oxidation step so that the top width of bit line contact reduces by the bit line is contacted, effectively to be reduced in the probability of mistake to punctual and other bit line short circuit.
According to above-mentioned purpose, the invention provides a kind of formation method of bit line, comprise the following steps: to provide the semiconductor substrate, be formed with a transistor at semiconductor-based the end, transistor has a gate and a source drain area; Form one first dielectric layer on the semiconductor-based end, first dielectric layer has contact hole, and contact hole exposes the surface of source drain area; Form a conductive layer in contact hole, conductive layer fills up contact hole; First dielectric layer is carried out the etch-back step, so that the top surface of first dielectric layer is lower than both set a distances of conductive layer top surface one; Conductive layer to exposing surface carries out oxidation step, to form an oxide layer at conductive layer; Remove oxide layer, form the conductive layer that a top width is dwindled; Form one second dielectric layer on the conductive layer and first dielectric layer, etching second dielectric layer is to exposing conductive layer, to form a plurality of bit line trenches; Reach and in the bit line trenches, form a bit line.
According to above-mentioned purpose, the present invention provides a kind of formation method of bit line again, comprises the following steps: to provide the semiconductor substrate, is formed with a transistor at semiconductor-based the end, and transistor has a gate and a source drain area; Form one first dielectric layer and one first patterning cover curtain layer on the semiconductor-based end in regular turn, the first patterning cover curtain layer has one first opening, and first opening exposes the part surface of first dielectric layer; With the first patterning cover curtain layer is etch mask, anisotropic etching first dielectric layer to the surface of exposing the source drain area to form a contact hole; Remove the first patterning photoresist layer; On first dielectric layer, form a conductive layer, and conductive layer fills up contact hole; Conductive layer is carried out planarisation step to exposing first dielectric layer; First dielectric layer is carried out the etch-back step, be lower than the top surface of conductive layer to the top surface of first dielectric layer; Conductive layer is carried out oxidation step, so that an oxide layer is formed at the top of conductive layer; Remove oxide layer; Form one second dielectric layer and one second patterning cover curtain layer on first dielectric layer and conductive layer in regular turn, the second patterning cover curtain layer has plural opening; With the second patterning cover curtain layer is etch mask, and anisotropic etching second dielectric layer is to exposing conductive layer to form plural groove, and wherein groove is the bit line trenches; Remove the second patterning cover curtain layer; Compliance forms a barrier layer and a metal level on second dielectric layer and conductive layer in regular turn, and metal level fills up plural groove; And planarization metal layer and barrier layer are to exposing second dielectric layer in regular turn, and to stay the metal level in the plural groove, wherein metal level is the bit line.
Description of drawings
Fig. 1 a shows the known schematic diagram that is formed with the transistorized semiconductor-based end;
Fig. 1 b to Fig. 1 c is the schematic diagram of formation method of known bit line of the AA tangent plane of displayed map 1a;
Fig. 2 is the schematic diagram that shows known bit line aligning mistake;
Fig. 3 is the perspective view of displayed map 2;
Fig. 4 a shows the schematic diagram that is formed with the transistorized semiconductor-based end of the present invention;
Fig. 4 b to Fig. 4 j is the schematic diagram of formation method of bit line of the present invention of the AA tangent plane of displayed map 4a;
Fig. 5 is the schematic diagram that shows bit line aligning mistake of the present invention;
Fig. 6 is the perspective view of displayed map 5.
Symbol description:
101, the semiconductor-based end of 201-
102,202-brake-pole dielectric layer
103,203-gate
104,204-curtain layer of hard hood
105,205-clearance wall
106,206,206a-dielectric layer
107,207,211-opening
The 108-polysilicon layer
109,215-barrier layer
110a, 110b-tungsten metal level
111,214-dotted line
208,208a-conductive layer
The 208b-oxide layer
The 209-dielectric layer
The 210-cover curtain layer
212-bit line trenches
213,213a-metal level
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
As Fig. 4 a to Fig. 4 i, Fig. 5 and shown in Figure 6, Fig. 4 a shows the schematic diagram that is formed with the transistorized semiconductor-based end of the present invention, Fig. 4 b to Fig. 4 j is the schematic diagram of formation method of bit line of the present invention of the AA tangent plane of displayed map 4a, Fig. 5 is the schematic diagram that shows bit line aligning mistake of the present invention, and Fig. 6 is the perspective view of displayed map 5.
Shown in Fig. 4 a, at first, semiconductor substrate 201 is provided, be formed with a brake-pole dielectric layer 202 in regular turn at semiconductor-based the end 201, be formed with a gate 203 and a curtain layer of hard hood 204 on the brake-pole dielectric layer 202, and be formed with a clearance wall 205 at the sidewall of said modules, thus, promptly form a gate module.Then, forming a dielectric layer 206 and and have the patterning cover curtain layer (not shown) of opening on the semiconductor-based end 201 that is formed with said modules, for example is photoresist layer, the surface of opening meeting exposed portions serve dielectric layer 206.Then, be etch mask with the patterning cover curtain layer, etching dielectric layer 206 is till expose gate module, to form an opening 207 at dielectric layer 206; Then, the patterning cover curtain layer is removed.Wherein, the semiconductor-based end 201 for example is a silicon base; Brake-pole dielectric layer 202 for example is a gate pole oxidation layer; Gate 203 for example is a polysilicon layer; Curtain layer of hard hood 204 for example is a nitration case; Clearance wall 205 for example is a nitration case; Dielectric layer 206 for example is an oxide layer.
Shown in Fig. 4 b to Fig. 4 j, Fig. 4 b to Fig. 4 j is the present invention forms the bit line on the AA of Fig. 4 a sectional drawing a schematic diagram.
Shown in Fig. 4 c, on dielectric layer 206, form a conductive layer, conductive layer can fill up opening 207.Then, conductive layer is carried out planarisation step till the surface of exposing dielectric layer 206, to stay conductive layer 208 in opening 207, conductive layer 208 is bit line contact (CB).Wherein, planarisation step for example is cmp (chemical mechanical polishing); Conductive layer 208 for example is polysilicon (polysilicon) layer or crystal silicon of heap of stone (epi-silicon) layer.
Shown in Fig. 4 d, dielectric layer 206 is carried out etch-back (etch back) step, to form dielectric layer 206a, the surface one that the surface of dielectric layer 206a is lower than conductive layer 208 is set a distance both, this both set a distance can decide as required, the surface that conductive layer 208 exposes is big more, and then follow-up part oxidized when carrying out oxidation step is just many more, and what last bit line was separated by also can be far away more.
Next, carry out a characterization step of the present invention.
Shown in Fig. 4 e, the conductive layer 208 of exposing surface is carried out oxidation step, to form oxide layer 208b and unoxidized conductive layer 208a.Wherein, oxidation step for example is thermal oxidation method (thermaloxidation); Oxide layer 208b for example is a silicon oxide layer.
Then, 208b removes with oxide layer, to stay the conductive layer 208a that top width reduces, shown in Fig. 4 f.
Shown in Fig. 4 g, then, on the surface of conductive layer 208a and dielectric layer 206a, form the cover curtain layer 210 of a dielectric layer 209 and a bit line pattern in regular turn, cover curtain layer 210 has opening 211, the surface of opening 211 exposed portions serve dielectric layers 209.Wherein, dielectric layer 209 for example is an oxide layer; Cover curtain layer 210 for example is the patterning photoresist layer.
Shown in Fig. 4 h, be etch mask with cover curtain layer 210, dielectric layer 209 is carried out anisotropic etching (anisotropical etching) to exposing conductive layer 208a, to form bit line trenches 212 in dielectric layer 209; Then, cover curtain layer 210 is removed.Wherein, anisotropic etching for example is reactive ion etching (reactive ion etching) or electric paste etching (plasmaetching).
Because the height after the dielectric layer 206a process etch-back step is lower than the top surface of conductive layer 208a, so dielectric layer 209 is being carried out anisotropic etching to exposing conductive layer 208a when forming bit line trenches 212, except with bit line trenches 212 that conductive layer 208a communicates, remaining bit line trenches 212 all has a both set a distance with the bottom of dielectric layer 209.
Shown in Fig. 4 i, compliance forms a barrier layer 215 and a metal level 213 in regular turn on dielectric layer 209, and metal level 213 can fill up bit line trenches 212.Wherein, barrier layer 215 for example is titanium/titanium nitride (Ti/TiN) layer; Metal level 213 for example is tungsten (W) metal level.
Then, metal level 213 is carried out planarisation step till the surface of exposing dielectric layer 209, to stay the metal level 213a in the groove, metal level 213a is the bit line; And be positioned at the conductive layer 208a that the metal level 213a meeting conducting on the conductive layer 208a contacts as the bit line, shown in Fig. 4 j.Wherein, planarisation step for example is cmp (chemical mechanicalpolishing).
Be built on the different planes with metal level 213a as the conductive layer 208a of bit line contact because the present invention is formed as the bit line, and reduce the top dimension of conductive layer 208a, the size of metal level 213a also can be lowered, cause the distance between conductive layer 208a and other metal level 213a to be elongated.Therefore, if the situation of aligning mistake (mis-align) takes place, on the processing procedure of bit line and the contact of bit line with regard to not can because of too near and be affected, the situation that can effectively reduce short circuit takes place, shown in the dotted line 214 of Fig. 5 and Fig. 6.
Provided by the present invention by oxidation bit line contact with the top dimension that reduces the contact of bit line to reduce the method for bit linear dimension, can keep the distance between contact of bit line and other bit line, the situation that effectively reduces short circuit takes place, and then improves the reliability of product.
Claims (17)
1. the formation method of a bit line comprises the following steps:
The semiconductor substrate is provided, is formed with a transistor on this semiconductor-based end, this transistor has a gate and a source drain area;
Form one first dielectric layer on this semiconductor-based end, this first dielectric layer has contact hole, and this contact hole exposes the surface of this source drain area;
Form a conductive layer in this contact hole, this conductive layer fills up this contact hole;
This first dielectric layer is carried out the etch-back step, so that the top surface of this first dielectric layer is lower than both set a distances of this conductive layer top surface one;
This conductive layer to exposing surface carries out oxidation step, to form an oxide layer at this conductive layer;
Remove this oxide layer, form the conductive layer that a top width is dwindled;
Form one second dielectric layer on this conductive layer and this first dielectric layer, this second dielectric layer of etching is to exposing this conductive layer, to form a plurality of bit line trenches; And
In this bit line trenches, form a bit line.
2. the formation method of bit line according to claim 1, wherein this first dielectric layer is an oxide layer.
3. the formation method of bit line according to claim 1, wherein this conductive layer is polysilicon layer or crystal silicon layer of heap of stone.
4. the formation method of bit line according to claim 1, wherein this oxidation step is a thermal oxidation method.
5. the formation method of bit line according to claim 1, wherein this oxide layer is a silicon oxide layer.
6. the formation method of bit line according to claim 1, wherein this second dielectric layer is an oxide layer.
7. the formation method of bit line according to claim 1, wherein this bit line is the tungsten metal level.
8. the formation method of a bit line comprises the following steps:
The semiconductor substrate is provided, is formed with a transistor on this semiconductor-based end, this transistor has a gate and a source drain area;
Form one first dielectric layer and one first patterning cover curtain layer on this semiconductor-based end in regular turn, this first patterning cover curtain layer has one first opening, and this first opening exposes the part surface of this first dielectric layer;
With this first patterning cover curtain layer is etch mask, this first dielectric layer of anisotropic etching to the surface of exposing this source drain area to form a contact hole;
Remove this first patterning photoresist layer;
On this first dielectric layer, form a conductive layer, and this conductive layer fills up this contact hole;
This conductive layer is carried out planarisation step to exposing this first dielectric layer;
This first dielectric layer is carried out the etch-back step, be lower than the top surface of this conductive layer to the top surface of this first dielectric layer;
This conductive layer is carried out oxidation step, so that an oxide layer is formed at the top of this conductive layer;
Remove this oxide layer;
Form one second dielectric layer and one second patterning cover curtain layer on this first dielectric layer and this conductive layer in regular turn, this second patterning cover curtain layer has plural opening;
With this second patterning cover curtain layer is etch mask, and this second dielectric layer of anisotropic etching is to exposing this conductive layer to form plural groove, and wherein this groove is the bit line trenches;
Remove this second patterning cover curtain layer;
Compliance forms a barrier layer and a metal level on this second dielectric layer and this conductive layer in regular turn, and this metal level fills up this plural number groove; And
This metal level of planarization in regular turn and this barrier layer are to exposing this second dielectric layer, and to stay this metal level in this plural number groove, wherein this metal level is the bit line.
9. the formation method of bit line according to claim 8, wherein this first dielectric layer is an oxide layer.
10. the formation method of bit line according to claim 8, wherein this anisotropic etching is reactive ion etching or electric paste etching.
11. the formation method of bit line according to claim 8, wherein this conductive layer is polysilicon layer or crystal silicon layer of heap of stone.
12. the formation method of bit line according to claim 8, wherein this oxidation step is a thermal oxidation method.
13. the formation method of bit line according to claim 8, wherein this oxide layer is a silicon oxide layer.
14. the formation method of bit line according to claim 8, wherein this second dielectric layer is an oxide layer.
15. the formation method of bit line according to claim 8, wherein barrier layer is titanium/titanium nitride layer.
16. the formation method of bit line according to claim 8, wherein this metal level is the tungsten metal level.
17. the formation method of bit line according to claim 8, wherein this planarisation step is the cmp step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03136550 CN1275314C (en) | 2003-05-23 | 2003-05-23 | Bit line forming method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03136550 CN1275314C (en) | 2003-05-23 | 2003-05-23 | Bit line forming method |
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| Publication Number | Publication Date |
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| CN1549327A true CN1549327A (en) | 2004-11-24 |
| CN1275314C CN1275314C (en) | 2006-09-13 |
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| CN 03136550 Expired - Lifetime CN1275314C (en) | 2003-05-23 | 2003-05-23 | Bit line forming method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582373A (en) * | 2019-09-27 | 2021-03-30 | 南亚科技股份有限公司 | Semiconductor element with air gap and preparation method thereof |
| CN112786596A (en) * | 2019-11-08 | 2021-05-11 | 南亚科技股份有限公司 | Semiconductor element with epitaxial structure and forming method thereof |
| CN115148674A (en) * | 2021-03-30 | 2022-10-04 | 长鑫存储技术有限公司 | Method for manufacturing memory |
-
2003
- 2003-05-23 CN CN 03136550 patent/CN1275314C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582373A (en) * | 2019-09-27 | 2021-03-30 | 南亚科技股份有限公司 | Semiconductor element with air gap and preparation method thereof |
| CN112786596A (en) * | 2019-11-08 | 2021-05-11 | 南亚科技股份有限公司 | Semiconductor element with epitaxial structure and forming method thereof |
| CN112786596B (en) * | 2019-11-08 | 2024-05-24 | 南亚科技股份有限公司 | Semiconductor element with epitaxial structure and forming method thereof |
| CN115148674A (en) * | 2021-03-30 | 2022-10-04 | 长鑫存储技术有限公司 | Method for manufacturing memory |
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| Publication number | Publication date |
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| CN1275314C (en) | 2006-09-13 |
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Granted publication date: 20060913 |