CN1549273A - Precharge and detecting circuit for differential read-only storage - Google Patents
Precharge and detecting circuit for differential read-only storage Download PDFInfo
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- CN1549273A CN1549273A CNA031234461A CN03123446A CN1549273A CN 1549273 A CN1549273 A CN 1549273A CN A031234461 A CNA031234461 A CN A031234461A CN 03123446 A CN03123446 A CN 03123446A CN 1549273 A CN1549273 A CN 1549273A
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Abstract
The differential ROM pre-charging and detecting circuit has the memory unit connected to the first bit line or the second bit line. The differential ROM pre-charging and detecting circuit includes one pre-charging module connected electrically to the first bit line and the second bit line for pre-charging; one selecting module connected electrically to the first bit line, the second bit line, the first data line and the second data line for transmitting data based on the first control signal; one charge distributing module connected electrically to the first and the second data lines for distributing charge to the first or the second data line based on the first and the second control signals; and one detection module connected electrically to the first and the second data lines for detecting the signal of the first and the second data lines to produce one output signal.
Description
Technical field
The invention provides a kind of precharge and testing circuit, refer in particular to a kind of use in a differential type ROM (read-only memory) (Differential Type ROM) and include precharge and the testing circuit of a charge distributing module (Charge SharingModule).
Background technology
In present various electronic products on the market, storer always is one of wherein very important and indispensable element.Storer can be divided into volatile memory and nonvolatile memory two big classes according to the difference of storage data mode, wherein volatile memory is meant the data storage device that the numerical data that is stored in this storer promptly can be vanished from sight after cutting off the electricity supply, the advantage of volatile memory is that its access speed is fast, be commonly used to as processing unit at a high speed and the impact damper between other circuit, can't continue the preservation data but volatile memory but has under the state of cutting off the electricity supply, for example product such as DRAM, SDRAM all belongs to a kind of of volatile memory.Nonvolatile memory then refers to be stored in the data storage device that the numerical data in this storer still can continue to preserve after cutting off the electricity supply, the advantage of nonvolatile memory is that promptly it can continue to preserve data under the state of cutting off the electricity supply, shortcoming then is that its access speed is generally not quick like volatile memory, then belongs to the category of nonvolatile memory as products such as ROM, flash memories.
The field of memory application is very extensive, except function in general personal computer as data storage device, maturation day by day along with the Information technology industry, above-mentioned storer miscellaneous is all applied in large quantities as mobile computer, personal digital assistant (Personal Digital Assistant, PDA), in the middle of the electronic product of mobile phone, digital camera etc., with instrument as above-mentioned various electronic products storage numerical datas.
In general, the storer that is arranged in the electronic product can carry out following several main operator scheme according to the control signal of this electronic product, promptly writes pattern (Write Mode or Program Mode), elimination pattern (Erase Mode), reaches read mode (Read Mode).Wherein in writing pattern, this electronic product can write numerical data in this storer in the specific memory address according to the indication of above-mentioned control signal; In the elimination pattern, this electronic product can be removed the numerical data of being stored in the specific memory address in this storer according to the indication of above-mentioned control signal; And in read mode, this electronic product then can read out the numerical data of being stored in the specific memory address in this storer according to the indication of above-mentioned control signal.
In the middle of a storer, usually include a testing circuit (Sense Out Circuit or SensingAmplifier), be electrically connected to the memory cell array that is used for storing numerical data in this storer, come out with the data read of specific memory address in this memory cell array being stored according to the indication of control signal.At 2001 IEEE International SOI Conference, 10/01 delivers the structure that promptly discloses a testing circuit in the 143rd～144 page of the file, see also Fig. 1, the circuit diagram of the testing circuit of the differential type ROM (read-only memory) (Differential Type ROM) of expression known technology among Fig. 1.In Fig. 1, this differential type ROM (read-only memory) includes a testing circuit 10 and a memory cell array 20, and wherein memory cell array 20 includes a plurality of memory cells 22, and the address of memory cell 22 is via many word lines (Word Line) WL
1～W
1nAnd many pairs of bit line (BL
11, BL
12)～(BL
M1, BL
M2) define, that is the infall of each bar word line and each pairs of bit line all has a memory cell 22 and is electrically connected to this word line and this pairs of bit line.
In Fig. 1, memory cell 22 is made up of bi-NMOS transistor, before with writing data into memory unit 22, the source grounding of this bi-NMOS transistor, its grid all is electrically connected to this word line, its drain electrode then is electrically connected to wherein one of this pairs of bit line (nmos pass transistor that for example is positioned at the left side in Fig. 1 is electrically connected to the bit line on the left side, and the nmos pass transistor that is positioned at the right then is electrically connected to the bit line on the right) respectively.When desire during with logical data write store unit 22, then must be with being connected to block and (for example blowing between this two MOS transistor and the bit line with laser, be to connect with the representative of X mark to be blocked in Fig. 1), write in this memory cell 22 with the representative data that logical value is different.In the following description, will in memory cell 22, store logical value " 1 " to be blocked interval scale, and in memory cell 22, be stored logical value " 0 " to block interval scale when the connection on the right when the connection on the left side.
Next will be with above-mentioned bit line (BL
11, BL
12)～(BL
M1, BL
M2) in wherein a pair of for example describes, bit line (BL for example
11, BL
12), the first bit line BL
11And the second bit line BL
12Be to be electrically connected to testing circuit 10, testing circuit 10 includes one first pre-charge module 12, is electrically connected to the first bit line BL
11And the second bit line BL
12, be used for to the first bit line BL
11And the second bit line BL
12Carry out precharge; One second pre-charge module 16 is electrically connected to one first data line DL
1And one second data line DL
2, be used for to the first data line DL
1And one second data line DL
2Carry out precharge; One logic module 14 is electrically connected to the first bit line BL
11With the first data line DL
1Between and the second bit line BL
12With the second data line DL
2Between, be used for according to a control signal Y1 the first bit line BL
11Signal be sent to the first data line DL
1And with the second bit line BL
12Signal be sent to the second data line DL
2, with at the first data line DL
1And the second data line DL
2The last output signal that corresponds to the logical data of being stored in this memory cell 22 that produces.
When this storer when carrying out data read, only can choose many pairs of bit line (BL
11, BL
12)～(BL
M1, BL
M2) wherein pair of bit lines, for example above-mentioned bit line (BL
11, BL
12), and correspond to wherein word line (for example above-mentioned word line WL being connected to also only can choose in the middle of a plurality of memory cells 22 of this pairs of bit line
1) memory cell 22 read.Yet, for other bit lines (BL that prevents to be connected to same testing circuit 10 but be not selected
21, BL
22)～(BL
M1, BL
M2) on the leakage current effects (Leakage Current) that produces of memory cell 22 action of reading of testing circuit 10 is made a mistake, in the testing circuit 10 of known technology, select module 14 to be to use high threshold voltage element (High-V
THDevice) bit line and data line are separated, that is to say, in Fig. 1, selecting the bi-NMOS transistor in the module 14 is to have the higher threshold voltage value, in case the problem that the leak-stopping electric current may cause.
But in selecting module 14, use the high threshold voltage element but can produce a very big defective, that is in general the time of high threshold voltage element conductive all comes longly than normal element, this will cause this storer when reading of data, when desire is used control signal Y1 with these high threshold voltage element conductive, need the long running time just can reach this purpose, like this then time for reading (AccessTime) this storer will be subjected to very big influence.
Summary of the invention
Therefore fundamental purpose of the present invention is to provide a kind of precharge and testing circuit that includes a charge distributing module, to solve above-mentioned known problem.
According to claim of the present invention, be precharge and the testing circuit that discloses a kind of differential type ROM (read-only memory), be used for detecting the logical data of being stored in the memory cell of this ROM (read-only memory), this memory cell can be connected to one first bit line or one second bit line, be used to provide this first bit line or this second bit line digital signal, this precharge and testing circuit include a pre-charge module, be electrically connected to this first bit line and this second bit line, be used for this first bit line and this second bit line are carried out precharge; One selects module, be electrically connected to this first bit line, this second bit line, one first data line and one second data line, be used for the signal of this first bit line being sent to this first data line and the signal of this second bit line being sent to this second data line according to one first control signal; One charge distributing module, be electrically connected to this first data line and this second data line, be used for this first data line and this second data line are carried out precharge, and stored charge in this charge distributing module be dispensed to this first data line and this second data line according to one second control signal; And a detection module, be electrically connected to this first data line and this second data line, be used for detecting the signal of this first data line and this second data line to produce an output signal.
The present invention utilizes a pre-charge module and a charge distributing module that this first bit line, this second bit line, one first data line and one second data line all are precharged to ground voltage, the influence of the leakage current effects of the like this then bit line that data read memory cell on the bit line that is selected will can not be subjected to not being selected, and this charge distributing module also can be carried out charge distributing to this first data line and this second data line when reading of data, and then has accelerated the speed that signal on this first data line and this second data line enters steady state (SS).
Description of drawings
Fig. 1 is the synoptic diagram of the testing circuit of known technology.
Fig. 2 is the synoptic diagram of precharge of the present invention and testing circuit.
Fig. 3 is precharge and the sequential chart of testing circuit when reading of data among Fig. 2.
The reference numeral explanation
10 testing circuits
12,16,32 pre-charge modules
14,34 select module
20,40 memory cell arrays
22,42 memory cells
30 precharge and testing circuit
36 charge distributing module
38 detection modules
44,46,48,50,60,62,64,66,68,70,78,80,82,84 nmos pass transistors
52,54 electric capacity
56,58,72,74,76 PMOS transistors
Embodiment
See also Fig. 2, the precharge of expression differential type ROM (read-only memory) of the present invention and the circuit diagram of testing circuit among Fig. 2.In Fig. 2, this differential type ROM (read-only memory) includes a precharge and a testing circuit 30 and a memory cell array 40, wherein memory cell array 40 includes a plurality of memory cells 42, wherein memory cell array 40 is that memory cell array 20 among Fig. 1 with above-mentioned known technology is identical, and the address of memory cell 42 is via many word line WL
1～W
1nAnd many pairs of bit line (BL
11, BL
12)～(BL
M1, BL
M2) define, that is the infall of each bar word line and each pairs of bit line all has a memory cell 42 and is electrically connected to this word line and this pairs of bit line.
In Fig. 2, memory cell 42 is made up of bi-NMOS transistor, before with writing data into memory unit 42, the source grounding of this bi-NMOS transistor, its grid all is electrically connected to this word line, its drain electrode then is electrically connected to wherein one of this pairs of bit line (nmos pass transistor that for example is positioned at the left side in Fig. 1 is electrically connected to the bit line on the left side, and the nmos pass transistor that is positioned at the right then is electrically connected to the bit line on the right) respectively.When desire during with logical data write store unit 42, then being connected between this two MOS transistor and the bit line must be blocked (for example blowing with laser), write in this memory cell 42 with the representative data that logical value is different.In the following description, will in memory cell 42, store logical value " 1 " to be blocked interval scale, and in memory cell 42, be stored logical value " 0 " to block interval scale when the connection on the right when the connection on the left side.
Next will be with above-mentioned bit line (BL
11, BL
12)～(BL
M1, BL
M2) in wherein a pair of for example describes, bit line (BL for example
11, BL
12), the first bit line BL
11And the second bit line BL
12Be to be electrically connected to precharge and testing circuit 30, precharge and testing circuit 30 include a pre-charge module 32, are electrically connected to the first bit line BL
11And the second bit line BL
12, be used for to first bit line and BL
11The second bit line BL
12Carry out precharge; One logic module 34 is electrically connected to the first bit line BL
11, the second bit line BL
12, one first data line DL
1And one second data line DL
2, be used for according to one first control signal Y1 the first bit line BL
11Signal be sent to the first data line DL
1And with the second bit line BL
12Signal be sent to the second data line DL
2One charge distributing module 36 is electrically connected to the first data line DL
1And the second data line DL
2, be used for to the first data line DL
1And the second data line DL
2Carry out precharge, and stored charge in the charge distributing module 36 is dispensed to the first data line DL according to one second control signal TWL
1And the second data line DL
2And a detection module 38, be electrically connected to the first data line DL
1And the second data line DL
2, be used for detecting the first data line DL
1And the second data line DL
2Signal to produce an output signal.
Though note that formerly in the paragraph only with pair of bit lines (BL
11, BL
12) be the example explanation, but having many pairs of bit line in actual applications usually is electrically connected to a pair of first and second data line DL by different selection modules 34 respectively
1, DL
2On.
As shown in Figure 2, in the present embodiment, pre-charge module 32 includes one first charging nmos pass transistor 44, and its drain electrode is electrically connected to the first bit line BL
11, its grid is electrically connected to the inversion signal Y1b of the first control signal Y1, its source ground, the first charging nmos pass transistor 44 can be according to the control of the inversion signal Y1b of the first control signal Y1 conducting with to the first bit line BL
11Carry out precharge; And one second the charging nmos pass transistor 46, its drain electrode is electrically connected to the second bit line BL
12, its grid is electrically connected to the inversion signal Y1b of the first control signal Y1, its source ground, the second charging nmos pass transistor 46 also can be according to the control of the inversion signal Y1b of the first control signal Y1 conducting with to the second bit line BL
12Carry out precharge.Select 34 of modules to include one first and select nmos pass transistor 48, its drain electrode is electrically connected to the first bit line BL
11, its grid is electrically connected to the first control signal Y1, and its source electrode is electrically connected to the first data line DL
1And one second select nmos pass transistor 50, and its drain electrode is electrically connected to the second bit line BL
12, its grid is electrically connected to the first control signal Y1, and its source electrode is electrically connected to the second data line DL
2
And for example shown in Figure 2, in the present embodiment, charge distributing module 36 includes one first electric capacity 52, and the one end is electrically connected to a first node N
1And other end ground connection is used for storing and desires to be dispensed to the first data line DL
1Electric charge; One the one PMOS transistor 56, its source electrode are electrically connected to a supply voltage V
DD, its grid is electrically connected to the second control signal TWL, and its drain electrode is electrically connected to first node N
1One first nmos pass transistor 60, its drain electrode is electrically connected to first node N
1, its grid is electrically connected to the second control signal TWL, and its source electrode is electrically connected to the first data line DL
1One second electric capacity 54, one end are electrically connected to a Section Point N
2And other end ground connection is used for storing and desires to be dispensed to the second data line DL
2Electric charge; One the 2nd PMOS transistor 58, its source electrode is electrically connected to supply voltage V
DD, its grid is electrically connected to the second control signal TWL, and its drain electrode is electrically connected to Section Point N
2And one second nmos pass transistor 62, its drain electrode is electrically connected to Section Point N
2, its grid is electrically connected to the second control signal TWL, and its source electrode is electrically connected to the second data line DL
2When the second control signal TWL is low-voltage (being logical value " 0 "), first and second nmos pass transistor 60,62 can be turned off, first and second PMOS transistor 56,58 then can be switched on, and first and second PMOS transistor 56,58 that is switched on thus promptly can utilize the passage of its conducting first and second electric capacity 52,54 to be charged so that store electric charge in first and second electric capacity 52,54; Next first and second PMOS transistor 56,58 can be turned off when the second control signal TWL is switched to high voltage (being logical value " 1 "), first and second nmos pass transistor 60,62 then can be switched on, and first and second nmos pass transistor 60,62 that is switched on thus promptly can utilize the passage of its conducting respectively to first and second data line DL
1, DL
2Carry out charge distributing.
In addition, charge distributing module 36 also includes one the 3rd nmos pass transistor 64, and its drain electrode is electrically connected to the first data line DL
1, its grid is electrically connected to the inversion signal TWLB of the second control signal TWL, its source ground, the 3rd nmos pass transistor 64 can be according to the control of the inversion signal TWLB of the second control signal TWL conducting with to the first data line DL
1Carry out precharge; And one the 4th nmos pass transistor 66, its drain electrode is electrically connected to the second data line DL
2, its grid is electrically connected to the inversion signal TWLB of the second control signal TWL, its source ground the 4th nmos pass transistor 66 also can be according to the control of the inversion signal TWLB of the second control signal TWL and conducting with to the second bit line DL
2Carry out precharge.
As shown in Figure 2, in the present embodiment, 38 of detection modules include one first and isolate nmos pass transistor 68, and its drain electrode is electrically connected to the first data line DL
1, its grid is electrically connected to one the 3rd control signal FIC, and its source electrode is electrically connected to one first output signal line OUT
1One second isolates nmos pass transistor 70, and its drain electrode is electrically connected to the second data line DL
2, its grid is electrically connected to the 3rd control signal FIC, and its source electrode is electrically connected to one second output signal line OUT
2One first phase inverter, its input end are electrically connected to the second output signal line OUT
2, its output terminal is electrically connected to the first output signal line OUT
1And one second phase inverter, its input end is electrically connected to the first output signal line OUT
1, its output terminal is electrically connected to the second output signal line OUT
2Wherein aforesaid output signal is created in the first output signal line OUT
1On, the inversion signal of this output signal then is created in the second output signal line OUT
2On.Under above-mentioned circuit state, in the process of data read, first and second is isolated nmos pass transistor 68,70 and can be switched on according to the 3rd control signal FIC at reasonable time, with the first data line DL
1On signal be sent to the first output signal line OUT
1, and with the second data line DL
2On signal be sent to the second output signal line OUT
2, and by the latch that this first and second phase inverter is formed these signal latches are lived to produce this output signal.
In Fig. 2, detection module 38 includes an activation PMOS transistor 72 in addition, and its source electrode is electrically connected to supply voltage V
DD, its grid is electrically connected to one the 4th control signal SAEB, and its drain electrode is electrically connected to this first phase inverter and this second phase inverter, is used for activation (Enable) and anergy (Disable) according to the 4th control signal SAEB control detection circuit 38.In the present embodiment, this first phase inverter includes a PMOS transistor 74 and a nmos pass transistor 78, the grid of PMOS transistor 74 and nmos pass transistor 78 is connected with the input end as this first phase inverter, the drain electrode of PMOS transistor 74 and nmos pass transistor 78 is connected with the output terminal as this first phase inverter, the source electrode of PMOS transistor 74 is electrically connected to the drain electrode of activation PMOS transistor 72, and the source electrode of nmos pass transistor 78 is ground connection then.Similarly, this second phase inverter includes a PMOS transistor 76 and a nmos pass transistor 80, the grid of PMOS transistor 76 and nmos pass transistor 80 is connected with the input end as this second phase inverter, the drain electrode of PMOS transistor 76 and nmos pass transistor 80 is connected with the output terminal as this second phase inverter, the source electrode of PMOS transistor 76 is electrically connected to the drain electrode of activation PMOS transistor 72, and the source electrode of nmos pass transistor 80 is ground connection then.Under above-mentioned circuit configurations, then when the 4th control signal SAEB turn-offs the passage of activation nmos pass transistor 72, this first and second phase inverter will lose bias voltage and can't move; On the contrary, as the 4th control signal SAEB during with the passage conducting of activation nmos pass transistor 72, this first and second phase inverter latchs regular event and is positioned at first and second output signal line OUT
1, OUT
2On signal.
In addition, detection module 38 also includes one the 3rd nmos pass transistor 82, and its drain electrode is electrically connected to the first output signal line OUT
1, its grid is electrically connected to one the 5th control signal PC, and its source ground is used for to the first output signal line OUT
1Carry out precharge; And one the 4th nmos pass transistor 84, its drain electrode is electrically connected to the second output signal line OUT
2, its grid is electrically connected to the 5th control signal PC, and its source ground is used for to the second output signal line OUT
2Carry out precharge.The the 3rd and the 4th nmos pass transistor the 82, the 84th, can be according to the control of the 5th control signal PC conducting with respectively to the first output signal line OUT
1And the second output signal line OUT
2Carry out precharge.In Fig. 2, the 5th control signal PC carries out the AND logical operation by the inversion signal of the 3rd control signal FIC and the 4th control signal SAEB to be produced, that is when the value of arbitrary signal in the middle of the inversion signal of the 3rd control signal FIC and the 4th control signal SAEB was logical value " 0 ", the 5th control signal promptly switched to logical value " 0 " so that the 3rd and the 4th nmos pass transistor 82,84 is turn-offed.
Next Fig. 2 and Fig. 3 to be describing the principle of operation of precharge of the present invention and testing circuit 30 in detail, expression precharge of the present invention and testing circuit 30 one of them memory cell 42 (word line WL for example in reading memory cell array 40 among Fig. 3
1And bit line (BL
11, BL
12) the memory cell 52 of infall) in stored numerical data the time, the sequential chart of each control signal and signal wire among Fig. 2.Be to list the first control signal Y1, the second control signal TWL, the 3rd control signal FIC, and the 4th control signal SAEB respectively in regular turn in Fig. 3, and the first bit line BL
11, the second bit line BL
12, the first data line DL
1, the second data line DL
2, the first output signal line OUT
1, and the second output signal line OUT
2On signal.
Note that in order to illustrate and relatively convenience, is being respectively control signal Y1, TWL, FIC, the SAEB of four actives to be placed on the same time shaft in the middle of Fig. 3, and the signal BL that other are passive
11, BL
12, DL
1, DL
2, OUT
1, OUT
2And be placed on other three time shafts, as shown in Figure 3.In the present embodiment, the inversion signal Y1b of the first above-mentioned control signal Y1 and the inversion signal TWLB of the second control signal TWL be owing to be complementary with the first control signal Y1 and the second control signal TWL respectively, thus need not be listed among Fig. 3, and word line WL
1Signal be with the second control signal TWL for synchronously, the 5th control signal PC is the logical combination for the 3rd and the 4th control signal FIC, SAEB again, so also do not list in Fig. 3.In Fig. 3, be to represent respectively that according to time sequencing precharge of the present invention and testing circuit 30 are at the first output signal line OUT
1On output signal read the process of logical value " 1 " and logical value " 0 ".
Operating principle when next seeing also Fig. 3 with the numerical data " 1 " (i.e. situation when the connection on memory cell 42 left sides is blocked) that precharge of the present invention and testing circuit 30 are described in the memory cell 42 that reads memory cell array 40, are stored.Before beginning to read action, the first control signal Y1, the second control signal TWL, the 3rd control signal FIC all are set to logical value " 0 ", the 4th control signal SAEB then is set to logical value " 1 ", therefore inversion signal Y1b and TWLB are logical value " 1 ", the signal of word line is to be logical value " 0 " with second control signal TWL event synchronously, and the 5th control signal then is a logical value " 1 ".Under this state, select first, second selection nmos pass transistor 48,50 and first, second isolation nmos pass transistor 68,70 of module 34 to be turned off, 82,84 of the nmos pass transistors of the nmos pass transistor 44,46 of pre-charge module 32, the nmos pass transistor 64,66 of charge distributing module and detection module 38 can be switched on, and make first and second bit line BL
11, BL
12, first and second data line DL
1, DL
2, and first and second output signal line OUT
1, OUT
2All be precharged to 0V; First and second electric capacity 52,54 can be recharged and store electric charge because of the conducting of PMOS transistor 56,58, makes first and second node N
1, N
2On current potential be V
DD, this moment while, nmos pass transistor the 60, the 62nd was in off state; In detection module 38, then can be in disabled state because PMOS transistor 72 is turned off by this first phase inverter and latch that this second phase inverter constituted.
After beginning to read action, at first to be switched to logical value " 1 " simultaneously (be V for the first control signal Y1 and the 3rd control signal FIC
DD), then first and second charging nmos pass transistor 44,46 and nmos pass transistor 82,84 can be turned off to stop first and second data line BL
11, BL
12, and first and second output signal line OUT
1, OUT
2Charging action, first and second selects nmos pass transistor 48,50 and first and second to isolate 68,70 of nmos pass transistors can be switched on simultaneously, makes first and second bit line BL
11, BL
12, first and second data line DL
1, DL
2, and first and second output signal line OUT
1, OUT
2Can distribute electric charge mutually.
And then the second control signal TWL and be switched to logical value " 1 " with the synchronous word line WL of the second control signal TWL, then the bi-NMOS transistors in the middle of the memory cell 42 can be because word line WL
1Switching and be switched on, the bit lines that connect not intercepted side in the middle of the like this then memory cell 42 (are the second bit line BL in the present embodiment
12) can be connected to earth terminal via the passage of this nmos pass transistor.Again because the second control signal TWL is switched to logical value " 1 ", nmos pass transistor 64,66 can be turned off and stop first and second data line DL in addition
1, DL
2Charging action, PMOS transistor 56,58 also can be turned off and stop the charging of first and second electric capacity 52,54 is moved simultaneously, nmos pass transistor 60,62 then can be switched on, and first and second electric capacity 52,54 will begin by the passage of nmos pass transistor 60,62 and first and second bit line BL thus
11, BL
12, first and second data line DL
1, DL
2, and first and second output signal line OUT
1, OUT
2Carry out charge distributing.
Be all Cc at this capacitance of supposing first and second electric capacity 52,54, and the first bit line BL
11, the first data line DL
1, and the first output signal line OUT
1The summation capacitance (promptly equal the second bit line BL
12, the second data line DL
2, and the second output signal line OUT
2The summation capacitance) be C (BL+DL+OUT), then because previous first and second electric capacity the 52, the 54th is charged to V
DD, and above-mentioned all bit lines, data line and output signal line all are charged to 0V, and therefore through after the process of charge distributing, the first bit line BL
11, the first data line DL
1, and the first output signal line OUT
1On voltage will rise to V
SHARE=V
DD* C
C÷ (C
C+ C (BL+DL+OUT)), as shown in Figure 3.But the second bit line BL
12, the second data line DL
2, and the second output signal line OUT
2On voltage, then because by the passage of the nmos pass transistor in the memory cell 42 be connected to earth point so, can after the rising of blink, be returned to 0V, as shown in Figure 3.
Next, the 4th control signal SAEB then can be switched to logical value " 0 " (being 0V), then PMOS transistor 72 can be switched on and make the latch of being made up of this two phase inverter in the detection module 38 enter enabled status, thus first and second output signal line OUT
1, OUT
2On signal can be because the effect of this latch and be latched at V respectively
DDAnd 0V, and be positioned at the first output signal line OUT
1On output signal then can be read out, this moment this output signal be to correspond to the numerical data of being stored in the memory cell 42, be logical value " 1 ".In addition, be positioned at the first bit line BL
11, the first data line DL
1On voltage, then can select nmos pass transistor 48 and first to isolate the effect of nmos pass transistor 68 and be limited in (V because of first
DD-V
TH) size (V herein
THBe threshold voltage for nmos pass transistor), can reduce the power dissipation when operation of precharge and testing circuit 30.
At last, in regular turn the 3rd control signal FIC is switched back logical value " 0 ", with the 4th control signal SAEB switch back logical value " 1 ", again with the first control signal Y1 and the second control signal TWL (and word line WL
1) switch back logical value " 0 ", think that the action of reading of next stage is prepared.
It in the second half section of Fig. 3 expression precharge of the present invention and testing circuit 30 operating principle when reading the numerical data " 0 " (i.e. situation when the connection on memory cell 42 the right is blocked) of being stored in another memory cell 42 of memory cell array 40.This moment, action action of these control signals when reading numerical data " 1 " of the first, second, third and the 4th control signal Y1, TWL, FIC, SAEB was identical, and owing to the connection that is the right this moment in memory cell 42 is blocked, so first and second bit line BL
11, BL
12On magnitude of voltage opposite when reading logical value " 1 ", first and second data line DL
1, DL
2On magnitude of voltage opposite when reading logical value " 1 ", and first and second output signal line OUT
1, OUT
2On magnitude of voltage also opposite when reading logical value " 1 ", as shown in Figure 3.Then be positioned at the first output signal line OUT at last
1On output signal can be read out, this moment this output signal be to correspond to the numerical data of being stored in the memory cell 42, be logical value " 0 ".
Compare with known technology, precharge of the present invention and testing circuit are to utilize a pre-charge module and a charge distributing module with this first bit line, this second bit line, one first data line and one second data line all are precharged to ground voltage, the influence of the leakage current effects of the like this then bit line that data read memory cell on the bit line that is selected will can not be subjected to not being selected, and this charge distributing module also can be carried out charge distributing to this first data line and this second data line when reading of data, and then has accelerated the speed that signal on this first data line and this second data line enters steady state (SS).In addition, be positioned at the voltage on bit line and the data line, then can select the effect of a nmos pass transistor and an isolation nmos pass transistor and be limited in (V because of one
DD-V
TH) size, can reduce the power dissipation of this precharge and testing circuit in when operation.
The above only is the preferred embodiments of the present invention, and all equivalences of making according to claim of the present invention change and revise, and all belong to covering scope of the present invention.
Claims (10)
1. the precharge of a differential type ROM (read-only memory) and testing circuit, be used for detecting the logical data of being stored in the memory cell of this ROM (read-only memory), this memory cell can be connected to the two bit lines wherein of one first bit line and one second bit line, be used to provide this first bit line or this second bit line digital signal, this precharge and testing circuit include:
One pre-charge module is electrically connected to this first bit line and this second bit line, is used for this first bit line and this second bit line are carried out precharge;
One selects module, be electrically connected to this first bit line, this second bit line, one first data line and one second data line, be used for the signal of this first bit line being sent to this first data line and the signal of this second bit line being sent to this second data line according to one first control signal;
One charge distributing module, be electrically connected to this first data line and this second data line, be used for this first data line and this second data line are carried out precharge, and stored charge in this charge distributing module be dispensed to this first data line and this second data line according to one second control signal; And
One detection module is electrically connected to this first data line and this second data line, is used for detecting the signal of this first data line and this second data line to produce an output signal.
2. precharge as claimed in claim 1 and testing circuit, wherein this charge distributing module includes:
One first electric capacity, the one end is electrically connected to a first node and other end ground connection is used for storing the electric charge of desiring to be dispensed to this first data line;
One the one PMOS transistor, its source electrode is electrically connected to a supply voltage, and its grid is electrically connected to this second control signal, and its drain electrode is electrically connected to this first node;
One first nmos pass transistor, its drain electrode is electrically connected to this first node, and its grid is electrically connected to this second control signal, and its source electrode is electrically connected to this first data line;
One second electric capacity, the one end is electrically connected to a Section Point and other end ground connection is used for storing the electric charge of desiring to be dispensed to this second data line;
One the 2nd PMOS transistor, its source electrode is electrically connected to this supply voltage, and its grid is electrically connected to this second control signal, and its drain electrode is electrically connected to this Section Point; And
One second nmos pass transistor, its drain electrode is electrically connected to this Section Point, and its grid is electrically connected to this second control signal, and its source electrode is electrically connected to this second data line.
3. precharge as claimed in claim 2 and testing circuit, wherein this charge distributing module includes in addition:
One the 3rd nmos pass transistor, its drain electrode are electrically connected to this first data line, and its grid is electrically connected to the inversion signal of this second control signal, and its source ground is used for this first data line is carried out precharge; And
One the 4th nmos pass transistor, its drain electrode are electrically connected to this second data line, and its grid is electrically connected to the inversion signal of this second control signal, and its source ground is used for this second data line is carried out precharge.
4. precharge as claimed in claim 1 and testing circuit, wherein this pre-charge module includes:
One first charging nmos pass transistor, its drain electrode is electrically connected to this first bit line, and its grid is electrically connected to the inversion signal of this first control signal, its source ground; And
One second charging nmos pass transistor, its drain electrode is electrically connected to this second bit line, and its grid is electrically connected to the inversion signal of this first control signal, its source ground.
5. precharge as claimed in claim 1 and testing circuit, wherein this selection module includes:
One first selects nmos pass transistor, and its drain electrode is electrically connected to this first bit line, and its grid is electrically connected to this first control signal, and its source electrode is electrically connected to this first data line; And
One second selects nmos pass transistor, and its drain electrode is electrically connected to this second bit line, and its grid is electrically connected to this first control signal, and its source electrode is electrically connected to this second data line.
6. precharge as claimed in claim 1 and testing circuit, wherein this detection module includes:
One first isolates nmos pass transistor, and its drain electrode is electrically connected to this first data line, and its grid is electrically connected to one the 3rd control signal, and its source electrode is electrically connected to one first output signal line;
One second isolates nmos pass transistor, and its drain electrode is electrically connected to this second data line, and its grid is electrically connected to the 3rd control signal, and its source electrode is electrically connected to one second output signal line;
One first phase inverter, its input end are electrically connected to this second output signal line, and its output terminal is electrically connected to this first output signal line; And
One second phase inverter, its input end are electrically connected to this first output signal line, and its output terminal is electrically connected to this second output signal line;
Wherein this output signal is to be created on this first output signal line, and the inversion signal of this output signal then is created on this second output signal line.
7. precharge as claimed in claim 6 and testing circuit, wherein this detection module includes an activation PMOS transistor in addition, its source electrode is electrically connected to a supply voltage, its grid is electrically connected to one the 4th control signal, its drain electrode is electrically connected to this first phase inverter and this second phase inverter, is used for controlling according to the 4th control signal the activation and the anergy of this testing circuit.
8. precharge as claimed in claim 7 and testing circuit, wherein this first phase inverter includes a PMOS transistor and a nmos pass transistor, the grid of this PMOS transistor and this nmos pass transistor is connected with the input end as this first phase inverter, the drain electrode of this PMOS transistor and this nmos pass transistor is connected with the output terminal as this first phase inverter, the transistorized source electrode of this PMOS is electrically connected to this activation PMOS transistor drain, and the source electrode of this nmos pass transistor is ground connection then.
9. precharge as claimed in claim 6 and testing circuit, wherein this second phase inverter includes a PMOS transistor and a nmos pass transistor, the grid of this PMOS transistor and this nmos pass transistor is connected with the input end as this second phase inverter, the drain electrode of this PMOS transistor and this nmos pass transistor is connected with the output terminal as this second phase inverter, the transistorized source electrode of this PMOS is electrically connected to this activation PMOS transistor drain, and the source electrode of this nmos pass transistor is ground connection then.
10. precharge as claimed in claim 6 and testing circuit, wherein this detection module includes in addition:
One the 3rd nmos pass transistor, its drain electrode are electrically connected to this first output signal line, and its grid is electrically connected to one the 5th control signal, and its source ground is used for this first output signal line is carried out precharge; And
One the 4th nmos pass transistor, its drain electrode are electrically connected to this second output signal line, and its grid is electrically connected to the 5th control signal, and its source ground is used for this second output signal line is carried out precharge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN031234461A CN100407335C (en) | 2003-05-09 | 2003-05-09 | Precharge and detecting circuit for differential read-only storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN031234461A CN100407335C (en) | 2003-05-09 | 2003-05-09 | Precharge and detecting circuit for differential read-only storage |
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| Publication Number | Publication Date |
|---|---|
| CN1549273A true CN1549273A (en) | 2004-11-24 |
| CN100407335C CN100407335C (en) | 2008-07-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN031234461A Expired - Fee Related CN100407335C (en) | 2003-05-09 | 2003-05-09 | Precharge and detecting circuit for differential read-only storage |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102903382A (en) * | 2011-07-28 | 2013-01-30 | 台湾积体电路制造股份有限公司 | Differential ROM |
| CN111583974A (en) * | 2018-12-10 | 2020-08-25 | 钰创科技股份有限公司 | Dynamic random access memory with maintained memory architecture |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0127216B1 (en) * | 1994-11-24 | 1998-04-02 | 문정환 | Memory device |
| EP0758127B1 (en) * | 1995-06-13 | 2001-09-26 | Samsung Electronics Co., Ltd. | Sense amplifier circuit of a nonvolatile semiconductor memory device |
| US5636170A (en) * | 1995-11-13 | 1997-06-03 | Micron Technology, Inc. | Low voltage dynamic memory |
| US6141259A (en) * | 1998-02-18 | 2000-10-31 | Texas Instruments Incorporated | Dynamic random access memory having reduced array voltage |
-
2003
- 2003-05-09 CN CN031234461A patent/CN100407335C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102903382A (en) * | 2011-07-28 | 2013-01-30 | 台湾积体电路制造股份有限公司 | Differential ROM |
| CN111583974A (en) * | 2018-12-10 | 2020-08-25 | 钰创科技股份有限公司 | Dynamic random access memory with maintained memory architecture |
| CN111583974B (en) * | 2018-12-10 | 2022-09-13 | 钰创科技股份有限公司 | Dynamic random access memory with maintained memory architecture |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100407335C (en) | 2008-07-30 |
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