CN1538680A - Programmable telecommunication network interface - Google Patents
Programmable telecommunication network interface Download PDFInfo
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- CN1538680A CN1538680A CNA031164919A CN03116491A CN1538680A CN 1538680 A CN1538680 A CN 1538680A CN A031164919 A CNA031164919 A CN A031164919A CN 03116491 A CN03116491 A CN 03116491A CN 1538680 A CN1538680 A CN 1538680A
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Abstract
Programmable interface of telecommunication network (E1 interface) is mainly composed of decoding unit, digital phase locked loop, frame synchronization state machine, time slot selector etc. The E1 is capable of executing operation of transmitting and receiving data in E1 format. Operating principle of transmitting data is converting binary data to E1 format forming data in E1 frames, which are encoded in HDB3 and output from wire; when receiving data, bit synchronizing received signal decoding HDB3, decoded E1 frame through frame synchronization and solving for frame recovers binary data. The advantages are small volume, low consumption, high reliable, etc.
Description
Technical field
The invention belongs to communication interface technique, Programmable telecommunication network interface especially is applicable to the access device of telecommunications network, switching equipment and routing device interface conversion etc.
Background technology
Before the present invention made, traditional telecommunications network interface used the interface chip, buffer chip and the control chip that separate to go up through complicated wiring at printed circuit board (PCB) (PCB) and completes.This interface exists that volume is big, power consumption is big, be subject to disturb, reliability is low, shortcoming such as editing and updating interface logic function at any time.The conventional telecommunications network interface is owing to complex process simultaneously, and the design cycle is long, and cost is also higher.
Summary of the invention
Purpose of the present invention is the shortcoming that overcomes prior art, provides that volume is little, low in energy consumption, reliability is high, the telecommunications network interface of renewal able to programme (E1 interface).
Programmable telecommunication network interface includes decoding [1], digital phase-locked loop [2], frame synchronization state machine [3], time slot selector [4], time slot selector [8], serial/parallel conversion [5], parallel/serial conversion [6], framer [7], coding [9] parts, it is characterized in that mainly by digital phase-locked loop [2], frame synchronization state machine [3], time slot selector [4], time slot selector [8], framer [7] parts are formed, the line code input signal cable is connected respectively with digital phase-locked loop [2] with decoding [1], digital phase-locked loop [2] is by clock sync signal line and decoding [1], frame synchronization state machine [3], time slot selector [4] is connected respectively with serial/parallel conversion [5], decoding [1] is connected respectively with serial/parallel conversion [5] with frame synchronization state machine [3] by the decoded signal line, frame synchronization state machine [3] is connected respectively with serial/parallel conversion [5] with time slot selector [4] by the count signal line, time slot selects holding wire to be connected respectively with time slot selector [8] with time slot selector [4], the write signal line is connected to time slot selector [4], the data output signal line is connected to serial/parallel conversion [5], the data input signal line is connected to parallel/serial conversion [6], time slot selector [8] is connected with parallel/serial conversion [6] by reading signal lines, parallel/serial conversion [6] is connected with framer [7] by the serial data signal line, framer [7] is connected with time slot selector [8] by framing count signal line, framer [7] is connected with coding [9] by the framing data wire, the line code output signal line is connected with coding [9], system clock line and decoding [1], digital phase-locked loop [2], frame synchronization state machine [3], time slot selector [4], time slot selector [8], serial/parallel conversion [5], parallel/serial conversion [6], framer [7], coding [9] connects respectively.
Digital phase-locked loop [2] is made up of marginal detector [10], phase discriminator [11] and local oscillator frequency divider [12] parts, the line code input signal cable is connected with marginal detector [10], marginal detector [10] is connected with phase discriminator [11] by the edge signal lines, phase discriminator [11] is connected with local oscillator frequency divider [12] by the division control signal line, and local oscillator frequency divider [12] is connected with phase discriminator [11] by the local oscillation signal line.
Frame synchronization state machine [3] is made up of synchronous code character detector [13], state machine [14], frame-synchronizing impulse generator [15] parts, the decoded signal line is connected with synchronous code character detector [13], code character detector [13] is connected with state machine [14] by synchronous code character holding wire synchronously, state machine [14] is connected with frame-synchronizing impulse generator [15] by status signal lines, and frame-synchronizing impulse generator [14] is connected with state machine [14] by the frame synchronizing signal line.
Framer [7] is made up of frame head generator [16], counter [17] and alternative selector [18] parts, the serial data signal line is connected with alternative selector [18], frame head generator [16] is connected with alternative selector [18] by the header signal line, and counter [17] is connected with alternative selector [18] by the splitting signal line.
The present invention compared with prior art, the automatic electronic that uses a computer design (EDA) technology, download to programmable logic device by download cable and realize the description logic function, avoided complicated printed circuit board (PCB) (PCB) wiring, dwindle volume in kind, reduce power consumption, improve system reliability, have the online updating ability simultaneously.Programmable telecommunication network interface also can be programmed with other programmable interface or central microprocessor (CPU) and is connected, and realizes SOC (system on a chip) (SOC).
Description of drawings
Fig. 1: Programmable telecommunication network interface system concrete structure figure.
Fig. 2: digital phase-locked loop structure chart.
Fig. 3: frame synchronization state machine structure chart.
Fig. 4: framer structure chart.
Fig. 5: frame synchronization state machine state transition diagram.
Among the figure: [1]-decoding, [2]-digital phase-locked loop, [3]-frame synchronization state machine, [4]-and time slot selector, [5]-serial/parallel conversion, [6]-parallel/serial conversion, [7]-and framer, [8]-time slot selector, [9]-coding, [10]-and marginal detector, [11]-phase discriminator, [12]-local oscillator frequency divider, [13]-and synchronous code character detector, [14]-state machine, [15]-frame-synchronizing impulse generator, [16]-and the frame head generator, [17]-counter, [18]-alternative selector
I/O port signalization implication is as follows in the Programmable telecommunication network interface:
Sys_clk: system clock input.System clock adopts the active crystal oscillator of 32.768M.
Hin[1..0]: the input of line code data.
Hout[1..0]: the output of line code data.
Tcho[30..1]: time slot is selected.High level represents to select corresponding slot transmission data, can select in the E1 frame any time slot except that frame swynchronization code to carry out data and transmit.
Wt: write data signal.Expression has data from dout[7..0] output, high level is effective, and significant level width and system clock square-wave signal are with wide.
Dout[7..0]: channel transmission data output.The output of 8 parallel-by-bits can be sent into data buffer then.
Rd: reading data signal.Read in data to din[7..0 from the module appearance], high level is effective, and significant level width and system clock square-wave signal are with wide.
Din[7..0]: the transmission data are read in.The input of 8 parallel-by-bits can be imported from data buffer.
Mc_en: external clock input enable signal.Represent to use external clock synchronous signal during high level, otherwise use inner synchronousing signal.
M_clk: external clock input.According to the difference of clock synchronization requirement situation, can be from the m_clk input clock signal.
Embodiment
Embodiment 1: as shown in Figure 1, operation principle of the present invention and embodiment are: use the MAXPLUSII software of ALTERA company that description document is compiled the formation download configuration file.By download cable file in download is downloaded on the ACEX1K30 device then, perhaps use cd-rom recorder that configuring chip is carried out burning.
Programmable telecommunication network interface includes decoding [1], digital phase-locked loop [2], frame synchronization state machine [3], time slot selector [4], time slot selector [8], serial/parallel conversion [5], parallel/serial conversion [6], framer [7], coding [9] parts, it is characterized in that mainly by digital phase-locked loop [2], frame synchronization state machine [3], time slot selector [4], time slot selector [8], framer [7] parts are formed, the line code input signal cable is connected respectively with digital phase-locked loop [2] with decoding [1], digital phase-locked loop [2] is by clock sync signal line and decoding [1], frame synchronization state machine [3], time slot selector [4] is connected respectively with serial/parallel conversion [5], decoding [1] is connected respectively with serial/parallel conversion [5] with frame synchronization state machine [3] by the decoded signal line, frame synchronization state machine [3] is connected respectively with serial/parallel conversion [5] with time slot selector [4] by the count signal line, time slot selects holding wire to be connected respectively with time slot selector [8] with time slot selector [4], the write signal line is connected to time slot selector [4], the data output signal line is connected to serial/parallel conversion [5], the data input signal line is connected to parallel/serial conversion [6], time slot selector [8] is connected with parallel/serial conversion [6] by reading signal lines, parallel/serial conversion [6] is connected with framer [7] by the serial data signal line, framer [7] is connected with time slot selector [8] by framing count signal line, framer [7] is connected with coding [9] by the framing data wire, the line code output signal line is connected with coding [9], system clock line and decoding [1], digital phase-locked loop [2], frame synchronization state machine [3], time slot selector [4], time slot selector [8], serial/parallel conversion [5], parallel/serial conversion [6], framer [7], coding [9] connects respectively.
As shown in Figure 2: digital phase-locked loop [2] is made up of marginal detector [10], phase discriminator [11] and local oscillator frequency divider [12] parts, the line code input signal cable is connected with marginal detector [10], marginal detector [10] is connected with phase discriminator [11] by the edge signal lines, phase discriminator [11] is connected with local oscillator frequency divider [12] by the division control signal line, and local oscillator frequency divider [12] is connected with phase discriminator [11] by the local oscillation signal line.
As shown in Figure 3: frame synchronization state machine [3] is made up of synchronous code character detector [13], state machine [14], frame-synchronizing impulse generator [15] parts, the decoded signal line is connected with synchronous code character detector [13], code character detector [13] is connected with state machine [14] by synchronous code character holding wire synchronously, state machine [14] is connected with frame-synchronizing impulse generator [15] by status signal lines, and frame-synchronizing impulse generator [14] is connected with state machine [14] by the frame synchronizing signal line.
As shown in Figure 4: framer [7] is made up of frame head generator [16], counter [17] and alternative selector [18] parts, the serial data signal line is connected with alternative selector [18], frame head generator [16] is connected with alternative selector [18] by the header signal line, and counter [17] is connected with alternative selector [18] by the splitting signal line.
Operation principle when receiving data: as Fig. 1, Fig. 2, shown in Figure 3, outside two-way line signal hin[1..0] be input to digital phase-locked loop [2] respectively and decode [1].Digital phase-locked loop [2] is extracted line signal digit pulse information mutually or through marginal detector [10] with the two-way line code of input, digit pulse information through phase discriminator [11] and local oscillator frequency divider [12] pulse ratio mutually, if lag behind, local oscillator frequency divider [12] divide ratio increases, if it is leading, then local oscillator frequency divider [12] divide ratio reduces, and constantly adjusts up to phase-locked success.The bit synchronization signal that digital phase-locked loop [2] produces acts on decoding [1], frame synchronization state machine [3], and time slot is selected [4], serial/parallel conversion [5].Under decoding [1] synchronizing datum signal effect on the throne line code is decoded, line code is reverted to the E1 frame.The E1 frame is transferred to frame synchronization state machine [3] and carries out frame synchronization.Frame synchronization state machine [3] carries out synchronous code character to the E1 frame and detects, when the frame synchronization code character occurs, starting state machine [14] carries out state exchange, the state transition diagram of state machine [14] is as shown in Figure 5: be in the los_sta state when initial, when synchronous code character detector [13] detects the external sync code character, state machine [14] enters accurate synchronous state syn_1 by the step-out attitude, starts frame-synchronizing impulse generator [15] counting simultaneously; Frame-synchronizing impulse generator [15] count module length is two distances between the frame synchronization code character, when counter overflows, to detect whether the synchronous code character of external frame occurs again, if state machine enters plesiochronous mode syn_2 with same steps in sequence, up to synchronous state syn_sta, if wherein once do not examine the frame synchronization code character arbitrarily then state machine returns initial step-out attitude los_sta; After state machine enters synchronous state syn_sta, if can not detect the external sync code character when counter overflows, then enter accurate step-out attitude los_los_2, los_3 successively, up to step-out attitude los_sta, if wherein once examine the frame synchronization code character again arbitrarily then return synchronous state.Frame synchronization is set up back back output frame lock-out pulse and slot synchronization pulse.The frame synchronization state machine has effectively been avoided pseudo-frame synchronization code character and error code influence that frame synchronization is set up once in a while.Time slot is selected [4] according to tcho[30..0] situation output wt pulse is set, be input to serial/parallel conversion [5] from E1 frame assigned timeslot sense data, serial/parallel conversion is in following time slot data parallel output of the effect of bit synchronization signal.
Operation principle when sending data: as Fig. 1, shown in Figure 4, the parallel data serial that reads in of parallel/serial conversion [6] is exported, and time slot is selected [8] according to tcho[30..0] situation generation rd signal is set, specifying the E1 frame slot to read in data.Bit synchronization signal used herein can be from line code, extract bit synchronization signal, also can be outside clock signal, select flexibly by the mc_en signal.Framer [7] inserts corresponding time slot to the input data, and adds the frame synchronization code character, forms the output of E1 frame.Coding [9] is the output of encoding of E1 frame data.
Embodiment 2: as Fig. 1, Fig. 2, Fig. 3, shown in Figure 4, Programmable telecommunication network interface can combine with Ethernet interface and finish protocol conversion work.Programmable telecommunication network interface will receive data write buffer buffer memory, and Ethernet interface is from buffer sense data packing output.Or Ethernet interface will receive data write buffer buffer memory, and Programmable telecommunication network interface is exported from buffer sense data framing.Other is identical with embodiment 1.
Embodiment 3: as Fig. 1, Fig. 2, Fig. 3, shown in Figure 4, Programmable telecommunication network interface combines with the programmable logic device that contains embedded central microprocessor, downloads on the chip, realizes SOC (system on a chip) (SOC).Programmable telecommunication network interface is by data wire and embedded central microprocessor swap data, other with
Embodiment 4: as Fig. 1, Fig. 2, Fig. 3, shown in Figure 4, can carry out a plurality of Programmable telecommunication network interfaces multiplexing, add switching processor after, can finish the function of E1 frame exchange.Other is identical with embodiment 1.
Claims (4)
1. Programmable telecommunication network interface includes decoding [1], digital phase-locked loop [2], frame synchronization state machine [3], time slot selector [4], time slot selector [8], serial/parallel conversion [5], parallel/serial conversion [6], framer [7], coding [9] parts, it is characterized in that mainly by digital phase-locked loop [2], frame synchronization state machine [3], time slot selector [4], time slot selector [8], framer [7] parts are formed, the line code input signal cable is connected respectively with digital phase-locked loop [2] with decoding [1], digital phase-locked loop [2] is by clock sync signal line and decoding [1], frame synchronization state machine [3], time slot selector [4] is connected respectively with serial/parallel conversion [5], decoding [1] is connected respectively with serial/parallel conversion [5] with frame synchronization state machine [3] by the decoded signal line, frame synchronization state machine [3] is connected respectively with serial/parallel conversion [5] with time slot selector [4] by the count signal line, time slot selects holding wire to be connected respectively with time slot selector [8] with time slot selector [4], the write signal line is connected to time slot selector [4], the data output signal line is connected to serial/parallel conversion [5], the data input signal line is connected to parallel/serial conversion [6], time slot selector [8] is connected with parallel/serial conversion [6] by reading signal lines, parallel/serial conversion [6] is connected with framer [7] by the serial data signal line, framer [7] is connected with time slot selector [8] by framing count signal line, framer [7] is connected with coding [9] by the framing data wire, the line code output signal line is connected with coding [9], system clock line and decoding [1], digital phase-locked loop [2], frame synchronization state machine [3], time slot selector [4], time slot selector [8], serial/parallel conversion [5], parallel/serial conversion [6], framer [7], coding [9] connects respectively.
2. according to the described Programmable telecommunication network interface of claim 1, it is characterized in that digital phase-locked loop [2] is made up of marginal detector [10], phase discriminator [11] and local oscillator frequency divider [12] parts, the line code input signal cable is connected with marginal detector [10], marginal detector [10] is connected with phase discriminator [11] by the edge signal lines, phase discriminator [11] is connected with local oscillator frequency divider [12] by the division control signal line, and local oscillator frequency divider [12] is connected with phase discriminator [11] by the local oscillation signal line.
3. according to the described Programmable telecommunication network interface of claim 1, it is characterized in that frame synchronization state machine [3] is made up of synchronous code character detector [13], state machine [14], frame-synchronizing impulse generator [15] parts, the decoded signal line is connected with synchronous code character detector [13], code character detector [13] is connected with state machine [14] by synchronous code character holding wire synchronously, state machine [14] is connected with frame-synchronizing impulse generator [15] by status signal lines, and frame-synchronizing impulse generator [14] is connected with state machine [14] by the frame synchronizing signal line.
4. according to the described Programmable telecommunication network interface of claim 1, it is characterized in that framer [7] is made up of frame head generator [16], counter [17] and alternative selector [18] parts, the serial data signal line is connected with alternative selector [18], frame head generator [16] is connected with alternative selector [18] by the header signal line, and counter [17] is connected with alternative selector [18] by the splitting signal line.
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| CN 03116491 CN1286296C (en) | 2003-04-16 | 2003-04-16 | Programmable telecommunication network interface |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100417068C (en) * | 2005-01-27 | 2008-09-03 | 浙江中控技术股份有限公司 | Ethernet signal processor and Ethernet signal processing method |
| CN100444561C (en) * | 2005-08-29 | 2008-12-17 | 中兴通讯股份有限公司 | Signal collecting module with exchanging convergence function |
| CN101330354B (en) * | 2008-07-23 | 2011-05-18 | 北京佳讯飞鸿电气股份有限公司 | Method for transmitting data through E1 |
| CN111917504A (en) * | 2020-07-20 | 2020-11-10 | 武汉海奥电气有限公司 | Double-line synchronous high-speed transmission system for transmitting multi-path data |
-
2003
- 2003-04-16 CN CN 03116491 patent/CN1286296C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100417068C (en) * | 2005-01-27 | 2008-09-03 | 浙江中控技术股份有限公司 | Ethernet signal processor and Ethernet signal processing method |
| CN100444561C (en) * | 2005-08-29 | 2008-12-17 | 中兴通讯股份有限公司 | Signal collecting module with exchanging convergence function |
| CN101330354B (en) * | 2008-07-23 | 2011-05-18 | 北京佳讯飞鸿电气股份有限公司 | Method for transmitting data through E1 |
| CN111917504A (en) * | 2020-07-20 | 2020-11-10 | 武汉海奥电气有限公司 | Double-line synchronous high-speed transmission system for transmitting multi-path data |
| CN111917504B (en) * | 2020-07-20 | 2022-07-05 | 武汉海奥电气有限公司 | Double-line synchronous high-speed transmission system for transmitting multi-path data |
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| CN1286296C (en) | 2006-11-22 |
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Assignee: Zhejiang Nantian post and Telecommunication Technology Co., Ltd. Assignor: Zhejiang University of Technology Contract fulfillment period: 2008.3.18 to 2013.3.17 contract change Contract record no.: 2009330000981 Denomination of invention: Programmable telecommunication network interface Granted publication date: 20061122 License type: Exclusive license Record date: 2009.5.13 |
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Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2008.3.18 TO 2013.3.17; CHANGE OF CONTRACT Name of requester: ZHEJIANG NANTIAN P+T CO., LTD. Effective date: 20090513 |
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