CN1538617A - Offset compensation circuit and drive circuit and liquid crystal display device using it - Google Patents
Offset compensation circuit and drive circuit and liquid crystal display device using it Download PDFInfo
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- CN1538617A CN1538617A CNA200410031747XA CN200410031747A CN1538617A CN 1538617 A CN1538617 A CN 1538617A CN A200410031747X A CNA200410031747X A CN A200410031747XA CN 200410031747 A CN200410031747 A CN 200410031747A CN 1538617 A CN1538617 A CN 1538617A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims description 34
- 239000003990 capacitor Substances 0.000 claims abstract description 77
- 210000002858 crystal cell Anatomy 0.000 claims description 14
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- 238000002834 transmittance Methods 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 11
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/003—Changing the DC level
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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Abstract
An offset-compensation drive circuit turns on first, second and third switches to charge a first capacitor to an offset voltage of a drive circuit, and thereafter turns off the first and second switches and turns on a fourth switch to charge a second capacitor to a first voltage loss caused by a parasitic capacitor of an input node of the drive circuit. Following this, the third and fourth switches are turned off and fifth and sixth switches are turned on. At this time as well, there occurs a second voltage loss due to the parasitic capacitor and thus an output voltage is equal to a difference between an input voltage and the second voltage loss. Supposing that the parasitic capacitor, the first capacitor and the second capacitor have the same capacitance value, the second voltage loss is one-sixth as large as the first voltage loss.
Description
Technical field
The present invention relates to bias compensation circuit and use the drive circuit and the liquid crystal indicator of the band bias compensation function of this bias compensation circuit, particularly relate to the compensation output current potential corresponding with importing current potential drive circuit bias voltage bias compensation circuit and use the drive circuit and the liquid crystal indicator of the band bias compensation function of this bias compensation circuit.
Background technology
In the past, the bias compensation circuit of the bias voltage of eliminating drive circuit was adopted in suggestion always.In this bias compensation circuit, make capacitor charge to bias voltage, compensate bias voltage (for example the spy opens the 2000-114889 communique) by the input node that this capacitor is connected to drive circuit.
But, in bias compensation circuit in the past, owing to be activated the influence of parasitic capacitance of the input node of circuit, thus can cause the loss of voltage of capacitor, and eliminate bias voltage accurately.
If the capacitance of capacitor is big more a lot of than parasitic capacitance, then the loss of voltage can be reduced, but the area of capacitor certainly will be will increased thus, cause the occupied area of bias compensation circuit to increase.When bias compensation circuit is used for the data line drive circuit of liquid crystal indicator, owing to need to adopt a lot of bias compensation circuits, thereby will produce very big problem.
Summary of the invention
Just because of this, main purpose of the present invention is the drive circuit and the liquid crystal indicator of the band bias compensation function that a kind of bias compensation circuit of accurately eliminate bias voltage is provided and uses this bias compensation circuit.
In bias compensation circuit involved in the present invention, be provided with: the 1st～the N capacitor, 1 elementary electrode is connected to the input node of drive circuit, each 1 electrode is connected on another electrode of previous stage; The 1st commutation circuit provides the current potential of regulation to the input node of drive circuit, and another electrode of the 1st capacitor is connected to the output node of drive circuit and makes the 1st capacitor charge to bias voltage; The 2nd commutation circuit, time is in accordance with regulations selected the 2nd～the N capacitor successively separately, the input current potential is offered 1 electrode of the capacitor of having selected, another electrode with the capacitor selected is connected with the output node of drive circuit simultaneously, and makes the 1st～the N capacitor charge to bias voltage; And the 3rd commutation circuit that described input current potential is provided to another electrode of N capacitor.Therefore, can reduce the influence of parasitic capacitance of the input node of drive circuit, and eliminate bias voltage accurately.
With reference to accompanying drawing and in conjunction with further understanding above-mentioned and other purpose, feature, situation and advantage of the present invention about following detailed description meeting of the present invention.
Description of drawings
Accompanying drawing 1 is the integrally-built block diagram of the color liquid crystal display arrangement described in the expression embodiment of the present invention 1.
Accompanying drawing 3 is the compensator that comprised in the horizontal scanning circuit of expression shown in the accompanying drawing 1 and the circuit diagram of pre-charge circuit structure.
Accompanying drawing 7 is sequential charts of action of the drive circuit of the band bias compensation function of expression shown in the accompanying drawing 5.
Accompanying drawing 8 is circuit diagrams of the variation of expression execution mode 1.
Accompanying drawing 9 is circuit diagrams of the structure of the pusher drive circuit that comprised in the drive circuit of expression embodiments of the present invention 2 described band bias compensation functions.
Accompanying drawing 13 is circuit diagrams of the variation of expression execution mode 3.
Accompanying drawing 14 is circuit diagrams of other variation of expression execution mode 3.
Accompanying drawing 15 is circuit diagrams of structure of the drive circuit of embodiments of the present invention 4 described band bias compensation functions.
Embodiment
Accompanying drawing 1 is the block diagram of the structure of the color liquid crystal display arrangement described in the expression embodiment of the present invention 1.In accompanying drawing 1, this color liquid crystal display arrangement comprises liquid crystal panel 1, vertical scanning circuit 7 and horizontal scanning circuit 8, and this device for example can be arranged on the portable telephone.
As shown in Figure 2, be provided with liquid crystal display drive circuit 10 in each liquid crystal cells 2.Liquid crystal display drive circuit 10 comprises N transistor npn npn 11 and capacitor 12.N transistor npn npn 11 is connected between the electrode 2a of data wire 6 and liquid crystal cells 2, and its grid is connected with scan line 4.Capacitor 12 is connected between the electrode 2a and common electrical bit line 5 of liquid crystal cells 2.Another electrode to liquid crystal cells 2 provides driving current potential VDD, provides common potential VSS to common electrical bit line 5.
Turn back to accompanying drawing 1, vertical scanning circuit 7 is according to picture intelligence, and the time is according to the rules selected multi-strip scanning line 4 successively separately, and the scan line of selecting 4 is placed " H " level of selecting level.In case scan line 4 is placed in " H " level of selecting level, then N transistor npn npn 11 conductings in the accompanying drawing 2, an electrode 2a of each liquid crystal cells 2 corresponding with this scan line 4 connects with the data wire 6 corresponding to liquid crystal cells 2.
Horizontal scanning circuit 8 is selected to provide tonal gradation current potential VG to each data wire 6 during 1 scan line 4 at vertical scanning circuit 7 according to picture intelligence.The light transmittance of liquid crystal cells 2 changes with the level of tonal gradation current potential VG.When scanning all liquid crystal cells 2 of liquid crystal panels 1, just on liquid crystal panel 1, show an images by vertical scanning circuit 7 and horizontal scanning circuit 8.
Accompanying drawing 3 is circuit diagrams of the core texture of the horizontal scanning circuit 8 shown in the expression accompanying drawing 1.In accompanying drawing 3, this horizontal scanning circuit 8 is included in to each data wire 6 provides the current potential that is used to make each data wire 6 before the tonal gradation current potential VG to place compensator and the pre-charge circuit 15 of precharge potential VPC.
Compensator and pre-charge circuit 15 comprise with the switch 16 of each data wire 6 corresponding settings and with the switch 17 of 2 data wire 6 corresponding settings of respectively adjoining.One termination of switch 16 is subjected to precharge potential VPC, and the other end is connected on the corresponding data line 6.Switch 16 is placed in as " H " level of activation level and conducting along with precharging signal Φ PC.In case switch 16 conductings, then each data wire 6 is changed to precharge potential VPC.Switch 17 is connected between 2 data wires 6, and along with compensating signal Φ EQ is placed in as " H " level of activation level and conducting.In case switch 17 conductings, then the current potential equalization of all data wires 6.After switch 16 and 17 ends, provide tonal gradation current potential VG to each data wire 6.Here, precharge potential VPC is made as 0V.
Tonal gradation potential generating circuit 20 comprise between the line of the line that is connected in series in the 1st power supply potential VH (5V) and the 2nd power supply potential VL (0V) n+1 (but, n is a natural number) resistive element 21.1～21.n+1, and be connected to n switch 22.1～22.n between node of the n between n+1 resistive element 21.1～21.n+1 and output node 20a.
At the current potential that on the node of the n between n+1 resistive element 21.1～21.n+1, occurs the n level respectively.Switch 22.1～22.n is controlled by visual node signal φ P, and only is set to conducting state with one in them.The current potential of any one-level outputs to output node 20a as tonal gradation current potential VG in the n level current potential.The drive circuit 25 of band bias compensation function provides electric current to make selecteed data wire 6 become tonal gradation current potential VG to data wire 6.
As shown in Figure 6, pusher drive circuit 26 comprises P transistor npn npn 31～33, N transistor npn npn 34,35 and constant-current source 36,37.P transistor npn npn 31,32 is connected to line and the node N31 of the 3rd power supply potential VH1 (for example 10V), and between the N32, and their grid is connected on the node N32 jointly.P transistor npn npn 31,32 constitutes current mirroring circuit.
N transistor npn npn 34,35 is connected to node N31, and between N32 and the node N34, and its grid is connected on input node N21 and the output node N22.Constant-current source 36 is from the constant current of output node 34 to the line output regulation of the 4th power supply potential VL1 (for example 0V).P transistor npn npn 33 is connected between the line and output node N22 of the 3rd power supply potential VH1, and its grid is connected with node N31.Constant-current source 37 is from the constant current of output node N22 to the line output regulation of the 4th power supply potential VL1.P transistor npn npn 31,32, N transistor npn npn 34,35 and constant-current source 36 constitute differential amplifier circuit.
Current direction N transistor npn npn 34 with the corresponding grade of current potential V21 of importing node potential N21.Current direction N transistor npn npn 35 with the corresponding grade of current potential V22 of output node N22.P transistor npn npn 31 and 32 constitutes current mirroring circuits because P transistor npn npn 32 is connected in series with N transistor npn npn 35, so with the current direction transistor 31,32,35 of the corresponding grade of current potential V22 of output node current potential N22.
When V21 was higher than V22, the electric current that the current ratio that flows to P transistor npn npn 31 flows to N transistor npn npn 34 was little, and the current potential of node N31 reduces, and the electric current that flows to P transistor npn npn 33 increases, and current potential V22 rises.When V21 was lower than V22, the electric current that the current ratio that flows to P transistor npn npn 31 flows to N transistor npn npn 34 was big, and the current potential of node N31 rises, and the electric current that flows to P transistor npn npn 33 reduces, and causes current potential V22 to reduce.Therefore, become V21=V22.
That is, pusher drive circuit 26 is a kind of input impedance height and output impedance is low, and voltage amplification degree is 1 buffer circuit.But, because the deviation of the threshold voltage of transistor 31～35 produces potential difference, i.e. bias voltage VOF between input current potential V21 and output potential V22.For example, threshold voltage VTN can produce bias voltage VOF not simultaneously between N transistor npn npn 34,35.This bias voltage VOF is poor with the threshold voltage of N transistor npn npn 34,35 | and Δ VTN| represents.
Turn back to accompanying drawing 5, the input node N21 of pusher drive circuit 26 has parasitic capacitance C0.In the accompanying drawing 5, this parasitic capacitance C0 represents with the capacitor 28 between the line that is connected input node N21 and earthing potential GND.In addition, load capacitance is represented with the capacitor 29 between the line that is connected output node N23 and earthing potential GND.Capacitor 27.1,27.2 and switch S 1, S2.1, S2.2, S3.1, S3.2, S4 are configured for compensating the bias compensation circuit of the bias voltage VOF of pusher drive circuit 26.
That is to say that switch S 1 is connected between the input node N21 of input node N20 and drive circuit 26, switch S 4 is connected between the output node N22 of output node N23 and drive circuit 26.Capacitor 27.1 and switch S 2.1 are connected in series between the input node N21 and output node N22 of drive circuit 26.Switch S 3.1 is connected input node N20 and between the node N1 between capacitor 27.1, the switch S 2.1.Capacitor 27.2 and switch S 2.2 are connected in series between node N1 and the N22.Switch S 3.2 is connected input node N20 and between the node N2 of 2.2 in capacitor 27.2, switch S.
Switch S 1, S2.1, S2.2, S3.1, S3.2, S4 both can be the P transistor npn npns, also can be the N transistor npn npns, simultaneously also can be P transistor npn npn and N transistor npn npn to be connected in parallel constitute together.Switch S 1, S2.1, S2.2, S3.1, S3.2, S4 are according to control signal (not shown) and conduction and cut-off.
Now, to the output potential V22 of drive circuit 26 than input current potential V21 only the situation of low bias voltage VOF describe.As shown in Figure 7, in initial condition, all switch S 1, S2.1, S2.2, S3.1, S3.2, S4 all are in cut-off state.T1 at a time, in case switch S 1, S2.1, S2.2 conducting, then the current potential V21 of the input node N21 of drive circuit 26 becomes V21=VI, and the output potential V22 of drive circuit 26 and node N1, the current potential V1 of N2, V2 becomes V22=V1=V2=VI-VOF, and when capacitor 27.1 was charged to bias voltage VOF, the terminal voltage of capacitor 27.2 was reset to 0V.Afterwards, at moment t2, when switch S 1, when S2.1 ended, bias voltage VOF remained on the capacitor 27.1.At next moment t3, when switch S 3.1 conductings, then the current potential V1 of node N1 becomes V1=VI.If do not have parasitic capacitance C0 on the input node N21 of drive circuit 26, then the input current potential V21 of drive circuit 26 becomes V21=VI+VOF, and the output potential V22 of drive circuit 26 becomes V22=VI.But just owing in fact have parasitic capacitance C0, so the input current potential V21 of drive circuit 26 becomes V21=VI+VOF-Δ V1, and the output potential V22 of drive circuit 26 becomes V22=VI-Δ V1.When representing the electric capacity of capacitor 27.1 with C1, this loss voltage Δ V1 can represent with following formula.
ΔV1＝VOF·C0/(C0+C1) …(1)
And, since switch S 2.2 at this moment, the S3.1 conducting, and switch S 3.2 is ended, thereby the current potential V2 of node N2 becomes V2=VI-Δ V1.That is, the current potential V2 of node N2 becomes the current potential of the loss voltage Δ V1 that is produced than only low the 1st the biasing elimination action of input voltage VI, and capacitor 27.2 is charged to Δ V1.
In moment t4 switch S 2.2, after S3.1 ended, when in 3.2 conductings of the moment t5 switch S, the current potential V2 of node N2 became VI from VI-Δ V1.In other words, the current potential V2 of the node N2 Δ V1 that only risen.This changing unit Δ V1 is delivered to node N21 by capacitor 27.2,27.1, thereby the current potential V21 of node N21 rises.But, in this case still can be owing to parasitic capacitance C0 produces loss voltage Δ V2, the current potential V21 of the node N21 Δ V1-Δ V2 that only rises becomes V21=VI+VOF-Δ V1+ Δ V1-Δ V2=VI+VOF-Δ V2.
Because the rising of the current potential V1 of node N21, the voltage Δ V1-Δ V2 that the current potential V22 of node N22 also only rises identical becomes V22=VI-Δ V1+ Δ V1-Δ V2=VI-Δ V2.In addition, when using C1, C2 to represent the electric capacity of capacitor 27.1,27.2 respectively, the current potential V1 of node N1 can represent with following formula (2):
V1＝VI+ΔV1·C2/[C2+C0·C1/(C0+C1)]?…(2)
And Δ V2 can be represented by following formula (3):
ΔV2＝ΔV1·C0/[C0+C1·C2/(C1+C2)]?…(3)
Here, for convenience of explanation, suppose C1=C2, then Δ V2=Δ V1C0/ (C0+C1/2).And then, if C0/C1=1/10, then Δ V2=Δ V11/6.That is, the 2nd biasing eliminated the loss part Δ V2 that action produced and is reduced to 1/6 of the 1st loss part Δ V1.
In order to realize using 1 capacitor and utilize the existing method of carrying out the 1st biasing elimination action to make loss part Δ V1 become 1/6 that space required is the capacitor of 6 times in former capacitor.On the other hand, in present embodiment 1, owing to use 2 capacitors 27.1 and 27.2, institute is so that the area of capacitor becomes original 2 times, but the area that is used to make loss part Δ V1 to become 1/6 capacitor just has the 2/6=1/3 of area now.And, switch S 2.2, the area of S3.2 is compared very little with capacitor.
Then, if in 4 conductings of moment t6 switch S, then output potential V0 becomes V0=VI-Δ V2 and offers load.Moreover switch S 4 is not necessary.If but do not have switch S 4, and then when load capacitance is very big, from moment t1 switch S 1, S2.1, the S2.2 conducting begins to settle out the needed time with elongated to the terminal voltage VOF of capacitor 27.1.
Accompanying drawing 8 is circuit diagrams of structure of drive circuit 38 of the band bias compensation function of expression present embodiment 1 described variation.With reference to accompanying drawing 8 as can be known, the drive circuit 38 of this band bias compensation function is with the difference of the drive circuit 25 of the band bias compensation function of accompanying drawing 5: with m (but, m is the integer more than or equal to 3) capacitor 27.1～27.m, m switch S 2.1～S2.m, m switch S a 3.1～S3.m replaces 2 capacitors 27.1,27.2,2 switch S 2.1, S2.2 and 2 switch S 3.1, S3.2.
An electrode of capacitor 27.1 is connected the input node of drive circuit 26, and the electrode of capacitor 27.2～27.m is connected on another electrode of capacitor 27.1～27.m-1.The end of switch S 2.1～S2.m all is connected on the node N22, and their other end is connected on another electrode of capacitor 27.1～27.m.The end of switch S 3.1～S3.m all is connected on the node N20, and their other end is connected on another electrode of capacitor 27.1～27.m.
At a time, switch S 1, S2.1～S2.m conducting, capacitor 27.1 is charged to bias voltage VOF, and simultaneously, the terminal voltage of capacitor 27.2～27.m is reset to 0V.
The electric capacity of each is C1 among capacitor 27.1～27.m if establish, and the loss of voltage Δ Vm when then carrying out m biasing elimination action can represent with following formula (4).
ΔVm＝VOF·C0/(C0+C1)·C0/(C0+C1/2)…C0/(
C0+C1/m) …(4)
But though loss voltage Δ Vm reduces with the increase of m, the degree that reduces diminishes gradually, on the contrary, relatively become greatly owing to the area of capacitor 27.1～27.m increases the harmful effect that produces, therefore, need set the number of times m of the best according to required output potential precision.
Accompanying drawing 9 is circuit diagrams of core texture of the drive circuit of embodiments of the present invention 2 described band bias compensation functions.With reference to accompanying drawing 9 as can be known, the difference of the drive circuit 25 of the band bias compensation function of the drive circuit of this band bias compensation function and accompanying drawing 5 is: replaced pusher drive circuit 26 with pusher drive circuit 40.
This push type drive circuit 40 comprises constant- current source 41,42, N transistor npn npn 43,44 and P transistor npn npn 45,46.Constant-current source 41, N transistor npn npn 43 and P transistor npn npn 45 are connected between the line of the line of the 3rd power supply potential VH1 (for example 10V) and the 4th power supply potential VL1 (for example 0V).The grid of P transistor npn npn 45 is connected on the input node N21.The grid of N transistor npn npn 43 is connected with its drain electrode (node N41).N transistor npn npn 43 constitutes diode.Because the drive current of transistor 43,45 is set at much larger than the current value of constant-current source 41, therefore, P transistor npn npn 45 carries out source output (source-follower) operation, and the current potential V41 of node N41 becomes V41=V21+|VTP|+VTN.Here, VTP is the threshold voltage of P transistor npn npn, and VTN is the threshold voltage of N transistor npn npn.
N transistor npn npn 44, P transistor npn npn 46 and constant-current source 42 are connected between the line of the line of the 5th power supply potential VH2 (for example 10V) and the 6th power supply potential VL2 (for example 0V).The current potential V41 of the grid recipient node N41 of N transistor npn npn 44.The grid of P transistor npn npn 46 is connected with its drain electrode (output node N22).The drive current of transistor 44,46 is set at much larger than the current value of constant-current source 42, and therefore, N transistor npn npn 44 carries out the source output function, and the current potential V22 of output node N22 becomes V22=V41-VTN-|VTP|=V21.
That is, this push type drive circuit 40 be the level shift circuit that constitutes by constant-current source 41, N transistor npn npn 43 and P transistor npn npn 45 with constitute level shift circuit by N transistor npn npn 44, P transistor npn npn 46 and constant-current source 42 and carry out 2 grades and be connected the circuit that forms.This drive circuit 40 charges by 44,46 pairs of nodes that are pre-charged to than electronegative potential of transistor, and makes the current potential V22 of output node N22 rise to the current potential V21 that imports node N21.
When N transistor npn npn 43 is identical with 44 threshold voltage VTN, and under P transistor npn npn 45 situation identical with 46 threshold voltage VTP, this drive circuit 40 does not have bias voltage VOF.But under N transistor npn npn 43 and 44 threshold voltage VTN situation inequality and/or the threshold voltage VTP situation inequality of P transistor npn npn 45 and 46, will produce bias voltage VOF.At this moment, the difference of establishing the threshold voltage VTN of N transistor npn npn 43 and 44 is Δ VTN, and when the difference of P transistor npn npn 45 and 46 threshold voltage VTP was Δ VTP, bias voltage VOF became VOF=| Δ VTP+ Δ VTN|.This bias voltage VOF is owing to above-mentioned biasing elimination action repeatedly reduces.
In this 2nd execution mode, to compare with execution mode 1, the through current of drive circuit reduces, and power consumption reduces.
Below, the variation of present embodiment 2 is described.
The pusher drive circuit 47 of accompanying drawing 10 is to remove N transistor npn npn 43 and P transistor npn npn 46 and constitute from the pusher drive circuit 40 of accompanying drawing 9.The current potential V41 of node N41 becomes V41=V21+| Δ VTP|, and output potential V22 becomes V22=V41-VTN=V21+|VTP|-VTN.So these 47 starting stages of drive circuit have bias voltage VOF=VTN-|VTP|.This bias voltage VOF is owing to above-mentioned biasing elimination action repeatedly reduces.
The pusher drive circuit 48 of accompanying drawing 11 is to remove constant-current source 41 and P transistor npn npn 45 and the grid of N transistor npn npn 44 is formed by connecting with input node N21 from the pusher drive circuit 47 of accompanying drawing 10.Output potential V22 becomes V22=V21-VTN.Therefore, these 48 starting stages of drive circuit have bias voltage VOF=VTN.This bias voltage VOF is owing to above-mentioned biasing elimination action repeatedly reduces.
Execution mode 3
Accompanying drawing 12 is circuit diagrams of structure of the drive circuit of expression execution mode 3 described band bias compensation functions.With reference to accompanying drawing 12 as can be known, the difference of the drive circuit 25 of the band bias compensation function of the drive circuit of this band bias compensation function and accompanying drawing 5 is: adopt pusher drive circuit 50 to replace pusher drive circuit 26.When accompanying drawing 3 illustrated precharge potential VCP are 5V, because tonal gradation current potential VG is 0～5V, thus can carry out the discharge of data wire 6, and do not need charging.At this moment, use pusher drive circuit 50.
This push type drive circuit 50 comprises N transistor npn npn 51,52, P transistor npn npn 53,54 and constant-current source 55,56.N transistor npn npn 51, P transistor npn npn 53 and constant-current source 55 are connected the line of the 7th power supply potential VH3 (for example 5V) and the 8th power supply potential VL3 (between the line for example-10V).The grid of N transistor npn npn 51 is connected on the input node N21.The grid of P transistor npn npn 53 is connected with its drain electrode (node N55).P transistor npn npn 53 constitutes diode.Because the drive current of transistor 51,53 is set for much larger than the current value of constant-current source 55, so N transistor npn npn 51 carries out the source output function, the current potential V55 of node N55 becomes V55=V21-VTN-|VTP|.
Constant-current source 56, N transistor npn npn 52 and P transistor npn npn 54 are connected the line of the 9th power supply potential VH4 (for example 5V) and the 10th power supply potential VL4 (between the line for example-10V).The grid of P transistor npn npn 54 is connected on the node N55.The grid of N transistor npn npn 52 is connected with its drain electrode (output node N22).The drive current of transistor 52,54 is set for much larger than the current value of constant-current source 56, so P transistor npn npn 54 carries out the source output function, the current potential V22 of output node N22 becomes V22=V55+|VTP|+VTN=V21.
That is, this push type drive circuit 50 is the level shift circuit that is made of N transistor npn npn 51, P transistor npn npn 53, constant-current source 55 to be carried out 2 grades with the level shift circuit that has used constant-current source 56, N transistor npn npn 52, P transistor npn npn 54 be connected the circuit that forms.This drive circuit 50 makes the node discharge that is pre-charged to high potential by transistor 52,54, and makes the current potential V22 of output node N22 drop to the current potential V21 that imports node N21.
When N transistor npn npn 51 is identical with 52 threshold voltage VTN, and under P transistor npn npn 53 situation identical with 54 threshold voltage VTP, this drive circuit 50 does not have bias voltage VOF.But under N transistor npn npn 51 and 52 threshold voltage VTN situation inequality and/or the threshold voltage VTP situation inequality of P transistor npn npn 53 and 54, will produce bias voltage VOF.At this moment, the difference of establishing the threshold voltage VTN of N transistor npn npn 51 and 52 is Δ VTN, and when the difference of P transistor npn npn 53 and 54 threshold voltage VTP was Δ VTP, bias voltage VOF became VOF=| Δ VTP+ Δ VTN|.This bias voltage VOF is owing to above-mentioned biasing elimination action repeatedly reduces.
In this 3rd execution mode, to compare with execution mode 1, the through current of drive circuit reduces, and power consumption reduces.
Below, will the variation of present embodiment 3 be described.The pusher drive circuit 57 of accompanying drawing 13 is to remove P transistor npn npn 53 and N transistor npn npn 52 and constitute from the pusher drive circuit 50 of accompanying drawing 12.The current potential V55 of node N55 becomes V55=V21-VTN, and output potential V22 becomes V22=V21-VTN+|VTP|.So these 57 starting stages of drive circuit have bias voltage VOF=VTN-|VTP|.This bias voltage VOF is owing to above-mentioned biasing elimination action repeatedly reduces.
The pusher drive circuit 58 of accompanying drawing 14 is to remove N transistor npn npn 51 and constant-current source 55 and the grid of P transistor npn npn 54 is formed by connecting with input node N21 from the pusher drive circuit 57 of accompanying drawing 13.Output potential V22 becomes V22=V21+|VPT|.Therefore, these 58 starting stages of drive circuit have bias voltage VOF=VTN.This bias voltage VOF is owing to above-mentioned biasing elimination action repeatedly reduces.
Accompanying drawing 15 is circuit block diagrams of structure of the drive circuit 60 of embodiments of the present invention 4 described band bias compensation functions.From accompanying drawing 15 as can be known, the drive circuit 60 of this band bias compensation function is the circuit that the towed drive circuit 62 with the pusher drive circuit 61 of band bias compensation function and band bias compensation function is connected in parallel and forms, and it is used in accompanying drawing 3 illustrated precharge potential VCP and is in the current potential occasion of 2.5V for example between 0～5V.
Any one is identical in the pusher drive circuit 61 of band bias compensation function and the pusher drive circuit of the multiple band bias compensation function shown in the execution mode 1,2.Any one is identical in the towed drive circuit 62 of band bias compensation function and the towed drive circuit of the multiple band bias compensation function shown in the execution mode 3.Switch S 4.1, in fact S4.2 is included in the drive circuit 61,62, but for convenience of explanation and understand, and it is distinguished to come with drive circuit 61 and 62 be described.
In execution mode 4, owing to make precharge potential VCP place current potential 2.5V for example between 0～5V, therefore, when being set at 0V or 5V, precharge potential VCP compares the power consumption of the current potential of setting data line 6, and reduction at high speed.
Accompanying drawing 16 is circuit block diagrams of structure of the drive circuit 65 of embodiments of the present invention 5 described band bias compensation functions.From accompanying drawing 16 as can be known, the drive circuit 65 of this band bias compensation function is to replace input node N20 and an end of the switch S 1 of the drive circuit 25 of the band bias compensation function of accompanying drawing 5 is connected to the node N60 of reference potential VR (for example 2.5V) and the circuit that constitutes.Reference potential VR can directly provide from the outside of liquid crystal indicator, also can supply with from the power circuit that is arranged on the low output impedance in the liquid crystal indicator.Input node N20 is connected switch S 3.1, the end of S3.2.Switch S 1, S2.1, S2.2, S3.1, S3.2, the control method of S4 is as enforcement mode 1 is illustrated.
Below, by means of using capacitor 27.1 and switch S 1, S2.1, S3.1 and the effect that action illustrates the drive circuit 65 of this band bias compensation function is eliminated in the 1st biasing carrying out.Here, will the output potential V22 when drive circuit 26 be described than the situation of importing V21 low bias voltage VOF of current potential.
At first, in case switch S 1, the S2.1 conducting, then the input current potential V21 of drive circuit 26 becomes reference potential VR, and the output potential V22 of drive circuit 26 and the current potential V1 of node N1 become V21-VOF=VR-VOF, and capacitor 27.1 is charged to bias voltage VOF.
Secondly, when switch S 1, when S2.1 ended, bias voltage VOF remained on capacitor 27.1.Then, when switch S 3.1 conductings, the current potential V1 of node N1 becomes VI from VR-VOF.This changing unit is delivered to the input node N21 of drive circuit 26 by capacitor 27.1.When VI＞VR-VOF, the change in voltage Δ V of the input node N21 of drive circuit 26 represents with following formula:
ΔV＝[VI-(VR-VOF)]·C1/(C0+C1) …(5)
Here, C1/ (C0+C1)=1/ (1+C0/C1), when C0＜＜during C1, then become 1/ (1+C0/C1) 1-C0/C1.When C0/C1=r, 1-C0/C1 becomes 1-r, if this formula is brought in the following formula (5), then can obtain following formula:
ΔV＝[VI-(VR-VOF)]·(1-r) …(6)
The input current potential V21 of drive circuit 26 becomes by Δ V and reference potential VR addition and the current potential VR+ Δ V that obtains, and it can be represented by following formula:
V21＝VR+ΔV＝VR+[VI-(VR-VOF)]·(1-r)
＝VR+VI-VR+VOF-[VI-(VR-VOF)]·r
＝VI+VOF-r·VOF-r·(VI-VR) …(7)
Drive circuit 25 to the band bias compensation function of accompanying drawing 5 carries out identical calculating, then can obtain:
V21＝VI+VOF-VOF·C0/(C0+C1)
＝VI+VOF-VOF·(C0/C1)/(C0/C1+1)
＝VI+VOF-VOF·r/(1+r)
VI+VOF-VOF·r·(1-r)
＝VI+VOF-VOF·(r-r
2)
If r here
2 0, then can obtain following formula:
V21VI+VOF-r·VOF …(8)
If compare formula (7) and (8), then as can be known, though the V21 of the drive circuit 65 of the band bias compensation function of accompanying drawing 16 compares the 4th [r (VI-VR)] part of only little formula (7) with the V21 of the drive circuit 25 of the band bias compensation function of accompanying drawing 5, but, by reducing r and the elimination action of repeatedly setovering, this value can be little of ignoring.
When from the tonal gradation generation circuit 20 shown in the accompanying drawing 4 when the drive circuit 25 of a plurality of band bias compensation functions provides same tonal gradation current potential VG, the load capacitance value of tonal gradation generation circuit 20 becomes the summation of the input capacitance value C0 of a plurality of drive circuits 26, and the time that tonal gradation current potential VG settles out is elongated.
Yet, if replace the drive circuit 25 of band bias compensation functions with the drive circuit 65 of the band bias compensation function of accompanying drawing 16, then owing to the input capacitance of drive circuit 26 is charged with reference potential VR, so, the load capacitance value of tonal gradation generation circuit 20 reduces significantly, and tonal gradation current potential VG was just settled out in the short time.
Accompanying drawing 17 is circuit diagrams of the variation of expression execution mode 5.With reference to accompanying drawing 17 as can be known, in the drive circuit 66 of this band bias compensation function, replace input node N20 and an end of the switch S 1 of the drive circuit 38 of the band bias compensation function of accompanying drawing 8 is connected with the node N60 of reference potential VR.Even this variation also can obtain to be equal to the effect of drive circuit 65 of the bias compensation function of accompanying drawing 16.
Though the present invention has been carried out detailed explanation, be readily appreciated that this only is for example, and can not be interpreted as qualification, the spirit and scope of the invention only limits by additional claims.
Claims (10)
1. bias compensation circuit is used for the bias voltage of compensation drive circuit, this drive circuit output with import the corresponding current potential of current potential, it is characterized in that, comprising:
The 1st～the N capacitor, 1 elementary electrode is connected with the input node of described drive circuit, and each 1 electrode is connected on another electrode of previous stage, and wherein N is the integer more than or equal to 2;
The 1st commutation circuit provides the current potential of regulation to the input node of described drive circuit, and another electrode with described the 1st capacitor is connected with the output node of described drive circuit simultaneously, and makes described the 1st capacitor charge to described bias voltage;
The 2nd commutation circuit, select the 2nd～the N capacitor separately in required time successively, 1 electrode to the capacitor of selecting provides described input current potential, simultaneously another electrode of the capacitor selected is connected to the output node of described drive circuit, and described the 1st～the N capacitor is charged to described bias voltage; And
The 3rd commutation circuit provides described input current potential to another electrode of described N capacitor.
2. bias compensation circuit as claimed in claim 1 is characterized in that,
The current potential of described regulation is described input current potential.
3. bias compensation circuit as claimed in claim 1 is characterized in that,
The current potential of described regulation is described reference potential.
4. bias compensation circuit as claimed in claim 1 is characterized in that,
After described the 2nd commutation circuit all is connected to the output node of described drive circuit with another electrode of described the 1st～the N capacitor and each inter-electrode voltage of described the 2nd～the N capacitor is reset to 0V, select described the 2nd～the N capacitor separately in required time successively, when the output node of 1 electrode of selected capacitor and described drive circuit is disconnected, described input current potential is offered 1 electrode of selected capacitor, and make described the 1st～the N capacitor charge to described bias voltage.
5. the drive circuit with the bias compensation function is characterized in that, comprising:
The drive circuit of the current potential that output is corresponding with the input current potential; And
Compensate the described bias compensation circuit of claim 1 of the bias voltage of described drive circuit.
6. the drive circuit of band bias compensation function as claimed in claim 5 is characterized in that,
Described drive circuit comprises:
The 1st transistor of the 1st conduction form, the 1st power supply potential is accepted in its drain electrode, and its source electrode is connected described output node, and its grid is connected described input node; With
The 1st constant-current source is connected between the line of described output node and the 2nd power supply potential.
7. the drive circuit of band bias compensation function as claimed in claim 6 is characterized in that,
Described drive circuit also comprises level shift circuit, be arranged between described input node and the described the 1st transistorized grid, and provide to the described the 1st transistorized grid and to make described input current potential to the current potential of described the 1st power supply potential side after only level has moved predetermined the 1st voltage
Described level shift circuit comprises:
The 2nd constant-current source is connected between the line and the described the 1st transistorized grid of the 3rd power supply potential; With
The 2nd transistor of the 2nd conduction form, its source electrode is connected with the described the 1st transistorized grid, and its drain electrode is connected with the line of the 4th power supply potential, and its grid is accepted described input current potential.
8. the drive circuit of band bias compensation function as claimed in claim 7 is characterized in that,
Described drive circuit also comprises the 3rd transistor of the 2nd conduction form, and between the described the 1st transistorized source electrode and described output node, its grid is connected with described output node,
Described level shift circuit also comprises the 4th transistor of the 1st conduction form, and between the described the 1st transistorized grid and the described the 2nd transistorized source electrode, its grid is connected with the described the 1st transistorized grid.
9. the drive circuit of band bias compensation function as claimed in claim 5 is characterized in that,
Described drive circuit comprises:
Be connected the line of the 1st power supply potential and the transistor between the described output node; Be connected the constant-current source between the line of described output node and the 2nd power supply potential; And control described transistorized grid potential so that the current potential of the described output node differential amplifier circuit consistent with the current potential of described input current potential.
10. a liquid crystal indicator is characterized in that, comprising:
The drive circuit of the described band bias compensation of claim 5 function; With
Change the liquid crystal cells of its light transmittance according to the output potential of the drive circuit of described band bias compensation function.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003082580 | 2003-03-25 | ||
| JP82580/2003 | 2003-03-25 | ||
| JP82580/03 | 2003-03-25 | ||
| JP193015/2003 | 2003-07-07 | ||
| JP2003193015A JP4159935B2 (en) | 2003-03-25 | 2003-07-07 | Offset compensation circuit, drive circuit with offset compensation function using the same, and liquid crystal display device |
| JP193015/03 | 2003-07-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1538617A true CN1538617A (en) | 2004-10-20 |
| CN1303756C CN1303756C (en) | 2007-03-07 |
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ID=32993022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200410031747XA Expired - Lifetime CN1303756C (en) | 2003-03-25 | 2004-03-25 | Offset compensation circuit and drive circuit and liquid crystal display device using it |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6930529B2 (en) |
| JP (1) | JP4159935B2 (en) |
| KR (1) | KR100543227B1 (en) |
| CN (1) | CN1303756C (en) |
| DE (1) | DE102004013139B4 (en) |
| TW (1) | TWI243536B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101282109B (en) * | 2007-04-02 | 2013-06-12 | 冲电气工业株式会社 | Arrangement for canceling offset |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007116493A (en) * | 2005-10-21 | 2007-05-10 | Oki Electric Ind Co Ltd | Offset canceller |
| KR100790259B1 (en) * | 2005-12-14 | 2008-01-02 | 매그나칩 반도체 유한회사 | Analog digital converter, cmos image sensor having the same and method for removing analog offset |
| US7514978B2 (en) * | 2006-05-08 | 2009-04-07 | Mellanox Technologies Ltd. | Terminated input buffer with offset cancellation circuit |
| JP2009284150A (en) | 2008-05-21 | 2009-12-03 | Panasonic Corp | Offset canceling circuit and display |
| JP2010134107A (en) * | 2008-12-03 | 2010-06-17 | Seiko Epson Corp | Integrated circuit device, electrooptical device, and electronic device |
| JP2011244677A (en) * | 2010-04-23 | 2011-12-01 | Rohm Co Ltd | Control circuit for switching power supply, and switching power supply, light-emitting device and electronic apparatus with the same |
| KR102193688B1 (en) * | 2014-02-05 | 2020-12-21 | 삼성전자주식회사 | Buffer circuit having an amplifier offset compensation and source driving circuit including the same |
| CN111243507B (en) * | 2018-11-29 | 2022-07-22 | 乐金显示有限公司 | Pixel sensing device and organic light emitting display device including the same |
| WO2024141888A1 (en) * | 2022-12-28 | 2024-07-04 | 株式会社半導体エネルギー研究所 | Semiconductor device and display device |
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| US4644304A (en) * | 1981-08-17 | 1987-02-17 | The Regents Of The University Of Calif. | Switched-capacitor pseudo-n-path filter |
| US4543534A (en) * | 1984-05-04 | 1985-09-24 | The Regeants Of University Of Calif. | Offset compensated switched capacitor circuits |
| US4707624A (en) * | 1986-09-10 | 1987-11-17 | National Semiconductor Corp. | Offset cancellation scheme for a differential reset stabilized latch |
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| US4942367A (en) * | 1989-09-29 | 1990-07-17 | General Electric Company | Auto-zeroing switched-capacitance buffer amplifiers with minus-unity voltage gain |
| JPH03139908A (en) | 1989-10-25 | 1991-06-14 | Olympus Optical Co Ltd | Source-follower circuit |
| IT1249299B (en) * | 1991-04-30 | 1995-02-22 | Sgs Thomson Microelectronics | INTEGRATED CIRCUIT WITH TRIMMABLE PASSIVE COMPONENTS |
| JP3277056B2 (en) * | 1993-12-09 | 2002-04-22 | シャープ株式会社 | Signal amplification circuit and image display device using the same |
| US5504444A (en) * | 1994-01-24 | 1996-04-02 | Arithmos, Inc. | Driver circuits with extended voltage range |
| US5825230A (en) * | 1996-02-01 | 1998-10-20 | University Of Waterloo | Amplifier-less low power switched-capacitor techniques |
| US5796300A (en) * | 1996-02-14 | 1998-08-18 | Pacesetter, Inc. | Switched-capacitor amplifier offset voltage compensation circuit |
| JP3031312B2 (en) * | 1997-09-11 | 2000-04-10 | 日本電気株式会社 | Driver circuit, liquid crystal driving semiconductor device, and driving method thereof |
| JP3998343B2 (en) | 1998-10-05 | 2007-10-24 | 三菱電機株式会社 | Offset voltage compensation circuit |
| US6169427B1 (en) * | 1998-12-10 | 2001-01-02 | National Semiconductor Corporation | Sample and hold circuit having single-ended input and differential output and method |
| US6288669B1 (en) * | 1999-07-15 | 2001-09-11 | Daramana G. Gata | Switched capacitor programmable gain and attenuation amplifier circuit |
| GB0029245D0 (en) * | 2000-11-30 | 2001-01-17 | Imperial College | Self-compensating buffer amplifier |
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| US6459078B1 (en) * | 2000-12-04 | 2002-10-01 | Pixel Devices International, Inc. | Image sensor utilizing a low FPN high gain capacitive transimpedance amplifier |
| JP4861566B2 (en) * | 2001-05-08 | 2012-01-25 | 富士通セミコンダクター株式会社 | Switched capacitor filter circuit |
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-
2003
- 2003-07-07 JP JP2003193015A patent/JP4159935B2/en not_active Expired - Lifetime
-
2004
- 2004-03-03 TW TW093105487A patent/TWI243536B/en not_active IP Right Cessation
- 2004-03-17 DE DE102004013139A patent/DE102004013139B4/en not_active Expired - Lifetime
- 2004-03-23 KR KR1020040019630A patent/KR100543227B1/en active IP Right Grant
- 2004-03-23 US US10/806,376 patent/US6930529B2/en not_active Expired - Lifetime
- 2004-03-25 CN CNB200410031747XA patent/CN1303756C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101282109B (en) * | 2007-04-02 | 2013-06-12 | 冲电气工业株式会社 | Arrangement for canceling offset |
Also Published As
| Publication number | Publication date |
|---|---|
| US6930529B2 (en) | 2005-08-16 |
| US20040189369A1 (en) | 2004-09-30 |
| KR20040084718A (en) | 2004-10-06 |
| JP2004350256A (en) | 2004-12-09 |
| DE102004013139A1 (en) | 2004-10-21 |
| TW200501556A (en) | 2005-01-01 |
| JP4159935B2 (en) | 2008-10-01 |
| CN1303756C (en) | 2007-03-07 |
| TWI243536B (en) | 2005-11-11 |
| KR100543227B1 (en) | 2006-01-20 |
| DE102004013139B4 (en) | 2008-03-13 |
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