CN1536578A - Operation method of non-volatile memory unit array - Google Patents
Operation method of non-volatile memory unit array Download PDFInfo
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Abstract
The invention provides a nonvolatile storage cell array operating method, applied to operating NAND storage cell array, where each storage cell has a charge immersing layer. When operating the array, it uses F-N tunneling effect to erase the whole storage cell array and uses thermal electric hole-injecting effect to code a single bit in a single storage cell. With the F-N tunneling effect, its electron injecting efficiency is high, thus able to reduce the current of the storage cell when erasing and at the same time enhance operating speed. Moreover, the current consumption is low, able to effectively reduce the power loss of the whole chip.
Description
Technical field
The invention relates to the method for operating of a kind of Nonvolatile storage unit array (Non-Volatile MemoryArray), and particularly relevant for two of a kind of single memory cells (1 Cell, 2 Bits) but can erasing and program read-only memory (Electrically Erasable ProgrammableRead Only Memory, EEPROM) array operating method by electricity of storing.
Background technology
Can erase and but program read-only memory has the actions such as depositing in, read, erase that can carry out repeatedly data by electricity in the non-volatility memorizer, and the advantage that the data that deposit in also can not disappear after outage, thus become personal computer and electronic equipment a kind of storage component part of extensively adopting.
But typically can erase and the polysilicon making floating boom utmost point (Floating Gate) and control grid (Control Gate) of program read-only memory by electricity to mix.When storer carried out sequencing (Program), the electronics that injects the floating boom utmost point can be uniformly distributed among the whole floating polysilicon grid layer.Yet, when the tunnel oxide defectiveness of floating polysilicon grid layer below exists, just cause the loss of the electronics of device storage easily, influence the fiduciary level of device.
So, but in order to solve the problem of program read-only memory device creepage of can electricity erasing, and adopting a charge immersing layer to replace the floating polysilicon grid, the material of this charge immersing layer for example is a silicon nitride.This charge immersing layer one deck monox respectively arranged up and down usually, and form a kind of silicon oxide/silicon nitride/silicon oxide (ONO) composite bed that comprises at interior stacking-type (Stacked) grid structure.But for this kind can electricity erase and program read-only memory for, because silicon nitride has the characteristic of catching electronics and electric hole, and itself can not conduct electricity, and is less for the susceptibility of defective in the tunnel oxide, and the phenomenon that lose in electronics that device stores and electric hole is difficult for taking place.
And, but this kind can electricity erase and program read-only memory when carrying out sequencing, can make the source/drain region of stacked gate first side have higher voltage, and in the charge immersing layer of the source/drain region of approaching first side, deposit electronics in; And also can make the source/drain region of stacked gate second side have higher voltage, and in the charge immersing layer of the source/drain region of approaching second side, deposit electronics in.So,, can have two groups of electronics, single group's electronics among the single charge immersing layer or not have electronics by the voltage that is applied on the source/drain regions that changes grid and its both sides.Therefore, but this kind can erase and program read-only memory can write four kinds of states among single storage unit by electricity, be the non-volatility memorizer of two of a kind of single memory cells (2 bits/cell).
Generally speaking, but this kind can electricity erase and program read-only memory utilizes the channel hot electron injection way (Channel Hot-Electron CHE), makes electronics iunjected charge immersed layer to carry out sequencing.And after sequencing, owing on the charge immersing layer of drain side (or source side), have net negative charge, so can make the start voltage (V of storage unit
T) rise.And these electronics can stop one section long time (for example in 85 ℃, the residence time was above about 10 years) in charge immersing layer, except that unintentional it are erased.When carrying out erase operation for use, then utilize band that the band hot hole is injected that (Band-to-Band Hot Hole Injection) pattern makes electric hole inject in the immersed layer combine near drain side (or source side) and with the electronics that is stored in this side or electric charge offsets and reaches the effect of erasing.After erasing, the combined or payment owing to the negative charge on the charge immersing layer that originally is present in drain side (or source side) is so can make the start voltage (V of storage unit
T) descend and become erased status.
Yet, but above-mentioned can electricity erasing and program read-only memory is to use channel hot electron to carry out sequencing, so the efficient that its electronics injects is very low.Therefore, in the process of sequencing, need to apply high voltage so that bigger electric current to be provided, and by to increase the speed of sequencing.Yet, when the voltage that uses raises, the high leakage current and the low sequencing efficient that will be caused because of punch-through effect (Punch-through), and cause the fiduciary level (Reliability) of electron device to reduce, particularly the size when storage component part is more little, the high leakage current that punch-through effect (Punch-through) is caused and the situation of low sequencing efficient will be serious more, and the degree that meeting limiting device size is dwindled.
Summary of the invention
In view of this, a purpose of the present invention is exactly in that a kind of Nonvolatile storage unit array operating method is provided, and can reduce memory cell current, and improves the operating speed of storage component part.
Another object of the present invention is providing a kind of Nonvolatile storage unit array operating method exactly, can be that unit carries out sequencing with single (Bit), byte (Byte), joint district (Sector).
For reaching above-mentioned purpose, the invention provides a kind of Nonvolatile storage unit array operating method, this Nonvolatile storage unit array comprises the plurality of memory cells row, and the storage unit series connection in each column of memory cells is connected in first and selects transistor AND gate second to select between the transistor; Each storage unit comprises substrate, source area, drain region, charge immersing layer and grid at least; Plural number character line is arranged in parallel at line direction, and connects the grid with the storage unit of delegation; The plural number up line connects the transistorized source electrode of each first selection respectively; Plural number bit line down connects each second selection transistor drain respectively; First selects gate line to connect with first of delegation selects transistorized grid, and second selects gate line to connect with second of delegation selects transistorized grid; The method is when carrying out erase operation for use, on character line, apply first voltage, apply second voltage in the substrate of storage unit, wherein a voltage difference of first voltage and second voltage is enough to make electronics to inject the charge storing unit immersed layer, to carry out erasing of whole storage cell array.When carrying out programming operations, on the selected character line that storage unit coupled, apply tertiary voltage, apply the 4th voltage on the non-selected character line, to open the channel of storage unit, apply the 5th voltage in selected up line, non-selected up line applies the 6th voltage with following bit line, to utilize the source side position of hot hole injection effect sequencing storage unit.When carrying out read operation, on the selected character line that storage unit coupled, apply the 7th voltage, apply the 8th voltage on the non-selected character line, to open the channel of storage unit, apply the 9th voltage in selected following bit line, non-selected up line applies the tenth voltage with following bit line, with the source side position of reading cells.
The method of operating of above-mentioned non-volatility memorizer, also be included on the selected character line that storage unit coupled and apply tertiary voltage, apply the 4th voltage on the non-selected character line, to open the channel of storage unit, apply the 5th voltage in selected following bit line, non-selected bit line down and up line apply the 6th voltage, to utilize a drain side position of hot hole injection effect sequencing storage unit.When carrying out read operation, on the selected character line that storage unit coupled, apply the 7th voltage, apply the 8th voltage on the non-selected character line, to open the channel of storage unit, apply the 9th voltage in selected up line, non-selected following bit line and up line apply the tenth voltage, with the drain side position of reading cells.
The present invention proposes a kind of Nonvolatile storage unit array operating method in addition, be applicable to the operating NAND memory cell array, this method is when carrying out erase operation for use, on character line, apply first voltage, in the substrate of storage unit, apply second voltage, wherein a voltage difference of first voltage and second voltage is enough to make electronics to inject the charge storing unit immersed layer, to carry out erasing of whole storage cell array.
In the operator scheme of Nonvolatile storage unit array of the present invention, it utilizes the storage unit of F-N tunneling effect (F-N Tunneling) the whole array of erasing.Then, utilizing the hot hole injection effect is that unit carries out sequencing with the single position of single memory cell, and can the sequencing of other storage unit not impacted.Same, also can carry out read operation to the single position of single memory cell.Certainly, the sequencing of Nonvolatile storage unit array of the present invention and read operation also can be by various character lines, select the control of gate line, up line and following bit line, and with byte, save and distinguish, or block is that unit carries out sequencing and read operation.
In addition, the present invention utilizes F-N tunneling effect (F-N Tunneling) carrying out the erase operation for use of storage unit, and utilizes the hot hole injection effect to carry out the programming operations of storage unit when carrying out the operation of Nonvolatile storage unit array.Because adopt the FN-tunneling effect, its electron injection efficiency is higher, thus the memory cell current when erasing can be reduced, and can improve operating speed simultaneously.Therefore, current drain is little, can effectively reduce the power attenuation of entire chip.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborate.
Description of drawings
Fig. 1 is the electrical schematic diagram that illustrates a kind of Nonvolatile storage unit array;
Fig. 2 A to Fig. 2 D is the erase operation for use synoptic diagram that illustrates Nonvolatile storage unit array of the present invention;
Fig. 3 A to Fig. 3 D is for illustrating Nonvolatile storage unit array program operation chart of the present invention; And
Fig. 4 A to Fig. 4 D is for illustrating Nonvolatile storage unit array read operations synoptic diagram of the present invention.
Label declaration
100: substrate
102: tunnel oxide
104: charge immersing layer
106: dielectric layer
108: grid
110: source area
112: the drain region
BLD1～BLD4: following bit line
BLU1～BLU4: up line
Qa1～Qdn: storage unit
SG1, SG2: select gate line
STa1～STd1, STa2～STd2: select transistor
WL1～WLn: character line
Embodiment
Fig. 1 is the electrical schematic diagram that illustrates a kind of Nonvolatile storage unit array.Wherein, this Nonvolatile storage unit array is NAND (Sheffer stroke gate) type array.And Nonvolatile storage unit array operating method of the present invention is applicable to NAND (Sheffer stroke gate) type array.NAND array storage unit with 4 row is that example is done explanation in the present embodiment.
Please refer to Fig. 1, the Nonvolatile storage unit array comprises a plurality of selection transistor STa1～STd1 and STa2～STd2, plurality of memory cells Qa1～Qdn, plurality of word lines WL1～WLn, selects gate line SG1 and SG2.Up line BLU1～BLU4 and following bit line BLD1～BLD4.
Storage unit Qa1～Qan forms column of memory cells in the direction of row, and parallel-series is connected in to be selected between transistor STa1 and the selection transistor STa2.Storage unit Qb1～Qbn forms column of memory cells in the direction of row, and parallel-series is connected in to be selected between transistor STb1 and the selection transistor STb2.Storage unit Qc1～Qcn forms column of memory cells in the direction of row, and parallel-series is connected in to be selected between transistor STc1 and the selection transistor STc2.Storage unit Qd1～Qdn forms column of memory cells in the direction of row, and parallel-series is connected in to be selected between transistor STd1 and the selection transistor STd2.
Plural number character line is arranged in parallel at line direction, and connects the grid with the storage unit of delegation.That is the grid of the storage unit Qa1～Qd1 of first row then is coupled to pairing character line WL1.The grid of the storage unit Qa2 of secondary series～Qd2 then is coupled to pairing character line WL2.The grid of tertial storage unit Qa3～Qd3 then is coupled to pairing character line WL3.The grid of the storage unit Qa4～Qd4 of the 4th row then is coupled to pairing character line WL4.The rest may be inferred, and the grid of the storage unit Qan～Qdn of n row then is coupled to pairing character line WLn.
Select the grid of transistor STa1～STd1 then to be coupled to selection gate line SG1.Select the source electrode of transistor STa1～STd1 to be coupled to up line BLU1～BLU4 respectively.Select the grid of transistor STa2～STd2 then to be coupled to selection gate line SG2.Select the drain electrode of transistor STa2～STd2 to be coupled to down bit line BLD1～BLD4 respectively.
Then please refer to table one and Fig. 2 A to Fig. 2 D, Fig. 3 A to Fig. 3 D, Fig. 4 A to Fig. 4 D, to understand the operator scheme of Nonvolatile storage unit array of the present invention, it comprises (the Erase that erases, Fig. 2 A to Fig. 2 D), sequencing (Program, Fig. 3 A to Fig. 3 D) with data read operator schemes such as (Read, Fig. 4 A to Fig. 4 D).Be that example is done explanation with storage unit Qb2 shown in Figure 1 in following explanation, Fig. 2 B and Fig. 2 D, Fig. 3 B and Fig. 3 D, Fig. 4 B and Fig. 4 D then illustrate the operator scheme of single Nonvolatile storage unit.
Table one
| Erase | Sequencing | Read | ||||
| ????(1) | ????(2) | The drain side position | The source side position | The drain side position | The source side position | |
| Selected character line WL2 | ????+Vge | ????-Vge | ??-Vgp | ??-Vgp | ??+Vcc | ??+Vcc |
| Non-selected character line WL1, WL3, WL4 ... WLn | ????+Vge | ????-Vge | ??+Vg | ??+Vg | ??+Vg | ??+Vg |
| Selected up line BLU2 | ????0 | Float | ??0 | ??+Vsp | ??+Vsr | ??0 |
| Non-selected up line BLU1, BLU3, BLU4 | ????0 | Float | ??0 | ??0 | ??0 | ??0 |
| Selected bit line BLD2 down | ????0 | Float | ??+Vdp | ??0 | ??0 | ??+Vdr |
| Non-selected bit line BLD1, BLD3, BLD4 down | ????0 | Float | ??0 | ??0 | ??0 | ??0 |
| Select gate line SG1 | ????Vst | Float | ??Vst | ??Vst | ??Vst | ??Vst |
| Select gate line SG2 | ????Vdt | Float | ??Vdt | ??Vdt | ??Vdt | ??Vdt |
| Substrate | ????-Vb | ????+Vb | ??0 | ??0 | ??0 | ??0 |
As shown in Table 1, erasing method of the present invention explains for example for whole storage cell array is erased.The erase operation for use of certain Nonvolatile storage unit array of the present invention also can be by each character line control, and with the joint district or block is that unit erases.
Erasing method of the present invention can be divided into two kinds, please be simultaneously with reference to Fig. 2 A and Fig. 2 B, and it is in order to illustrate first kind of erasing method of the present invention.When storage unit is erased, on all character line WL1 to WLn (grid 108), apply bias voltage+Vge, it for example is about 0 volt to 20 volts, applies bias voltage-Vb in substrate 100, it for example is 0 volt to-20 volts.In selecting gate line SG1 to apply bias voltage+Vst, it for example is about 5 volts, and in selecting gate line SG2 to apply bias voltage+Vdt, it for example is about 5 volts.Up line BLU2 (source electrode 110) and following bit line BLD2 (drain electrode 112) apply 0 volt of bias voltage respectively.So the voltage difference (0 volt to 40 volts) that puts between grid 108 and the substrate 100 is enough to set up a big electric field between grid 108 and substrate 100, and utilized F-N tunneling effect (F-N Tunneling) that electronics is passed in the tunnel oxide 102 iunjected charge immersed layers 104 by channel, shown in Fig. 2 B.After erasing, owing on charge immersing layer 104, have net negative charge, so can make the start voltage (V of storage unit
T) rise.
Please be simultaneously with reference to Fig. 2 C and Fig. 2 D, it is in order to illustrate second kind of erasing method of the present invention.When whole memory unit is erased, on all character line WL1 to WLn (grid 108), apply bias voltage-Vge, it for example is about 0 volt to-20 volts.Apply bias voltage+Vb in substrate 100, it for example is 0 volt to 20 volts.Select gate line SG1, select gate line SG2, up line BLU2 (source electrode 110) and following bit line BLD2 (drain electrode 112) for floating.Make the voltage difference (0 volt to-40 volts) that puts between grid 108 and the substrate 100 be enough between grid 108 and substrate 100, set up a big electric field, and utilized F-N tunneling effect (F-N Tunneling) that electronics is passed in the dielectric layer 106 iunjected charge immersed layers 104 by grid 108, shown in Fig. 2 D.After erasing, owing on charge immersing layer 104, have net negative charge, so can make the start voltage (V of storage unit
T) rise.
Please when programming operations is carried out in storage unit Qb2 drain side position, apply bias voltage-Vgp on selected character line WL2 (grid 108) simultaneously with reference to Fig. 3 A and Fig. 3 B, it for example is about 0 volt to-15 volts.Apply bias voltage Vg on other not selected character line WL1, WL3～WLn, it for example is about 10 volts, to open the channel region of storage unit.In selecting gate line SG1 to apply bias voltage+Vst, it for example is about 5 volts, opening the channel of selecting transistor STa1～STd1, and up line BLU1～BLU4 is electrically connected respectively with the source electrode of storage unit Qa1～Qd1.In selecting gate line SG2 to apply bias voltage+Vdt, it for example is about 5 volts, opening the channel of selecting transistor STa2～STd2, and make down bit line BLD1～BLD4 respectively with the drain electrode electric connection of storage unit Qan～Qdn.Selected bit line BLD2 down (drain electrode 112) applies bias voltage Vdp, and it for example is about 5 volts, and the non-selected voltage of bit line BLD1, BLD3, BLD4 down then is 0 volt.Up line BLU1～BLU4 (source electrode 110) voltage is 0 volt.Under this kind bias condition, the overlay region of grid 108 and drain electrode 112 produces the phenomenon of the degree of depth vague and general (Deep Depletion), and owing to high electric field perpendicular to tunnel oxide, and make the electric hole of close drain side to enter (hot hole injection effect (Hot HoleInjection)) in the charge immersing layer 104 through the energy barrier of tunnel oxide, shown in Fig. 3 B.After sequencing, the electric hole that is injected into owing to the negative charge on the charge immersing layer 104 that originally is present in drain side neutralizes, so can make the start voltage (V of storage unit
T) descend.
When programming operations is carried out in storage unit Qb2 drain side position, share storage unit Qa2, the Qc2 of same character line WL2, the drain side position of Qd2, because bit line BLD1, BLD3, BLD4 are all 0 volt down, therefore can be by sequencing.
Same, please when programming operations is carried out in storage unit Qb2 source side position, on character line WL2 (grid 108), apply bias voltage-Vgp simultaneously with reference to Fig. 3 C and Fig. 3 D, it for example is about 0 volt to-15 volts.Apply bias voltage Vg on other not selected character line WL1, WL3～WLn, it for example is about 10 volts, to open the channel region of storage unit.In selecting gate line SG1 to apply bias voltage+Vst, it for example is about 5 volts, opening the channel of selecting transistor STa1～STd1, and up line BLU1～BLU4 is electrically connected respectively with the source electrode of storage unit Qa1～Qd1.In selecting gate line SG2 to apply bias voltage+Vdt, it for example is about 5 volts, opening the channel of selecting transistor STa2～STd2, and make down bit line BLD1～BLD4 respectively with the drain electrode electric connection of storage unit Qan～Qdn.Apply bias voltage Vdp on the up line BLU2 (source electrode 110), it for example is about 5 volts, and the voltage of non-selected up line BLU1, BLU3, BLU4 then is 0 volt.Following bit line BLD1～BLD4 (drain electrode 112) voltage is 0 volt.Under this kind bias condition, the overlay region of grid 108 and source electrode 110 produces the phenomenon of the degree of depth vague and general (Deep Depletion), and owing to high electric field perpendicular to tunnel oxide, and make the electric hole of close source side to enter (hot hole injection effect (Hot HoleInjection)) in the charge immersing layer 104 through the energy barrier of tunnel oxide, shown in Fig. 3 D.After sequencing, the electric hole that is injected into owing to the negative charge on the charge immersing layer 104 that originally is present in source side neutralizes, so can make the start voltage (V of storage unit
T) descend.
When programming operations is carried out in storage unit Qb2 source side position, share storage unit Qa2, the Qc2 of same character line WL2, the source side position of Qd2, owing to up line BLU1, BLU3, BLU4 are all 0 volt, therefore can be by sequencing.
And in the above description, though the single position with single memory cell in the memory element array is that unit carries out sequencing, yet the sequencing of Nonvolatile storage unit array of the present invention also can be passed through each character line, select the control of gate line, up line and following bit line, and with byte, joint district, or block is that unit carries out sequencing.
Please be simultaneously with reference to Fig. 4 A and Fig. 4 B, when the data of reading cells Qb2 source side position, in selecting gate line SG1 to apply bias voltage+Vst, it for example is about 5 volts, opening the channel of selecting transistor STa1～STd1, and up line BLU1～BLU4 is electrically connected respectively with the source electrode of storage unit Qa1～Qd1.In selecting gate line SG2 to apply bias voltage+Vdt, it for example is about 5 volts, opening the channel of selecting transistor STa2～STd2, and make down bit line BLD1～BLD4 respectively with the drain electrode electric connection of storage unit Qan～Qdn.Apply the bias voltage Vdr about 1.5 volts on following bit line BLD2 (drain electrode 112), the non-selected voltage of bit line BLD1, BLD3, BLD4 down is 0 volt.Character line WL2 (grid 108) applies the bias voltage Vcc about 3 volts, applies bias voltage Vg on other not selected character line WL1, WL3～WLn, and it for example is about 5 volts, to open the channel region of storage unit.Apply 0 volt bias voltage on up line BLU1～BLU4 (source electrode 110).Because total charge dosage is very little for the channel off and the electric current of negative storage unit on the charge immersing layer 104 at this moment, and on the charge immersing layer 104 channel of the slightly positive storage unit of total charge dosage open and electric current big, so can judge that the numerical information that is stored in this storage unit is " 1 " or " 0 " by the channel switch/channel current size of storage unit.
Please be simultaneously with reference to Fig. 4 C and Fig. 4 D, when the data of reading cells Qb2 drain side position, in selecting gate line SG1 to apply bias voltage+Vst, it for example is about 5 volts, opening the channel of selecting transistor STa1～STd1, and up line BLU1～BLU4 is electrically connected respectively with the source electrode of storage unit Qa1～Qd1.In selecting gate line SG2 to apply bias voltage+Vdt, it for example is about 5 volts, opening the channel of selecting transistor STa2～STd2, and make down bit line BLD1～BLD4 respectively with the drain electrode electric connection of storage unit Qan～Qdn.Apply the bias voltage Vsr about 1.5 volts on up line BLU2 (source electrode 110), the voltage of non-selected up line BLU1, BLU3, BLU4 is 0 volt.Character line WL2 (grid 108) applies bias voltage Vcc, and it for example is about 3 volts.Apply bias voltage Vg on other not selected character line WL1, WL3～WLn, it for example is about 5 volts, to open the channel region of storage unit.Apply 0 volt bias voltage on following bit line BLD1～BLD4 (drain electrode 110).Because total charge dosage is very little for the channel off and the electric current of negative storage unit on the charge immersing layer 104 at this moment, and on the charge immersing layer 104 channel of the slightly positive storage unit of total charge dosage open and electric current big, so can judge that the numerical information that is stored in this storage unit is " 1 " or " 0 " by the channel switch/channel current size of storage unit.
And in the above description, though the single position with single memory cell in the memory element array is that unit carries out read operation, yet the read operation of Nonvolatile storage unit array of the present invention also can pass through each character line, select the control of gate line, up line and following bit line, and read with byte, joint district, or block is the data of unit.
In the operator scheme of Nonvolatile storage unit array of the present invention, it utilizes the storage unit of F-N tunneling effect (F-N Tunneling) the whole array of erasing.Then, utilizing the hot hole injection effect is that unit carries out sequencing with the single position of single memory cell, and can the sequencing of other storage unit not impacted.Same, also can carry out read operation to the single position of single memory cell.Certainly, the sequencing of Nonvolatile storage unit array of the present invention and read operation also can pass through each character line, select the control of gate line, up line and following bit line, and with byte, joint district, or block is that unit carries out sequencing and read operation.
In addition, the present invention utilizes F-N tunneling effect (F-N Tunneling) carrying out the erase operation for use of storage unit, and utilizes the hot hole injection effect to carry out the programming operations of storage unit when carrying out the operation of Nonvolatile storage unit array.Because adopt the FN-tunneling effect, its electron injection efficiency is higher, thus the memory cell current when erasing can be reduced, and can improve operating speed simultaneously.Therefore, current drain is little, can effectively reduce the power attenuation of entire chip.
Though the present invention with a preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (31)
1, a kind of Nonvolatile storage unit array operating method, this Nonvolatile storage unit array comprises the plurality of memory cells row, and respectively those storage unit series connection in this column of memory cells are connected between one first selection transistor AND gate, the one second selection transistor; Respectively this storage unit comprises tool one substrate, one source pole district, a drain region, a charge immersing layer and a grid at least; Plural number character line is arranged in parallel at line direction, and connects this grid with those storage unit of delegation; The plural number up line connects the transistorized source electrode of each those first selection respectively; Plural number bit line down connects each those second selection transistor drain respectively; One first selection gate line connects the transistorized grid of those first selections with delegation, and one second selects those the second selections transistorized grid of gate line connection with delegation; It is characterized in that this method comprises:
When carrying out erase operation for use, on those character lines, apply one first voltage, in this substrate of those storage unit, apply one second voltage, the voltage difference of this first voltage and this second voltage is enough to make electronics to inject this charge immersing layer of those storage unit, to carry out erasing of whole storage cell array;
When carrying out programming operations, on selected this character line that this storage unit coupled, apply a tertiary voltage, apply one the 4th voltage on non-selected those character lines, to open the channel of those storage unit, apply one the 5th voltage in this selected up line, non-selected those up lines and those bit line down apply one the 6th voltage, to utilize the one source pole side position of this storage unit of hot hole injection effect sequencing; And
When carrying out read operation, on selected this character line that this storage unit coupled, apply one the 7th voltage, apply one the 8th voltage on non-selected those character lines, to open the channel of those storage unit, apply one the 9th voltage in selected this time bit line, non-selected those up lines and those bit line down apply 1 the tenth voltage, to read this source side position of this storage unit.
2, the method for operating of non-volatility memorizer as claimed in claim 1 is characterized in that also comprising:
On selected this character line that this storage unit coupled, apply this tertiary voltage, apply the 4th voltage on non-selected those character lines, to open the channel of those storage unit, apply the 5th voltage in selected this time bit line, non-selected those following bit lines and those up lines apply the 6th voltage, to utilize a drain side position of this storage unit of hot hole injection effect sequencing.
3, the method for operating of non-volatility memorizer as claimed in claim 2 is characterized in that also comprising:
When carrying out read operation, on selected this character line that this storage unit coupled, apply the 7th voltage, apply the 8th voltage on non-selected those character lines, to open the channel of those storage unit, apply the 9th voltage in this selected up line, non-selected those following bit lines and those up lines apply the tenth voltage, to read this drain side position of this storage unit.
4, the method for operating of non-volatility memorizer as claimed in claim 1 is characterized in that this voltage difference is about 0 volt to-40 volts.
5, the method for operating of non-volatility memorizer as claimed in claim 1 is characterized in that this first voltage is about 0 volt to-20 volts.
6, the method for operating of non-volatility memorizer as claimed in claim 1 is characterized in that this second voltage is about 0 volt to 20 volts.
7, the method for operating of non-volatility memorizer as claimed in claim 1 is characterized in that this tertiary voltage is about 0 volt to-15 volts.
8, the method for operating of non-volatility memorizer as claimed in claim 1 is characterized in that the 4th voltage is about 0 volt to 10 volts.
9, the method for operating of non-volatility memorizer as claimed in claim 1 is characterized in that the 5th voltage is about 0 volt to 10 volts.
10, the method for operating of non-volatility memorizer as claimed in claim 1 is characterized in that the 6th voltage is about 0 volt to 10 volts.
11, the method for operating of non-volatility memorizer as claimed in claim 1 is characterized in that the 7th voltage is about 0 volt to 10 volts.
12, the method for operating of non-volatility memorizer as claimed in claim 1 is characterized in that the 8th voltage is about 0 volt to 10 volts.
13, the method for operating of non-volatility memorizer as claimed in claim 1 is characterized in that the 9th voltage is about 0 volt to 5 volts.
14, the method for operating of non-volatility memorizer as claimed in claim 1 is characterized in that the tenth voltage is about 0 volt to 5 volts.
15. Nonvolatile storage unit array operating method, be applicable to the operating NAND memory cell array, this memory cell array comprises the plurality of memory cells row, and respectively those storage unit series connection in this column of memory cells are connected between one first selection transistor AND gate, the one second selection transistor; Respectively this storage unit comprises tool one substrate, one source pole district, a drain region, a charge immersing layer and a grid at least; Plural number character line is arranged in parallel at line direction, and connects this grid with those storage unit of delegation; The plural number up line connects the transistorized source electrode of each those first selection respectively; Plural number bit line down connects each those second selection transistor drain respectively; One first selection gate line connects the transistorized grid of those first selections with delegation, and one second selects those the second selections transistorized grid of gate line connection with delegation, it is characterized in that this method comprises:
When carrying out erase operation for use, on those character lines, apply one first voltage, in this substrate of those storage unit, apply one second voltage, one voltage difference of this first voltage and this second voltage is enough to make electronics to inject this charge immersing layer of those storage unit, to carry out erasing of whole storage cell array.
16, the method for operating of non-volatility memorizer as claimed in claim 15 is characterized in that comprising:
When carrying out programming operations, on selected this character line that this storage unit coupled, apply a tertiary voltage, apply one the 4th voltage on non-selected those character lines, to open the channel of those storage unit, apply one the 5th voltage in this selected up line, non-selected those up lines and those bit line down apply one the 6th voltage, to utilize the one source pole side position of this storage unit of hot hole injection effect sequencing.
17, the method for operating of non-volatility memorizer as claimed in claim 15 is characterized in that also comprising:
When carrying out programming operations, on selected this character line that this storage unit coupled, apply this tertiary voltage, apply the 4th voltage on non-selected those character lines, to open the channel of those storage unit, apply the 5th voltage in selected this time bit line, non-selected those following bit lines and those up lines apply the 6th voltage, to utilize a drain side position of this storage unit of hot hole injection effect sequencing.
18, the method for operating of non-volatility memorizer as claimed in claim 15 is characterized in that also comprising:
When carrying out read operation, on selected this character line that this storage unit coupled, apply one the 7th voltage, apply one the 8th voltage on non-selected those character lines, to open the channel of those storage unit, apply one the 9th voltage in selected this time bit line, non-selected those up lines and those bit line down apply 1 the tenth voltage, to read this source side position of this storage unit.
19, the method for operating of non-volatility memorizer as claimed in claim 15 is characterized in that also comprising:
When carrying out read operation, on selected this character line that this storage unit coupled, apply the 7th voltage, apply the 8th voltage on non-selected those character lines, to open the channel of those storage unit, apply the 9th voltage in this selected up line, non-selected those following bit lines and those up lines apply the tenth voltage, to read this drain side position of this storage unit.
20, the method for operating of non-volatility memorizer as claimed in claim 15 is characterized in that this voltage difference is about 0 volt to-40 volts.
21, the method for operating of non-volatility memorizer as claimed in claim 15 is characterized in that this first voltage is about 0 volt to 20 volts.
22, the method for operating of non-volatility memorizer as claimed in claim 15 is characterized in that this second voltage is about 0 volt to-20 volts.
23, the method for operating of non-volatility memorizer as claimed in claim 16 is characterized in that this tertiary voltage is about 0 volt to-15 volts.
24, the method for operating of non-volatility memorizer as claimed in claim 16 is characterized in that the 4th voltage is about 0 volt to 10 volts.
25, the method for operating of non-volatility memorizer as claimed in claim 16 is characterized in that the 5th voltage is about 0 volt to 10 volts.
26, the method for operating of non-volatility memorizer as claimed in claim 16 is characterized in that the 6th voltage is about 0 volt to 10 volts.
27, the method for operating of non-volatility memorizer as claimed in claim 18 is characterized in that the 7th voltage is about 0 volt to 10 volts.
28, the method for operating of non-volatility memorizer as claimed in claim 18 is characterized in that the 8th voltage is about 0 volt to 10 volts.
29, the method for operating of non-volatility memorizer as claimed in claim 18 is characterized in that the 9th voltage is about 0 volt to 5 volts.
30, the method for operating of non-volatility memorizer as claimed in claim 18 is characterized in that the tenth voltage is about 0 volt to 5 volts.
31, a kind of Nonvolatile storage unit array operating method, this Nonvolatile storage unit array comprises the plurality of memory cells row, and respectively those storage unit series connection in this column of memory cells are connected between one first selection transistor AND gate, the one second selection transistor; Respectively this storage unit comprises tool one substrate, one source pole district, a drain region, a charge immersing layer and a grid at least; Plural number character line is arranged in parallel at line direction, and connects this grid with those storage unit of delegation; The plural number up line connects the transistorized source electrode of each those first selection respectively; Plural number bit line down connects each those second selection transistor drain respectively; It is characterized in that this method comprises:
When carrying out erase operation for use, inject this charge immersing layer of those storage unit with electronics, to carry out erasing of whole storage cell array; And
When carrying out programming operations, utilize a side position of electric this storage unit of hole injection effect sequencing.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031091008A CN100437829C (en) | 2003-04-03 | 2003-04-03 | Operation method of non-volatile memory unit array |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031091008A CN100437829C (en) | 2003-04-03 | 2003-04-03 | Operation method of non-volatile memory unit array |
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| CN1536578A true CN1536578A (en) | 2004-10-13 |
| CN100437829C CN100437829C (en) | 2008-11-26 |
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| CNB031091008A Expired - Fee Related CN100437829C (en) | 2003-04-03 | 2003-04-03 | Operation method of non-volatile memory unit array |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461428C (en) * | 2005-04-15 | 2009-02-11 | 株式会社东芝 | Non-volatile semiconductor memory device |
| CN101361136B (en) * | 2005-12-20 | 2011-07-06 | 美光科技公司 | Nand architecture memory devices and operation |
| CN102280137A (en) * | 2010-06-08 | 2011-12-14 | 奇景光电股份有限公司 | Memory unit and related memory apparatus thereof |
| CN101461011B (en) * | 2006-05-11 | 2012-09-05 | 美光科技公司 | Nand architecture memory devices and operation |
| CN105518795A (en) * | 2013-09-13 | 2016-04-20 | 株式会社东芝 | Semiconductor memory device and memory system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5386132A (en) * | 1992-11-02 | 1995-01-31 | Wong; Chun C. D. | Multimedia storage system with highly compact memory device |
| JP3303789B2 (en) * | 1998-09-01 | 2002-07-22 | 日本電気株式会社 | Flash memory and its writing / erasing method |
-
2003
- 2003-04-03 CN CNB031091008A patent/CN100437829C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461428C (en) * | 2005-04-15 | 2009-02-11 | 株式会社东芝 | Non-volatile semiconductor memory device |
| CN101361136B (en) * | 2005-12-20 | 2011-07-06 | 美光科技公司 | Nand architecture memory devices and operation |
| CN101461011B (en) * | 2006-05-11 | 2012-09-05 | 美光科技公司 | Nand architecture memory devices and operation |
| CN102280137A (en) * | 2010-06-08 | 2011-12-14 | 奇景光电股份有限公司 | Memory unit and related memory apparatus thereof |
| CN102280137B (en) * | 2010-06-08 | 2013-07-10 | 奇景光电股份有限公司 | Memory unit and related memory apparatus thereof |
| CN105518795A (en) * | 2013-09-13 | 2016-04-20 | 株式会社东芝 | Semiconductor memory device and memory system |
| CN105518795B (en) * | 2013-09-13 | 2019-08-13 | 东芝存储器株式会社 | Semiconductor storage and storage system |
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| CN100437829C (en) | 2008-11-26 |
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