CN1536577A - Sensing circuit of single bit line semiconductor memory element - Google Patents
Sensing circuit of single bit line semiconductor memory element Download PDFInfo
- Publication number
- CN1536577A CN1536577A CNA031105181A CN03110518A CN1536577A CN 1536577 A CN1536577 A CN 1536577A CN A031105181 A CNA031105181 A CN A031105181A CN 03110518 A CN03110518 A CN 03110518A CN 1536577 A CN1536577 A CN 1536577A
- Authority
- CN
- China
- Prior art keywords
- electrically connected
- data line
- module
- line
- sensing circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Read Only Memory (AREA)
Abstract
The invention provides a sensing circuit, to sense logic data, and a memory unit is connected to a bit line, and the sensing circuit contains a first precharge module connected to the bit line and to precharge; a select module connected between the bit line and a first data line and to transmit signal and isolate capacitor; a second precharge module connected to the first data line and to precharge; a first voltage hold module connected to the first data line and to hold the signal of the first data line at high-voltage level; an isolate module connected between the first data line and a second data line and to transmit signal and isolate capacitor; and a third precharge module connected to the second data line and to precharge.
Description
Technical field
The invention provides a kind of sensing circuit (Sense Out Circuit), refer to especially a kind ofly be used in the semiconductor memory component of single bit line and include the sensing circuit that a voltage is kept module (Keeper).
Background technology
In present various electronic products on the market, storer always is one of wherein very important and indispensable element.Storer can be divided into volatile memory and nonvolatile memory two big classes according to the difference of storage data mode, wherein volatile memory is meant the data storage device that the numerical data that is stored in this storer promptly can be vanished from sight after the supply of cutting off the electricity supply, the advantage of volatile memory is that its access speed is fast, be commonly used to as processing unit at a high speed and the impact damper between other circuit, but volatile memory but has and can't continue to possess data under the state of supply of cutting off the electricity supply, for example DRAM, products such as SDRAM all belong to a kind of of volatile memory.Nonvolatile memory then refers to be stored in the data storage device that the numerical data in this storer still can continue to preserve after the supply of cutting off the electricity supply, the advantage of nonvolatile memory is that promptly it can continue to possess data under the state of supply of cutting off the electricity supply, shortcoming then is that its access speed is generally not quick like volatile memory, then belongs to the category of nonvolatile memory as products such as ROM, flash memories.
The field of memory application is very extensive, except the function of performance in general PC as data storage device, maturation day by day along with the Information technology industry, above-mentioned storer miscellaneous is all applied in large quantities as notebook computer, personal digital assistant (Personal DigitalAssistant, PDA), in the middle of the electronic product of mobile phone, digital camera etc., with instrument as above-mentioned various electronic products storage numerical datas.
In general, the storer that is arranged in the electronic product can carry out following several main operator schemes according to the control signal of this electronic product, promptly writes pattern (Write Mode or ProgramMode), erasing mode (Erase Mode), reaches read mode (Read Mode).Wherein in writing pattern, this electronic product can write numerical data in this storer in the specific memory address according to the indication of above-mentioned control signal; In erasing mode, this electronic product can be removed the numerical data of being stored in the specific memory address in this storer according to the indication of above-mentioned control signal; And in read mode, this electronic product then can read out the numerical data of being stored in the specific memory address in this storer according to the indication of above-mentioned control signal.
In the middle of a storer, usually include a sensing circuit (Sense Out Circuit or SensingAmplifier), be electrically connected on the memory cell array that is used for storing numerical data in this storer, come out with the data read of specific memory address in this memory cell array being stored according to the indication of control signal.In the 158th～161 page of 1998 Symposium on VLSI Circuits Digest of Technical Papers, promptly disclosed the structure of a sensing circuit, see also Fig. 1, the circuit diagram of the sensing circuit of the single bit line ROM (read-only memory) (Single Bit Line ROM) of demonstration prior art among Fig. 1.In Fig. 1, this ROM (read-only memory) includes a sensing circuit 10 and a memory cell array 20, and wherein memory cell array 20 includes a plurality of memory cells 22, and the address of memory cell 22 is via many character lines (Word Line) WL
1～WLn and multiple bit lines BL
1～BLm defines, that is the infall of each bar character line and each bit lines all has a memory cell 22 and is electrically connected to this character line and this bit line.Among Fig. 1, memory cell 22 is a NMOS electric crystal, and its drain electrode is electrically connected on this bit line, and its gate pole is electrically connected on this character line, and its source electrode is ground connection then.
Next will be with above-mentioned bit line BL
1Among～the BLm wherein one be example (bit line BL for example
1) describe bit line BL
1Be electrically connected on sensing circuit 10, sensing circuit 10 includes one first pre-charge module 12, is electrically connected on bit line BL
1, be used for pairs of bit line BL
1Carry out pre-charge, the first pre-charge module 12 is a NMOS electric crystal herein, and its drain electrode is electrically connected on bit line BL
1, its gate pole is electrically connected on a control signal Y1b, and its source electrode is ground connection then, is used for bit line BL
1Be precharged to 0V; One selects module 14, be electrically connected between a bit line Y1b and the data line DL, be used for the signal of bit line Y1b being sent to data line DL according to complementary control signal Y1 and Y1b, select the transmission gate (TransmissionGate) of module 14 herein, and control its switching by control signal Y1 and Y1b for being formed by a NMOS electric crystal and a PMOS electric crystal; One second pre-charge module 16, be used for data line DL is carried out pre-charge, the second pre-charge module 16 is a PMOS electric crystal herein, and its drain electrode is electrically connected on data line DL, its gate pole is electrically connected on a control signal PRE, and its source electrode then is electrically connected on power supply supply voltage V
DD, be used for data line DL is precharged to V
DDAnd a sensing breech lock module 18, as shown in Figure 1, being electrically connected on data line DL, digital signal and this digital signal of breech lock of being used on the sensing data lines DL produce an output signal to go up in an output signal line OUT.
Though note that in the preceding paragraph only with a bit lines BL
1Be the example explanation, but in practical application, have multiple bit lines usually respectively by selecting module 14 to be electrically connected on same the data line DL, as shown in Figure 1.
Next ROM (read-only memory) in the key diagram 1 is utilized the flow process of sensing circuit 10 reading of data.When this ROM (read-only memory) is desired to read the numerical data of being stored in the memory cell array 20, its control module (not being shown among Fig. 1) can utilize control signal control the first pre-charge module 12 with will with address corresponding bit line (the bit line BL for example that desired to read
1) be precharged to 0V, utilize control signal Y1 and Y1b to open again and select module 14.Next, utilize control signal PRE to control the second pre-charge module 16 with data line DL and bit line BL again
1Be precharged to V
DDAt last, its control module can input to noble potential and the corresponding character line in address (the character line WL for example that desires to read
1), (be character line WL at this moment with the memory cell 22 that will be selected
1And bit line BL
1The memory cell 22 of infall) in the numerical data of being stored, by bit line BL
1, data line DL, and sensing breech lock module 18 export output signal line OUT to.
Yet the sensing circuit 10 among Fig. 1 but has following great defective.At first, when the numerical data of being stored in the memory cell 22 is logical value " 0 ", memory cell 22 is by the state of sequencing in low critical voltage (Low Threshold Voltage), this moment is if desire reads out the logical value " 0 " of being stored in this memory cell 22 the bit line BL that is selected
1And data line DL must be charged to V earlier
DD, again via the memory cell 22 that is unlocked be connected to ground the path be discharged to 0V, just can finish the action of reading.Because bit line BL
1Be electrically connected on very a large amount of memory cell 22 and data line DL also is electrically connected on many selection modules 14, so bit line BL
1And data line DL is all representing very large stray capacitance because of having very long layout figure.So in the middle of the process that reads logical value " 0 ", no matter be that the second pre-charge module 16 or the memory cell 22 that is selected must pairs of bit line BL
1And the huge capacitor charge and discharge of data line DL, and this will cause the speed of this ROM (read-only memory) reading of data to be very restricted.While pairs of bit line BL
1The huge electric capacity that reaches data line DL discharges and recharges, and also will cause very a large amount of dynamic power (Active Power) consumption.
Summary of the invention
Therefore fundamental purpose of the present invention is to provide a kind of and is used in the semiconductor memory component of a single bit line and includes the sensing circuit that a voltage is kept module (Keeper), to solve above-mentioned existing problem.
According to an aspect of the present invention, a kind of sensing circuit of semiconductor memory component is provided, be used for the logical data stored in the memory cell of this semiconductor memory component of sensing, this memory cell is electrically connected on a bit line, this sensing circuit includes: one first pre-charge module, be electrically connected on this bit line, be used for this bit line is carried out pre-charge; One selects module, is electrically connected between this bit line and one first data line, is used for according to one first control signal the signal of this bit line being sent to this first data line, and isolates the electric capacity of this bit line and this first data line; One second pre-charge module is electrically connected on this first data line, is used for this first data line is carried out pre-charge; One first voltage is kept module, is electrically connected on this first data line, when being used for logical value storage in this memory cell " 1 ", the signal of this first data line is maintained at high-voltage level; One isolation module is electrically connected between this first data line and one second data line, is used for according to one second control signal the signal of this first data line being sent to this second data line, and isolates the electric capacity of this first data line and this second data line; And one the 3rd pre-charge module, be electrically connected on this second data line, be used for this second data line is carried out pre-charge.
Sensing circuit of the present invention utilizes the design of a selection module and an isolation module, during logical value storage in this memory cell " 1 ", stray capacitance between stray capacitance between one bit line and one first data line and this first data line and one second data line is kept apart, and utilize a voltage to keep module the signal on the data line is maintained at high-voltage level, like this then parasitic capacitance effect on the data line will be generally not huge like the sensing circuit of prior art, and then can reduce the time of reading of data institute palpus.
Description of drawings
Fig. 1 is the circuit diagram of the sensing circuit of existing single bit line ROM (read-only memory).
Fig. 2 is the circuit diagram of the sensing circuit of single bit line semiconductor memory component of the present invention.
Fig. 3 for the sensing circuit among Fig. 2 at the sequential chart that reads logical data " 1 ".
Fig. 4 for the sensing circuit among Fig. 2 at the sequential chart that reads logical data " 0 ".
Embodiment
See also Fig. 2, show the circuit diagram of the sensing circuit of single bit line semiconductor memory component of the present invention among Fig. 2.In Fig. 2, this semiconductor memory component includes a sensing circuit 30 and a memory cell array 50, wherein the memory cell array 20 among Fig. 1 of memory cell array 50 and above-mentioned prior art is identical, memory cell array 50 includes a plurality of memory cells 52, and the address of memory cell 52 is via many character line WL
1～W1n and multiple bit lines BL
1-BLm defines, that is the infall of each bar character line and each bit lines all has a memory cell 52 and is electrically connected to this character line and this bit line.Memory cell 52 is a NMOS electric crystal in Fig. 2, and its drain electrode is electrically connected on this bit line, and its gate pole is electrically connected on this character line, and its source electrode is ground connection then.
Next will be with above-mentioned bit line BL
1Among～the BLm wherein one be example (bit line BL for example
1) describe.Among Fig. 2, bit line BL
1Be electrically connected on sensing circuit 30, sensing circuit 30 includes one first pre-charge module 32, is electrically connected on bit line BL
1, be used for pairs of bit line BL
1Carry out pre-charge; One selects module 34, is electrically connected on bit line BL
1And one first data line DL
1Between, be used for according to one first control signal Y1 bit line BL
1Signal be sent to the first data line DL
1, and isolate bit line BL
1And the first data line DL
1Electric capacity; One second pre-charge module 36 is electrically connected on the first data line DL
1, be used for to the first data line DL
1Carry out pre-charge; One first voltage is kept module (Keeper) 38, is electrically connected on the first data line DL
1, be used in the memory cell 52 desiring to read during logical value storage " 1 ", with the first data line DL
1Signal be maintained at high-voltage level; One isolation module 40 is electrically connected on the first data line DL
1And one second data line DL
2Between, be used for according to one second control signal SAIB the first data line DL
1Signal be sent to the second data line DL
2, and isolate the first data line DL
1And the second data line DL
2Electric capacity; And one the 3rd pre-charge module 42, be electrically connected on the second data line DL
2, be used for to the second data line DL
2Carry out pre-charge.
Though note that in first previous paragraphs only with a bit lines BL
1Be the example explanation, but have multiple bit lines in actual applications usually respectively by selecting module 34 to be electrically connected on same first data line DL
1On, as shown in Figure 2.
As shown in Figure 2, in present embodiment, the first pre-charge module 32 is a NMOS electric crystal, and its drain electrode is electrically connected on bit line BL
1, its gate pole is electrically connected on the inversion signal Y1b of the first control signal Y1, and its source electrode is ground connection then, and 32 meetings of the first pre-charge module are opened with pairs of bit line BL according to the control of the inversion signal Y1b of the first control signal Y1
1Carry out pre-charge.Selecting module 34 is a NMOS electric crystal, and its drain electrode is electrically connected on the first data line DL
1, its gate pole is electrically connected on the first control signal Y1, and its source electrode then is electrically connected on bit line BL
1The second pre-charge module 36 is a PMOS electric crystal, and its drain electrode is electrically connected on the first data line DL
1, its gate pole is electrically connected on the second control signal SAIB, and its source electrode then is electrically connected on power supply supply voltage V
DD, the second pre-charge module 36 can be opened according to the control of the second control signal SAIB with to the first data line DL
1Carry out pre-charge.Isolation module 40 is a NMOS electric crystal, and its drain electrode is electrically connected on the second data line DL
2, its gate pole is electrically connected on the second control signal SAIB, and its source electrode then is electrically connected on the first data line DL
1And the 3rd pre-charge module 42 is a PMOS electric crystal, and its drain electrode is electrically connected on the second data line DL
2, its gate pole is electrically connected on the second control signal SAIB, and its source electrode then is electrically connected on power supply supply voltage V
DD, 42 of the 3rd pre-charge modules can be opened according to the control of the second control signal SAIB with to the second data line DL
2Carry out pre-charge.
And for example shown in Figure 2, in the present embodiment, first voltage is kept 38 of modules and is included a PMOS electric crystal 54, and its source electrode is electrically connected on power supply supply voltage V
DD, its drain electrode is electrically connected on the first data line DL
1And a NAND logic gate 56, including two input ends and an output terminal, this two input end is electrically connected on the first data line DL
1, this output terminal is electrically connected on the gate pole of PMOS electric crystal 54.Keeping under the configuration of module 38, when being positioned at the first data line DL as the first above-mentioned voltage
1On signal be one near power supply supply voltage V
DDMagnitude of voltage the time because NAND logic gate 56 can be judged as logical value " 1 " with this magnitude of voltage, so the output terminal of NAND logic gate 56 can output logic value " 0 " (being 0V), therefore PMOS electric crystal 54 then can be opened, and makes power supply supply voltage V
DDCan continue to pass through the passage of PMOS electric crystal 54 to the first data line DL
1Charge, and make the first data line DL
1On signal level off to V
DDAnd be maintained at high-voltage level.And when being positioned at the first data line DL
1On signal be one during near the magnitude of voltage of ground value (0V) because NAND logic gate 56 can be judged as logical value " 0 " with this magnitude of voltage, (be V so the output terminal of NAND logic gate 56 is understood output logic value " 1 "
DD), therefore PMOS electric crystal 54 then can close, and making the voltage of winning keep module 38 can be to the first data line DL
1Have any impact.
Faster for the speed that makes sensing circuit 30 reading of data of the present invention, sensing circuit 30 also can include one second voltage in addition and keep a module 44 and a waveform-shaping module (Waveform ReshapeModule) 46, as shown in Figure 2.Wherein second voltage is kept module 44 and is electrically connected on the second data line DL
2, be used in the memory cell 52 desiring to read during logical value storage " 1 ", with the second data line DL
2Signal be maintained at high-voltage level.Waveform-shaping module 46 then is electrically connected on the second data line DL
2, be used for the sensing second data line DL
2Signal to produce an output signal in an output signal line OUT.
As shown in Figure 2, in present embodiment, second voltage is kept the configuration of module 44 and function and first voltage, and to keep module 38 identical, includes a PMOS electric crystal 58, and its source electrode is electrically connected on power supply supply voltage V
DD, its drain electrode is electrically connected on the second data line DL
2And a NAND logic gate 60, including two input ends and an output terminal, this two input end is electrically connected on the second data line DL
2, this output terminal is electrically connected on the gate pole of PMOS electric crystal 58.Keeping under the configuration of module 44, when being positioned at the second data line DL as the first above-mentioned voltage
2On signal be one near power supply supply voltage V
DDMagnitude of voltage the time because NAND logic gate 60 can be judged as logical value " 1 " with this magnitude of voltage, so the output terminal of NAND logic gate 60 can output logic value " 0 " (being 0V), therefore PMOS electric crystal 58 then can be opened, and makes power supply supply voltage V
DDCan continue to pass through the passage of PMOS electric crystal 58 to the second data line DL
2Charge, and make the second data line DL
2On signal level off to V
DDAnd be maintained at high-voltage level.And when being positioned at the second data line DL
2On signal be one during near the magnitude of voltage of ground value (0V) because NAND logic gate 60 can be judged as logical value " 0 " with this magnitude of voltage, (be V so the output terminal of NAND logic gate 60 is understood output logic value " 1 "
DD), therefore PMOS electric crystal 58 then can be closed, and making that second voltage is kept module 44 can be to the second data line DL
2Have any impact.
And for example shown in Figure 2, in present embodiment, waveform-shaping module 46 includes one first reverser 62, includes an input end and an output terminal, and the input end of first reverser 62 is electrically connected on the second data line DL
2One second reverser 64 includes an input end and an output terminal, and the input end of second reverser 64 is electrically connected on output signal line OUT; One the one NMOS electric crystal 66, its drain electrode are electrically connected on the second data line DL
2, its gate pole is electrically connected on the output terminal of second reverser 64; And one the 2nd NMOS electric crystal 68, its drain electrode is electrically connected on output signal line OUT, and its gate pole is electrically connected on the output terminal of first reverser 62.Under the configuration as above-mentioned waveform-shaping module 46, when waveform-shaping module 46 was enabled (Enable), it can be positioned at the second data line DL by sensing
2On signal, and via in the waveform-shaping module 46 by two reversers 62,64 and two NMOS electric crystals, 66,68 circuit configurations of being formed, on output signal line OUT, produce correspond to the output signal of the numerical data of being stored in the memory cell 52 desiring to read.
Note that according to the needs on the circuit design waveform-shaping module 46 also can include one the 3rd NMOS electric crystal 70, its drain electrode is electrically connected on the source electrode of a NMOS electric crystal 66, and its gate pole is electrically connected on one the 3rd control signal SAE, and its source electrode is ground connection then; And one the 4th NMOS electric crystal 72, its bushing is electrically connected on the source electrode of the 2nd NMOS electric crystal 68, and its gate pole is electrically connected on the 3rd control signal SAE, and its source electrode is ground connection also.The function of the 3rd NMOS electric crystal 70 and the 4th NMOS electric crystal 72 is to open and close its passage according to the 3rd control signal SAE herein, so that waveform-shaping module 46 enables (Enable) and forbids (Disable), words in other words, the 3rd and the 4th NMOS electric crystal 70,72 are used for the startup of control waveform Shaping Module 46 functions.Waveform-shaping module 46 also can include one the 4th pre-charge module 74, be electrically connected on output signal line OUT, be used for output signal line OUT is carried out pre-charge, the 4th pre-charge module 74 is a PMOS electric crystal herein, its drain electrode is electrically connected on output signal line OUT, its gate pole is electrically connected on the second control signal SAIB, and its source electrode then is electrically connected on power supply supply voltage V
DD, the 4th pre-charge module 74 can be opened so that output signal line OUT is carried out pre-charge according to the control of the second control signal SAIB.
At last, as shown in Figure 2, waveform-shaping module 46 includes a PMOS electric crystal 76 in addition, and its drain electrode is electrically connected on output signal line OUT, its gate pole is electrically connected on the output terminal that second voltage is kept the NAND logic gate 60 of module 44, and its source electrode then is electrically connected on power supply supply voltage V
DDUnder this configuration, when being positioned at the second data line DL
2On signal be one near power supply supply voltage V
DDMagnitude of voltage the time because NAND logic gate 60 can be judged as logical value " 1 " with this magnitude of voltage, so the output terminal of NAND logic gate 60 can output logic value " 0 " (being 0V), therefore PMOS electric crystal 76 then can be opened, and makes power supply supply voltage V
DDCan continue output signal line OUT to be charged, and make signal on the output signal line OUT level off to V by the passage of PMOS electric crystal 76
DDAnd be maintained at high-voltage level.And when being positioned at the second data line DL
2On signal be one during near the magnitude of voltage of ground value (0V) because NAND logic gate 60 can be judged as logical value " 0 " with this magnitude of voltage, (be V so the output terminal of NAND logic gate 60 is understood output logic value " 1 "
DD), therefore PMOS electric crystal 76 then can close, and makes second voltage keep module 44 and can not have any impact to output signal line OUT.
Next see also Fig. 2, Fig. 3 and Fig. 4 describing the principle of operation of sensing circuit 30 of the present invention in detail, show sensing circuit 30 of the present invention one of them memory cell 52 (character line WL for example in reading memory cell array 50 among Fig. 3
1And bit line BL
1The memory cell 52 of infall) in stored numerical data " 1 " time, the sequential chart of each control signal and signal wire among Fig. 2 then shows the sequential chart when reading the numerical data " 0 " of being stored in this memory cell 52 among Fig. 4.List the first control signal Y1, the second control signal SAIB, the 3rd control signal SAE, bit line BL among Fig. 3 and Fig. 4 respectively in regular turn
1Signal, the first data line DL
1Signal, the second data line DL
2Signal, and the signal of output signal line OUT.
To note that in order illustrating and relatively convenience, respectively control signal Y1, SAIB, the SAE of three actives to be positioned on the same time shaft in the middle of Fig. 3 and Fig. 4, and the signal BL that other are passive
1, DL
1, DL
2, and OUT be positioned on another time shaft.And in the present embodiment, the inversion signal Y1b of the first above-mentioned control signal Y1 is owing to be complementary with the first control signal Y1, so need not list among Fig. 3 and Fig. 4 character line WL again
1The signal and the first control signal Y1 be synchronously, so also in Fig. 3 and Fig. 4, do not list.
Operating principle when next seeing also Fig. 3 with the numerical data " 1 " that sensing circuit 30 of the present invention is described is stored in the memory cell 52 that reads memory cell array 50, this moment, this memory cell 52 was in high critical voltage state.Before beginning to read action, the first control signal Y1 be logical value " 0 " (therefore be 0V, and its inversion signal Y1b is logical value " 1 ", i.e. V
DD), the second control signal SAIB is that logical value " 0 ", the 3rd control signal SAE are logical value " 0 " and character line WL
1Signal and first control signal synchronously so be logical value " 0 ".Under this state, logic module 34 and isolation module 40 can be closed, and the first, second, third and the 4th pre-charge module 32,36,42,74 then can be unlocked, and make bit line BL
1Be precharged to 0V, and the first data line DL
1, the second data line DL
2, and output signal line OUT all be precharged to V
DD
After beginning to read action, the at first first control signal Y1 and character line WL
1Be switched to logical value " 1 " simultaneously, then the first pre-charge module 32 can be closed and select module 34 then to be unlocked, but because memory cell 52 is to be in the former closed condition that still remains in of high critical voltage state, bit line BL at this moment
1On signal can begin toward rising, yet because the effect of logic module 34, bit line BL
1On signal can only arrive (V at most
DD-V
TH) (herein for selecting the critical voltage of module 34).
Next, the second control signal SAIB will be switched to logical value " 1 ", then second, third, the 4th pre-charge module 36,42,74 all can be closed, isolation module 40 then is unlocked, this moment is owing to be positioned at the first data line DL
1And the second data line DL
2On signal be less than V
DDBut approach V
DD, then first and second voltage is kept module 38,44 and will be brought into play function, begins the first data line DL
1And the second data line DL
2On signal gradually toward V
DDDirection promote, simultaneously owing to select module 34 and isolation module 40 all to be in state of saturation (Saturation), it is very little to flow through this two the magnitude of current, and makes and select module 34 and isolation module 40 to show the characteristic of big resistance, thereby can be with bit line BL
1With the first data line DL
1The electric capacity and the first data line DL
1With the second data line DL
2Electric capacity keep apart bit line BL so then
1On huge stray capacitance will be difficult for and the first data line DL
1Carry out charge distributing, make first and second voltage keep module 38,44 and more can bring into play its function.Similarly, second voltage is kept module 44 and also can output signal line OUT be maintained V by the effect of PMOS electric crystal 76 at this moment
DD
At last, as the second data line DL
2On signal arrive suitable numerical value after, the 3rd control signal will be switched to logical value " 1 ", then waveform-shaping module 46 will begin action owing to the unlatching of the 3rd and the 4th NMOS electric crystal, after by effect by two reversers 62,64 and two NMOS electric crystals 66,68 circuit configurations of being formed, the second data line DL
2And the signal on the output signal line OUT will be stabilized in V apace
DD, so then can on output signal line OUT, read out the output signal of logical value " 1 ", and finish the action of data read.After data read finished, the first control signal Y1, the second control signal SAIB and the 3rd control signal SAE can be switched back logical value " 0 " in regular turn, to prepare data read action next time.
Operating principle when next seeing also Fig. 4 with the numerical data " 0 " that sensing circuit 30 of the present invention is described is stored in the memory cell 52 that reads memory cell array 50, this moment, this memory cell 52 was in low critical voltage state.Before beginning to read action, the first control signal Y1 is that logical value " 0 " (so its inversion signal Y1b is logical value " 1 "), the second control signal SAIB are that logical value " 0 ", the 3rd control signal SAE are logical value " 0 " and character line WL
1Signal and first control signal synchronously so be logical value " 0 ".Under this state, select module 34 and isolation module 40 to be closed, the first, second, third and the 4th pre-charge module 32,36,42,74 then can be unlocked, and makes bit line BL
1Be precharged to 0V, and the first data line DL
1, the second data line DL
2, and output signal line OUT all be precharged to V
DD
After beginning to read action, the at first first control signal Y1 and character line WL
1Be switched to logical value " 1 " simultaneously, then the first pre-charge module 32 can be closed and select module 34 then to be unlocked, owing to memory cell 52 is to be in low critical voltage state so it will be unlocked and begin by its passage pairs of bit line BL
1Discharge, at this moment bit line BL
1On signal can begin toward rising, yet owing to select the effect of module 34, bit line BL
1On signal can only arrive (V at most
DD-V
TH) (being for selecting the critical voltage of module 34) herein.
Next, the second control signal SAIB will be switched to logical value " 1 ", then second, third, the 4th pre-charge module 36,42,74 all can be closed, isolation module 40 then is unlocked, this moment is owing to be positioned at the first data line DL
1And the second data line DL
2On signal less than V
DDAnd approach 0V, then first and second voltage is kept module 38,44 and will can not brought into play function, and the first data line DL
1And the second data line DL
2On signal can because with bit line BL
1On huge stray capacitance carry out charge distributing and soon with bit line BL
1On signal Synchronization, and the memory cell opened of beginning 52 discharges, and then descend toward the direction of 0V gradually.
At last, as the second data line DL
2On signal arrive suitable numerical value after, the 3rd control signal will be switched to logical value " 1 ", then waveform-shaping module 46 will begin action owing to the unlatching of the 3rd and the 4th NMOS electric crystal, after by effect by two reversers 62,64 and two NMOS electric crystals 66,68 circuit configurations of being formed, the second data line DL
2The signal that reaches on the output signal line OUT will be stabilized in 0V apace, so then can read out the output signal of logical value " 0 " on output signal line OUT, and finish the action of data read.After data read finished, the first control signal Y1, the second control signal SAIB and the 3rd control signal SAE can be switched back logical value " 0 " in regular turn, to prepare data read action next time.
Compared to prior art, sensing circuit of the present invention is when reading logical data " 1 ", utilize a selection module and an isolation module electric capacity with a bit line and one first data line, and the electric capacity of this first data line and one second data line is kept apart, and utilize at least one voltage to keep the work of module in order to the signal on this data line is maintained at high-voltage level, and sensing circuit of the present invention is when reading logical data " 0 ", then utilize the huge stray capacitance on this bit line, make on this first data line and this second data line signal rapidly and the signal Synchronization on this bit line, the last speed of utilizing a waveform-shaping module to accelerate data sensing again is data reading speed rapidly and make sensing circuit of the present invention can have than the sensing circuit of prior art.
The above only is preferred embodiment of the present invention, and is all according to the equalization variation and modification done in claims limited range of the present invention, all belongs to the covering scope of patent of the present invention.
Claims (15)
1. the sensing circuit of a semiconductor memory component is used for the logical data stored in the memory cell of this semiconductor memory component of sensing, and this memory cell is electrically connected on a bit line, and this sensing circuit includes:
One first pre-charge module is electrically connected on this bit line, is used for this bit line is carried out pre-charge;
One selects module, is electrically connected between this bit line and one first data line, is used for according to one first control signal the signal of this bit line being sent to this first data line, and isolates the electric capacity of this bit line and this first data line;
One second pre-charge module is electrically connected on this first data line, is used for this first data line is carried out pre-charge;
One first voltage is kept module, is electrically connected on this first data line, when being used for logical value storage in this memory cell " 1 ", the signal of this first data line is maintained at high-voltage level;
One isolation module is electrically connected between this first data line and one second data line, is used for according to one second control signal the signal of this first data line being sent to this second data line, and isolates the electric capacity of this first data line and this second data line; And
One the 3rd pre-charge module is electrically connected on this second data line, is used for this second data line is carried out pre-charge.
2. sensing circuit as claimed in claim 1, wherein this first voltage is kept module and is included:
One PMOS electric crystal, its source electrode are electrically connected on power supply supply voltage, and its drain electrode is electrically connected on this first data line; And
One NAND logic gate includes two input ends and an output terminal, and this two input end is electrically connected on this first data line, and this output terminal is electrically connected on the gate pole of this PMOS electric crystal.
3. sensing circuit as claimed in claim 1, it includes one second voltage in addition and keeps module, is electrically connected on this second data line, when being used for logical value storage in this memory cell " 1 ", the signal of this second data line is maintained at high-voltage level.
4. sensing circuit as claimed in claim 3, wherein this second voltage is kept module and is included:
One PMOS electric crystal, its source electrode are electrically connected on power supply supply voltage, and its drain electrode is electrically connected on this second data line; And
One NAND logic gate includes two input ends and an output terminal, and this two input end is electrically connected on this second data line, and this output terminal is electrically connected on the gate pole of this PMOS electric crystal.
5. sensing circuit as claimed in claim 4, it includes a waveform-shaping module in addition, is electrically connected on this second data line, is used for the signal of this second data line of sensing to produce an output signal at an output signal line.
6. sensing circuit as claimed in claim 5, wherein this waveform-shaping module includes:
One first reverser includes an input end and an output terminal, and the input end of this first reverser is electrically connected on this second data line;
One second reverser includes an input end and an output terminal, and the input end of this second reverser is electrically connected on this output signal line;
One the one NMOS electric crystal, its drain electrode are electrically connected on this second data line, and its gate pole is electrically connected on the output terminal of this second reverser; And
One the 2nd NMOS electric crystal, its drain electrode is electrically connected on this output signal line, and its gate pole is electrically connected on the output terminal of this first reverser.
7. sensing circuit as claimed in claim 6, wherein this waveform-shaping module includes in addition:
One the 3rd NMOS electric crystal, its drain electrode is electrically connected on the source electrode of a NMOS electric crystal, and its gate pole is electrically connected on one the 3rd control signal, and its source electrode is ground connection then; And
One the 4th NMOS electric crystal, its drain electrode is electrically connected on the source electrode of the 2nd NMOS electric crystal, and its gate pole is electrically connected on the 3rd control signal, and its source electrode is ground connection then.
8. sensing circuit as claimed in claim 5, wherein this waveform-shaping module includes one the 4th pre-charge module in addition, is electrically connected on this output signal line, is used for this output signal line is carried out pre-charge.
9. sensing circuit as claimed in claim 8, wherein the 4th pre-charge module is a PMOS electric crystal, and its drain electrode is electrically connected on this output signal line, and its gate pole is electrically connected on this second control signal, and its source electrode then is electrically connected on power supply supply voltage.
10. sensing circuit as claimed in claim 5, wherein this waveform-shaping module includes a PMOS electric crystal in addition, its drain electrode is electrically connected on this output signal line, its gate pole is electrically connected on the output terminal that this second voltage is kept the NAND logic gate of module, and its source electrode then is electrically connected on power supply supply voltage.
11. sensing circuit as claimed in claim 1, wherein this first pre-charge module is a NMOS electric crystal, and its drain electrode is electrically connected on this bit line, and its gate pole is electrically connected on the inversion signal of this first control signal, and its source electrode is ground connection then.
12. sensing circuit as claimed in claim 1, wherein this selection module is a NMOS electric crystal, and its drain electrode is electrically connected on this first data line, and its gate pole is electrically connected on this first control signal, and its source electrode then is electrically connected on this bit line.
13. sensing circuit as claimed in claim 1, wherein this second pre-charge module is a PMOS electric crystal, and its drain electrode is electrically connected on this first data line, and its gate pole is electrically connected on this second control signal, and its source electrode then is electrically connected on power supply supply voltage.
14. sensing circuit as claimed in claim 1, wherein this isolation module is a NMOS electric crystal, and its drain electrode is electrically connected on this second data line, and its gate pole is electrically connected on this second control signal, and its source electrode then is electrically connected on this first data line.
15. sensing circuit as claimed in claim 1, wherein the 3rd pre-charge module is a PMOS electric crystal, and its drain electrode is electrically connected on this second data line, and its gate pole is electrically connected on this second control signal, and its source electrode then is electrically connected on power supply supply voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031105181A CN100345217C (en) | 2003-04-07 | 2003-04-07 | Sensing circuit of single bit line semiconductor memory element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031105181A CN100345217C (en) | 2003-04-07 | 2003-04-07 | Sensing circuit of single bit line semiconductor memory element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1536577A true CN1536577A (en) | 2004-10-13 |
| CN100345217C CN100345217C (en) | 2007-10-24 |
Family
ID=34319701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031105181A Expired - Lifetime CN100345217C (en) | 2003-04-07 | 2003-04-07 | Sensing circuit of single bit line semiconductor memory element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100345217C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138722A (en) * | 2011-12-05 | 2013-06-05 | 联发科技股份有限公司 | Isolation cell and integrated circuit |
| CN105957552A (en) * | 2016-04-21 | 2016-09-21 | 华为技术有限公司 | Memory |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07101554B2 (en) * | 1988-11-29 | 1995-11-01 | 三菱電機株式会社 | Semiconductor memory device and data transfer method thereof |
| JPH0955088A (en) * | 1995-08-11 | 1997-02-25 | Nec Corp | Semiconductor memory |
| US5781469A (en) * | 1997-01-24 | 1998-07-14 | Atmel Corporation | Bitline load and precharge structure for an SRAM memory |
| US5870343A (en) * | 1998-04-06 | 1999-02-09 | Vanguard International Semiconductor Corporation | DRAM sensing scheme for eliminating bit-line coupling noise |
-
2003
- 2003-04-07 CN CNB031105181A patent/CN100345217C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138722A (en) * | 2011-12-05 | 2013-06-05 | 联发科技股份有限公司 | Isolation cell and integrated circuit |
| US9374089B2 (en) | 2011-12-05 | 2016-06-21 | Mediatek Inc. | Isolation cell |
| CN105957552A (en) * | 2016-04-21 | 2016-09-21 | 华为技术有限公司 | Memory |
| CN105957552B (en) * | 2016-04-21 | 2018-12-14 | 华为技术有限公司 | memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100345217C (en) | 2007-10-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5373463A (en) | Ferroelectric nonvolatile random access memory having drive line segments | |
| US5847989A (en) | Ferroelectric memory using non-remnant reference circuit | |
| EP0145488B1 (en) | Semiconductor memory device | |
| US8050092B2 (en) | NAND flash memory with integrated bit line capacitance | |
| CN102820052B (en) | SRAM multiplex machine | |
| CN1153223C (en) | Page mode erase in flash memory array | |
| CN111179982B (en) | Apparatus and method for discharging control gate after performing access operation on memory cell | |
| CN1759448A (en) | Low-voltage sense amplifier and method | |
| US8724359B2 (en) | Methods and circuits for limiting bit line leakage current in a content addressable memory (CAM) device | |
| US20140313828A1 (en) | Sharing support circuitry in a memory | |
| CN103778944A (en) | Semiconductor device | |
| US10163514B2 (en) | Methods of operating a memory during a programming operation | |
| CN114550765A (en) | Memory array and memory system | |
| US9275708B2 (en) | Row address decoding block for non-volatile memories and methods for decoding pre-decoded address information | |
| US7130233B2 (en) | Sensing circuit for single bit-line semiconductor memory device | |
| CN113053434B (en) | High-energy-efficiency TCAM based on FeFET structure and operation method thereof | |
| DE69835116T2 (en) | Content-aware storage | |
| CN100345217C (en) | Sensing circuit of single bit line semiconductor memory element | |
| JPH04155694A (en) | Semiconductor memory | |
| US6292425B1 (en) | Power saving on the fly during reading of data from a memory device | |
| US6871155B2 (en) | Sensing circuit for single bit-line semiconductor memory device | |
| Pathak et al. | A 1.8 v 64 mb 100 mhz flexible read while write flash memory [in cmos] | |
| CN100407335C (en) | Precharge and detecting circuit for differential read-only storage | |
| CN1613115A (en) | Memory controller with AC power reduction through non-return-to-idle of address and control signals | |
| KR102481452B1 (en) | NOR Type Content Addressable Memory Cell Based on Ferroelectric Element and Content Addressable Memory Including Same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20071024 |
|
| CX01 | Expiry of patent term |