CN1529243A - Method and structure for realizing router flow management chip buffer-storage management - Google Patents
Method and structure for realizing router flow management chip buffer-storage management Download PDFInfo
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Abstract
With read command being received, buffer management module determines information of data address to be accessed, and hangs up the read command. If write command has not been received before next read command is received, then the read command is written to command FIFO. With write command being received, buffer management module determines whether there is a read command hung. The write command is ensured to write data into the RAM opposite to a RAM the read command will access. Read/write commands are written into command FIFO. If there is no read command hung, then it is ensured that the write command writes data into the RAM opposite to a RAM previous write command writes data into. Then, the write command is written into command FIFO module. Based on commands in FIFO, each RAM controller reads and writes data. Two groups of RAM are used as buffer in the invention so that bandwidth is as two times of original bandwidth.
Description
Technical field:
The present invention relates to a kind of T bit core router traffic management chip cache management implementation method and structure.
Background technology:
Router is as the nucleus equipment of internet, and along with network capacity and business constantly increase fast, its interface rate is increased to OC-192 (10GBPS) from OC-48 (2.5GBPS) rapidly.And T bit router must mate with interface rate as the core of next generation network pipeline equipment, realizes that the linear speed of OC-192 (10GBPS) speed is handled.This is to the forwarding engine of total system, and cache management and queue scheduling all have very high requirement.The traffic management chip is as the acp chip of T bit router, realize traffic management to 2.5GBPS～10GBPS data, section and reorganization comprising message, metadata cache, queue management and scheduling, the management of traffic shaping etc., as seen, the traffic management chip is in core status in whole router.
The traffic management chip transmit to be handled for the high speed that realizes built-in message, and generally the Cell (elementary cell) that data message is cut into regular length handles.The traffic management chip at up direction (finger from the MAC/Framer device) to the switching network direction from MAC/Framer (media access controller/framer) chip receiving data packets, message is cut into the Cell (elementary cell) of regular length, writes in the metadata cache by Cell (elementary cell) data of caching management module after section.After finishing the protocol processes of message, according to the result of queue scheduling, Cell (elementary cell) data are read out from metadata cache, be packaged into Cframe (general switch network interface frame) and send to switching network.The traffic management chip receives the CFrame (general switch network interface frame) that sends over from switching network at down direction (referring to from switching network to the MAC/Framer direction), after peeling CFrame (general switch network interface frame) head off, Cell (elementary cell) data are written in the down buffer storage by caching management module, and Cell (elementary cell) is reassembled as complete packet, join in the down queue.According to the queue scheduling result message data is read out from down buffer storage then, finish the modification of heading after, send to MAC/Framer (media access controller/framer) chip, finish the processing procedure of data message.In this process, the traffic management chip is handled on the direction two of up-downgoings, all will carry out message to the writing and read operation of metadata cache, and the buffer memory bandwidth that provides of caching management module is necessary for 2 times of data bandwidth like this.But because the traffic management chip is that Cell (elementary cell) according to regular length carries out to the visit of data buffer memory, there is slice loss in the buffer memory bandwidth, for message length is that Cell (elementary cell) length adds one packet, realize the linear speed processing of message, the buffer memory bandwidth that caching management module provides is necessary for 4 times of data bandwidth.As seen, the increasing of data traffic, also higher to the requirement of buffer memory bandwidth.
Metadata cache can use SRAM (static readable and writable memory) or DRAM (dynamically readable and writable memory) as storer, SRAM (static readable and writable memory) design of Controller is simple, and very high readwrite bandwidth can be provided, but finite capacity, therefore the price height uses also fewer.And DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) is (by rising edge and the negative edge transmission data at clock, very high data bandwidth can be provided, huge buffer memory capacity and relatively low price, therefore its use is wider, but, when using DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) as buffer memory, controller is to the read and write access of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) time, be to send an Active (activation) order to DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) earlier, provide Bank (memory bank) address and row address, send to DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) then and read or write order, after finishing, read command also wants Precharge (desire charging) operation, after write order is finished, be to write recovery operation and Precharge (desire charging) operation.After finishing, Precharge (desire charging) (desire charging) operation just can carry out read-write operation next time.Timing parameters according to DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory), from Active (activation) order send read write command need between at regular intervals, write recovery operation and Precharge (desire charging) operation and also will take the regular hour, cause total line use ratio of DDRSDRAM (Double Data Rate synchronous dynamic readable and writable memory) very low like this.And, under the certain situation of Cell (elementary cell) length, improve bandwidth if increase DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) data-bus width simply, because the shared periodicity of bus transmitting data reduces, can cause the bandwidth availability ratio of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) lower, can not satisfy the demand of T bit router the buffer memory bandwidth.
Summary of the invention:
At the existing problem and shortage of above-mentioned ordinary router traffic management chip cache management implementation method, the purpose of this invention is to provide a kind of cache management implementation method and structure of the T of satisfying bit core router traffic management chip demand.Simultaneously, when RAM (dynamic storage) is SDRAM (synchronous dynamic readable and writable memory) or DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory), be the read-write mode of four Bank (memory bank) repeating query with its design of Controller.
The present invention is achieved in that a kind of router traffic management chip cache management implementation method, wherein, described traffic management chip adopts two groups of RAM (dynamic storage) as its buffer memory, the shared read write command FIFO of the controller of these two groups of RAM (dynamic storage) (first in first out) module said method comprising the steps of:
After caching management module is received read command, judge that by the selection administration module in it data address information of its desire visit is also with this read command hang-up, if do not receive write order before receiving read command next time, then this read command is written among the described order FIFO (first in first out); After caching management module is received write order, have or not the read command that is suspended by selecting administration module to judge, if have, determine that then this write order writes data among opposite that RAM (dynamic storage) that visits with the read command desire, and with in read write command write command FIFO together (first in first out), if do not have, determine that then this write order is among opposite that RAM (dynamic storage) that data write with last time write order write, and with in this write order write command FIFO (first in first out) module, the information that simultaneously data is write among which RAM (dynamic storage) is recorded in the described cache management data structure.
Each RAM (dynamic storage) controller reads and writes data according to the order among the FIFO (first in first out).
Further, data are the Cell (elementary cell) of fixed size.
Further, described RAM (dynamic storage) can be SRAM (static readable and writable memory), DRAM (dynamically readable and writable memory), SDRAM (synchronous dynamic readable and writable memory) or DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory).
A kind of router traffic management chip cache management structure, include caching management module, FIFO (first in first out) module, RAM (dynamic storage) and RAM (dynamic storage) controller, it is characterized in that, described RAM (dynamic storage) and RAM (dynamic storage) controller are two groups, the controller of described two RAM (dynamic storage) is connected to read write command FIFO (first in first out) module altogether, and this FIFO (first in first out) module is connected with caching management module.
Further, also be connected with the selection administration module between described caching management module and FIFO (first in first out) module; Described caching management module receives read-write requests, judge that by selecting administration module the data address information of its desire visit is also with this read command hang-up, if do not receive that before receiving read command next time write order, this read command are written in described order FIFO (first in first out) module; Described caching management module receives write order, have or not the read command that is suspended by selecting administration module to judge, if have, determine that then this write order writes data among opposite that RAM (dynamic storage) that visits with the read command desire, and with in read write command write command FIFO (first in first out) module, if do not have, determine that then this write order is among opposite that RAM (dynamic storage) that data write with last time write order write, and with in this write order write command FIFO (first in first out) module, the information that simultaneously data is write among which RAM (dynamic storage) is recorded in the described cache management data structure;
Each RAM (dynamic storage) controller reads and writes data according to the order among the FIFO (first in first out).Include caching management module, FIFO (first in first out) module, RAM (dynamic storage) and RAM (dynamic storage) controller, it is characterized in that, the controller of described two RAM (dynamic storage) is connected to read write command FIFO (first in first out) module altogether, and this FIFO (first in first out) module is connected with caching management module; Caching management module is received the data address information of judging its desire visit after the read command also with this read command hang-up, if do not have write order in certain clock period, this read command is written in described order FIFO (first in first out) module; Caching management module is received write order, judge and have or not the read command that is suspended, if have, determine that then this write order writes data among opposite that RAM (dynamic storage) that visits with the read command desire, and with in read write command write command FIFO (first in first out) module, if do not have, determine that then this write order is among opposite that RAM (dynamic storage) that data write with last time write order write, and with in this write order write command FIFO (first in first out) module, the information that data is write among which RAM (dynamic storage) returns to described caching management module simultaneously, and is recorded in the described cache management data structure.RAM (dynamic storage) controller reads and writes data according to the order among the FIFO (first in first out).
Further, described RAM (dynamic storage) can be SRAM (static readable and writable memory), DRAM (dynamically readable and writable memory), SDRAM (synchronous dynamic readable and writable memory) or DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory).
Further, the mode that described SDRAM (synchronous dynamic readable and writable memory), DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) controller writes sense data is such: controller writes four Bank (memory bank) to the data of a Cell (elementary cell) according to the mode of four Bank (memory bank) repeating query; As the same when reading, read according to the mode of four Bank (memory bank) repeating query.
The present invention adopts two groups of RAM (dynamic storage) as its buffer memory, and in the cache management data structure, increase corresponding management information, when caching management module is received read command and write order at the same time, because the address information of the existing Cell (elementary cell) that desires to read of cache management data structure, can determine Cell (elementary cell) data from which address which organizes RAM (dynamic storage) are read, like this, the Cell (elementary cell) that desires to write can be write among another group RAM (dynamic storage).The read-write operation of traffic management chip to buffer memory is evenly distributed among two groups of RAM (dynamic storage), thereby bandwidth is risen to original 2 times.
In addition, if RAM (dynamic storage) is SDRAM (synchronous dynamic readable and writable memory) or DDRSDRAM (Double Data Rate synchronous dynamic readable and writable memory), the present invention is to its controller redesign, to four Bank (memory bank) concurrent operations, its controller is according to the mode of four Bank (memory bank) repeating query, the data of a Cell (elementary cell) are write among four Bank (memory bank), thereby mask the activationary time and Precharge (desire charging) time of row address, also undertaken when reading by this mode, thereby significantly reduce the reading and writing data time, obtained high bandwidth availability ratio.
By above-mentioned 2 beneficial effects as can be seen, adopt the present invention that Cell (elementary cell) is handled, can improve the buffer memory bandwidth of router traffic management chip greatly, be more suitable in T bit router.
Description of drawings:
Below in conjunction with accompanying drawing, the present invention is made detailed description.
Fig. 1 is the structural representation of traffic management chip cache management of the present invention;
Fig. 2 shows DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) the write data mode synoptic diagram of the method for the invention;
Fig. 3 shows DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) the read data mode synoptic diagram of the method for the invention.
Embodiment:
As shown in Figure 1, the present invention manages traffic management chip buffer memory like this: because the traffic management chip is symmetrical to the read and write access of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory), utilize this characteristic, use two groups of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) as spatial cache, the two address space overlaps, its shared read write command FIFO (first in first out) module, like this, can be assigned to read-write operation equably among two groups of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory), one group of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) carries out read operation, another group DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) carries out write operation, thereby the buffer memory bandwidth of traffic management chip is doubled.Concrete grammar is as follows:
After DDRSEL receives the read command that caching management module sends, Cell (elementary cell) address information of judging its desire visit is also with this read command hang-up, if do not receive that before receiving read command next time write order, this read command are written in order FIFO (first in first out) module; The DDRSEL module is received write order, judge and have or not the read command that is suspended, if have, determine that then this write order writes data among that the opposite DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) that visits with the read command desire, and with in read write command write command FIFO together (first in first out) module, if do not have, determine that then this write order is among that opposite DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) that data write with last time write order write, and with in this write order write command FIFO (first in first out) module, the information that Cell (elementary cell) is write among which RAM (dynamic storage) is kept in the cache management data structure simultaneously.Controller Controller0, the Controller1 of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) is according to the read-write of the order in FIFO (first in first out) module Cell (elementary cell).
Above-mentioned DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) can also be RAM (dynamic storage), SRAM (static readable and writable memory), DRAM (dynamically readable and writable memory), SDRAM (synchronous dynamic readable and writable memory) etc.And DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) also has such characteristic: comprise four Bank (memory bank) on its structure, four Bank (memory bank) can concurrent operations.Like this, utilize this characteristic, to the mode of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) controller according to four Bank (memory bank) repeating query, promptly the data of a Cell (elementary cell) are write among four Bank (memory bank), after the 4th Bank (memory bank) write, the writing of first Bank (memory bank) recovered and Precharge (desire charging) finishes, can begin to read and write next Cell (elementary cell) data immediately, thereby mask the activationary time and Precharge (desire charging) time of row address, obtain high bandwidth availability ratio, as Fig. 2, shown in 3.
As shown in Figure 1, the DDRSEL resume module is to the read-write requests of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory).Because read request is determined the visit of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) promptly can specified data from which address of which group DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) read.Write request is then determined according to situation about reading by the DDRSEL module, and the result who determines is write in the corresponding cache management data structures.For realizing that the read-write of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) is distributed, the DDRSEL module is after receiving a read command, this read command can't be written among the DDR order FIFO (first in first out) immediately, but be suspended, only do not receive before receiving read command next time under the situation to the write order of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) that this read command just is written among the DDR order FIFO (first in first out); After the DDRSEL module is received a write order, then at first check the read command that whether is suspended, if the read command that is suspended is arranged, then the DDR SDRAM that will visit according to read command (Double Data Rate synchronous dynamic readable and writable memory) determines that write order writes Cell (elementary cell) among the opposite DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory); If the read command that is not suspended, then write among the DDR SDRAM opposite (Double Data Rate synchronous dynamic readable and writable memory), and the information which RAM Cell (elementary cell) is write among is kept in the cache management data structure with last write order.DDR order FIFO (first in first out) deposits the read write command to DDRSDRAM (Double Data Rate synchronous dynamic readable and writable memory), and two groups of DDR controller Controller0, Controller1 order FIFO (first in first out) that DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) is carried out read-write operation according to this.
As shown in Figure 1, caching management module, DDRSEL module, DDR Cmd FIFO (first in first out) module, two DDR and corresponding controller thereof have been the present invention includes, caching management module is connected with the DDRSEL module, DDR Cmd fifo module is connected with the DDRSEL module, and two DDR controllers all are connected with DDR CmdFIFO module.Caching management module sends read write command to the DDRSEL module, DDRSEL handles the read-write requests to DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) (double data rate synchronous dynamic readable and writable memory), by the control information in the cache management data structure in the DDRSEL module request command is handled, and the order after will handling writes in FIFO (first in first out) module RAM (dynamic storage) controller Controller0, Controller1 reads Cell (elementary cell) or write from corresponding RAM (dynamic storage) by order.
Here, the DDR readable and writable memory can also be the readable and writable memory of other classes such as common RAM (dynamic storage), SRAM (static readable and writable memory), DRAM (dynamically readable and writable memory), SDRAM (synchronous dynamic readable and writable memory) etc.
If readable and writable memory is DDR SDRAM (a Double Data Rate synchronous dynamic readable and writable memory), then also can utilize its controller that its access characteristics is designed.A read and write access is at first to send an Active (activation) order to SDRAM (synchronous dynamic readable and writable memory) or DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory), provide Bank (memory bank) address and row address, send to DDRSDRAM then and read or write order, after finishing, read command also wants Precharge (desire charging) operation, after write order is finished, be to write recovery operation and Precharge (desire charging) operation.After finishing, Precharge (desire charging) operation just can carry out read-write operation next time.Timing parameters according to DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory), from Active (activation) order send read write command need between at regular intervals, write recovery operation and Precharge (desire charging) operation and also will take the regular hour, cause total line use ratio of DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) very low like this.Because comprise four Bank (memory bank) on SDRAM (synchronous dynamic readable and writable memory), DDR SDRAM (the Double Data Rate synchronous dynamic readable and writable memory) structure, four Bank (memory bank) can concurrent operations.Utilize this characteristic, to SDRAM (synchronous dynamic readable and writable memory), DDR SDRAM (Double Data Rate synchronous dynamic readable and writable memory) controller is according to the mode of four Bank (memory bank) repeating query, promptly the data of a Cell (elementary cell) are write among four Bank (memory bank), like this, after the 4th Bank (memory bank) write, the writing of first Bank (memory bank) recovered and Precharge (desire charging) finishes, next Cell (elementary cell) data can have been begun to read and write, thereby mask the activationary time and Precharge (desire charging) time of row address, obtain high bandwidth availability ratio, as Fig. 2, shown in 3.
Claims (7)
1. router traffic management chip cache management implementation method, wherein, described traffic management chip adopts two groups of RAM as its buffer memory, and the shared read write command fifo module of the controller of these two groups of RAM said method comprising the steps of:
After caching management module is received read command, judge that by the selection administration module in it data address information of its desire visit is also with this read command hang-up, if do not receive write order before receiving read command next time, then this read command is written among the described order FIFO; After caching management module is received write order, judge and have or not the read command that is suspended, if have, determine that then this write order writes data among that the opposite RAM that visits with the read command desire, and,, determine that then this write order is among that opposite RAM that data write with last time write order write if do not have with in read write command write command FIFO together, and with in this write order write command fifo module, the information that simultaneously data is write among which RAM is recorded in the described cache management data structure.
Each RAM controller reads and writes data according to the order among the FIFO.
2. router traffic management chip cache management implementation method as claimed in claim 1 is characterized in that data are the Cell of fixed size.
3. as any one described router traffic management chip cache management implementation method of claim 1 to 3, it is characterized in that described RAM can be SRAM, DRAM, SDRAM or DDR SDRAM.
4. router traffic management chip cache management structure, include caching management module, fifo module, RAM and RAM controller, it is characterized in that, described RAM and RAM controller are two groups, the controller of described two RAM is connected to the read write command fifo module altogether, and this fifo module is connected with caching management module.
5. router traffic management chip cache management structure as claimed in claim 4 is characterized in that, also is connected with the selection administration module between described caching management module and the fifo module; Described caching management module receives read-write requests, judge that by selecting administration module the data address information of its desire visit is also with this read command hang-up, if do not receive that before receiving read command next time write order, this read command are written in the described order fifo module; Described caching management module receives write order, have or not the read command that is suspended by selecting administration module to judge, if have, determine that then this write order writes data among that the opposite RAM that visits with the read command desire, and with in the read write command write command fifo module, if do not have, determine that then this write order is among that opposite RAM that data write with last time write order write, and with in this write order write command fifo module, the information that simultaneously data is write among which RAM returns to described selection administration module, and is recorded in the described cache management data structure;
Each RAM controller reads and writes data according to the order among the FIFO.
6. as claim 4 or 5 described router traffic management chip cache management structures, it is characterized in that described RAM can be SRAM, DRAM, SDRAM or DDR SDRAM.
7. router traffic management chip cache management structure as claimed in claim 6, it is characterized in that, the mode that described SDRAM, DDR sdram controller write sense data is such: controller writes four Bank to the data of a Cell according to the mode of four Bank repeating queries; As the same when reading, read according to the mode of four Bank repeating queries.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101621469B (en) * | 2009-08-13 | 2012-01-04 | 杭州华三通信技术有限公司 | Control device and control method for accessing data messages |
| CN102385555A (en) * | 2010-08-27 | 2012-03-21 | 深圳市朗科科技股份有限公司 | Caching system and method of data caching |
| CN105718384A (en) * | 2014-12-05 | 2016-06-29 | 中兴通讯股份有限公司 | Cache configuration method and device |
| CN111261206A (en) * | 2020-01-17 | 2020-06-09 | 苏州浪潮智能科技有限公司 | Read-write method and device, electronic equipment and readable storage medium |
| CN115604198A (en) * | 2022-11-29 | 2023-01-13 | 珠海星云智联科技有限公司（Cn） | Network card controller, network card control method, equipment and medium |
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2003
- 2003-09-29 CN CN 03134731 patent/CN1232909C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101621469B (en) * | 2009-08-13 | 2012-01-04 | 杭州华三通信技术有限公司 | Control device and control method for accessing data messages |
| CN102385555A (en) * | 2010-08-27 | 2012-03-21 | 深圳市朗科科技股份有限公司 | Caching system and method of data caching |
| CN102385555B (en) * | 2010-08-27 | 2015-03-04 | 深圳市朗科科技股份有限公司 | Caching system and method of data caching |
| CN105718384A (en) * | 2014-12-05 | 2016-06-29 | 中兴通讯股份有限公司 | Cache configuration method and device |
| CN111261206A (en) * | 2020-01-17 | 2020-06-09 | 苏州浪潮智能科技有限公司 | Read-write method and device, electronic equipment and readable storage medium |
| CN111261206B (en) * | 2020-01-17 | 2022-03-08 | 苏州浪潮智能科技有限公司 | Read-write method and device, electronic equipment and readable storage medium |
| US11868620B2 (en) | 2020-01-17 | 2024-01-09 | Inspur Suzhou Intelligent Technology Co., Ltd. | Read-write method and apparatus, electronic device, and readable memory medium |
| CN115604198A (en) * | 2022-11-29 | 2023-01-13 | 珠海星云智联科技有限公司（Cn） | Network card controller, network card control method, equipment and medium |
| CN115604198B (en) * | 2022-11-29 | 2023-03-10 | 珠海星云智联科技有限公司 | Network card controller, network card control method, equipment and medium |
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| CN1232909C (en) | 2005-12-21 |
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Owner name: HUAWEI TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: GANGWAN NETWORK CO., LTD. Effective date: 20061103 |
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Owner name: HUAWEI DIGITAL TECHNOLOGY CO. Free format text: FORMER OWNER: HUAWEI TECHNOLOGY CO., LTD. Effective date: 20081010 |
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Effective date of registration: 20081010 Address after: No. 3, information road, Haidian District, Beijing Patentee after: Huawei Digit Technology Co., Ltd. Address before: Bantian HUAWEI headquarters office building, Longgang District, Shenzhen, Guangdong Patentee before: Huawei Technologies Co., Ltd. |
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Granted publication date: 20051221 Termination date: 20120929 |