CN1529217A - Clock-signal switch-over circuit - Google Patents
Clock-signal switch-over circuit Download PDFInfo
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- CN1529217A CN1529217A CNA200310101951XA CN200310101951A CN1529217A CN 1529217 A CN1529217 A CN 1529217A CN A200310101951X A CNA200310101951X A CN A200310101951XA CN 200310101951 A CN200310101951 A CN 200310101951A CN 1529217 A CN1529217 A CN 1529217A
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- clock signal
- signal
- clock
- trigger
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Abstract
The invented circuit provides function for switching between two signals of time clocks. The switching circuit includes a timing clock generator, a D type trigger and a multiplexer. The timing clock generator is utilized to generate a reference signal. Cycle of the reference signal is a lease common multiple of cycles of two timing clock signals. With control signal of system being as input signal, and with the said reference signal as timing triggering signal, the D type trigger generates a selection signal. Based on the selection signal, the multiplexer outputs timing clock signal. When switching timing clock, the target timing clock is synchronous to the switched timing signal to complete a cycle.
Description
Technical field
The present invention relates to a kind of commutation circuit, particularly a kind of clock signal commutation circuit.
Background technology
Flourish along with science and technology; computing machine has just like become one of articles for use indispensable in modern's life; the utilization rate of computing machine and the lifting of owning rate; bring up computing machine manufacturing industry and become most important in the world now star's industry; and the part of computer-internal composition product is various; relatively; also drive the manufacturing development of computer parts; because motherboard (Mother Board) is a most important spare part in the main frame; and the consumer usually can be strict especially to the quality and the stability requirement of motherboard; therefore for the manufacturing dealer of motherboard; more essential its motherboard of producing is done higher qualitative control requirement, so that the quality height to be provided; the motherboard product that stability is good.
Wherein, on the motherboard in order to the clock signal of System Operation to be provided, be to produce by a clock generator (clockgenerator), be to make in early days with oscillator (oscillator), but, usually need the output of multiple clock signal on a slice motherboard,, be integrated into the chip of exportable various frequencies gradually so these became scattered about motherboard oscillator everywhere originally afterwards.Yet when system requirements switched clock signal, known way as shown in Figure 1, was that (multiplexer MUX) 10 finishes clock signal S with one 2 pairs 1 multiplexers
1With clock signal S
2Between mutual switching.
Please refer to shown in Figure 2ly, is according to the clock signal switching sequence figure of the multiplexer of Fig. 1, supposes clock signal S
1Frequency be 200MHz, and clock signal S
2Frequency be 250MHz, when system exports a controlling signal C
1(clock signal before switching was S when desire was switched clock signal
1), controlling signal C
1Do the transition (becoming high state) of logic level in time t, the clock signal S that makes output by low state
3Will be by original clock signal S
1Become clock signal S
2
Because multiplexer 10 is a combinational logic (combinational logic) assemblies, under desirable situation, when multiplexer 10 when time t switches, the clock signal S before time t
3Be clock signal S
1Frequency of operation; Clock signal S behind the time t
3Be clock signal S
2Frequency of operation.It should be noted, as shown in the figure, at clock signal S
3To no longer keep work period of one 50% (tp＞tn) in the work period of time point t (duty cycle), this undesired clock (glitch) output, to cause, thereby influence the normal operation state of system with of the misoperation of this clock signal as numerous circuit of reference clock signal.
Summary of the invention
The purpose of this invention is to provide a kind of design of clock signal commutation circuit, make the moment that clock signal is switched, still can keep normal clock signal output.
Above-mentioned purpose of the present invention is realized by following technical scheme.
A kind of clock signal commutation circuit, in order to the mutual switching of k clock signal to be provided, wherein 2
N-1＜k≤2
n, k and n are all a natural number, and the feature of this clock signal commutation circuit is to comprise:
One clock generator, in order to produce a reference signal, wherein the cycle of this reference signal is the lowest common multiple in the cycle of this k clock signal;
N trigger is the clock trigger signals respectively with g controlling signal of the system input signal as g this trigger, and with above-mentioned reference signal, produces n selection signal, and wherein g is the natural number of 1～n; And
One multiplexer, according to this n the clock signal of selecting the signal export target, when wherein the clock signal of this target is switched be with switch before clock signal finish one-period synchronously.
Described clock signal commutation circuit is characterized in that: above-mentioned trigger is the wherein a kind of of rest-set flip-flop, JK flip-flop, master-slave mode trigger, D flip-flop, toggle flip-flop.
Described clock signal commutation circuit is characterized in that: above-mentioned trigger is that positive edge triggers trigger, negative edge triggers the wherein a kind of of trigger.
Described clock signal commutation circuit is characterized in that: above-mentioned multiplexer is 2
nTo 1 multiplexer.
A kind of clock signal commutation circuit, in order to the mutual switching of k clock signal to be provided, wherein 2
N-1＜k≤2
n, k and n are all a natural number, and this clock signal commutation circuit feature is to comprise:
One clock generator, in order to produce a reference signal, wherein the cycle of this reference signal is the lowest common multiple in the cycle of this k clock signal;
N D flip-flop is the clock trigger signals respectively with g controlling signal of the system input signal as g this D flip-flop, and with above-mentioned reference signal, produces n selection signal, and wherein g is the natural number of 1～n; And
One multiplexer, according to this n the clock signal of selecting the signal export target, when wherein the clock signal of this target is switched be with switch before clock signal finish one-period synchronously.
Described clock signal commutation circuit is characterized in that: above-mentioned D flip-flop is that positive edge triggers trigger, negative edge triggers the wherein a kind of of trigger.
Described clock signal commutation circuit is characterized in that: above-mentioned multiplexer is 2
nTo 1 multiplexer.
A kind of clock signal commutation circuit, in order to the mutual switching of two clock signals to be provided, this clock signal commutation circuit comprises:
One clock generator, in order to produce a reference signal, wherein the cycle of this reference signal is the lowest common multiple in the cycle of these two clock signals;
One D flip-flop as input signal, and is the clock trigger signals with above-mentioned reference signal with the controlling signal of system, produces one and selects signal; And
One multiplexer is selected the clock signal of signal export target according to this, when wherein the clock signal of this target is switched be with switch before clock signal finish one-period synchronously.
Described clock signal commutation circuit is characterized in that: above-mentioned D flip-flop is for positive edge triggers trigger, negative edge triggers the wherein a kind of of trigger.
Described clock signal commutation circuit is characterized in that: above-mentioned multiplexer is 2 pairs 1 multiplexers.
The design of clock signal commutation circuit of the present invention has following advantage:
(1) with the commutation circuit of commutation circuit of the present invention as clock signal, the clock signal when make switching still can be kept stable output, allows keep normal operating state with this clock signal as numerous circuit of reference clock signal.
(2) clock signal commutation circuit of the present invention has simplicity of design, is easy to advantages such as realization, alleviates the burden of motherboard circuit designers.
To specific embodiment and in conjunction with the detailed description of institute's accompanying drawing, can understand the plurality of advantages of foregoing and the present invention by following easily.
Description of drawings
Fig. 1 be one 2 pairs 1 multiplexers (multiplexer, MUX);
Fig. 2 is the clock signal switching sequence figure according to the multiplexer of Fig. 1;
Fig. 3 is the clock signal commutation circuit synoptic diagram of the preferred embodiment according to the present invention;
Fig. 4 is the output characteristics table of a D flip-flop;
Fig. 5 is the clock signal switching sequence figure according to the embodiment of the invention; And
Fig. 6 is the clock signal commutation circuit synoptic diagram according to the embodiment of the invention.
Embodiment
The invention provides a kind of commutation circuit about clock signal.In the present invention, by producing the clock signal of one-period for the lowest common multiple of clock period of desiring switching frequency, and the selection signal that cooperates trigger to produce, use the control multiplexer and export accurate clock signal.Below enumerate a preferred embodiment now with explanation the present invention, right those who are familiar with this art know that all this only is one for example, and are not in order to limit invention itself.Details are as follows for appearance within relevant this preferred embodiment.
As shown in Figure 3, be the clock signal commutation circuit synoptic diagram of preferred embodiment according to the present invention, this commutation circuit comprises: a multiplexer 20 and a D flip-flop 30.In the present embodiment, be with two clock signal (S
4With S
5) switch to example mutually, therefore, the multiplexer 20 of this commutation circuit is 2 pairs 1 multiplexers, can handle two clock signal (S
4With S
5) mutual switching, and according to selection signal C from D flip-flop 30
2, with the clock signal S of decision output
6, just when selecting signal C
2During for low state, multiplexer 20 clock signal S
4Yet, when selecting signal C
2During for high state, 20 of multiplexers change clock signal S
5
D flip-flop 30 is to comprise an input end (D) and an output terminal (Q), in addition, has more a clock trigger signals input end (CK), and its output characteristics table can be referring to shown in Figure 4.In the present embodiment, be to select positive edge to trigger the trigger of (positive edge trigger), therefore, only just the input signal of input end (D) is done sampling (sampling) action, and export former input state by output terminal (Q) in the moment that the clock trigger signals rises.In addition, also can select negative edge to trigger the trigger of (negative edge trigger), difference only is the asynchronism(-nization) of taking a sample not influence category of the present invention.
In the present invention, D flip-flop 30 be controlling signal SC with system as input signal, the controlling signal of also switching simultaneously as clock signal, and with a reference signal CF as the clock trigger signals, select signal C to produce one
2, use the output of control multiplexer 20 and select.Wherein above-mentioned reference signal CF is that the clock generator by system is produced, and the cycle of this reference signal CF is these two clock signal (S
4With S
5) the lowest common multiple in cycle, in the present embodiment, suppose two clock signal S that desire is switched
4With S
5Cycle be respectively 5ns and 4ns (its frequency then is respectively 200MHz and 250MHz), therefore, the cycle of this reference signal CF is to be set at 20ns (its frequency is 50MHz).
Please refer to shown in Figure 5ly, is the clock signal switching sequence figure of the preferred embodiment according to the present invention, because system is when activating, all sequential related signals comprise: reference signal CF, clock signal S
4, clock signal S
5, clock signal S
6Deng, all can make that all signals can be initial by same time point through the action of a replacement (reset).When the controlling signal SC of system output in time t ', (just desire is with clock signal S when becoming high state by low state
6, by the clock signal S of original output
4Switch to clock signal S
5), but the clock trigger signals of D flip-flop 30 (reference signal CF just) is not in the state of rising edge, and therefore, D flip-flop 30 is still kept original output state and (is selected signal C
2Keep the output of low state), clock signal S
6Be still clock signal S
4Frequency of operation.
Up to time t " time, because therefore reference signal CF just in time, according to the output characteristics of D flip-flop 30, selects signal C at the triggering state of rising edge in the position
2To cause and select signal C according to controlling signal SC
2Become high state by low state, make multiplexer 20 by original clock signal S
4Become clock signal S
5, also the cycle (20ns) because of reference signal CF is to be set at clock signal S
4With clock signal S
5The lowest common multiple in cycle (5ns and 4ns), therefore, in time t " time, clock signal S
4With clock signal S
5Can finish a complete cycle synchronously, make clock signal S
6Can be at clock signal S
4When having finished a complete cycle, switch to clock signal S
5
In addition, under normal situation,,, all can produce delay (delay) when signal during through a plurality of logic lock because D flip-flop 30 is made up of a plurality of logic locks, therefore, selection signal C
2Certainly will just input to multiplexer 20 through one section delay, so at clock signal S
4With clock signal S
5Also must can move normally to guarantee signal before inputing to multiplexer 20 through the delay (being to provide) of an identical time by 22,24 of delay chains (delay chain).
In sum, be with two clock signal (clock signal S
4With clock signal S
5) switch to example mutually, as shown in Figure 6, if desire is switched four clock signal (clock signal S
7, S
8, S
9, S
10), then need use one 4 pairs 1 multiplexers 40 and two D flip-flops 42,44, and cooperate two controlling signal SC
1, SC
2Formed four kinds of various combinations, and with four clock signal (S
7, S
8, S
9, S
10) the lowest common multiple in cycle be the reference signal CF in cycle
1, just can finish the mutual switching of four clock signals; Switch three clock signals as desire, then still need use one 4 pairs 1 multiplexers and two D flip-flops, and cooperate two formed three kinds of various combinations of controlling signal (being to ignore under a kind of situation of condition), just can finish the mutual switching of three clock signals.
The rest may be inferred, in ideal conditions, when desire is switched k clock signal, then need use 1
nTo 1 multiplexer and n D flip-flop (2
N-1＜k≤2
nAnd k and n are all a natural number), and system must cooperate the quantity of trigger to provide corresponding controlling signal (for instance, g controlling signal of system will be as the input signal of g trigger, wherein g is the natural number of 1～n), and be a reference signal in cycle according to the lowest common multiple in cycle of k clock signal, just can finish the mutual switching of k clock signal.It should be noted, above-mentioned D flip-flop also can be replaced to logic (sequential logic) assembly by the preface that palpus clocks such as rest-set flip-flop, JK flip-flop, master-slave mode trigger, toggle flip-flop trigger, and so is familiar with the technology of the present invention person when being changed according to the application of reality.
Though the present invention illustrates as above with preferred embodiments, so it is not only to terminate in the foregoing description in order to limit the present invention's spirit with the invention entity.Be with, the modification of being done in not breaking away from spirit of the present invention and scope all should be included in the following claim.
Claims (10)
1, a kind of clock signal commutation circuit, in order to the mutual switching of k clock signal to be provided, wherein 2
N-1＜k≤2
n, k and n are all a natural number, and the feature of this clock signal commutation circuit is to comprise:
One clock generator, in order to produce a reference signal, wherein the cycle of this reference signal is the lowest common multiple in the cycle of this k clock signal;
N trigger is the clock trigger signals respectively with g controlling signal of the system input signal as g this trigger, and with above-mentioned reference signal, produces n selection signal, and wherein g is the natural number of 1～n; And
One multiplexer, according to this n the clock signal of selecting the signal export target, when wherein the clock signal of this target is switched be with switch before clock signal finish one-period synchronously.
2, clock signal commutation circuit according to claim 1 is characterized in that: above-mentioned trigger is the wherein a kind of of rest-set flip-flop, JK flip-flop, master-slave mode trigger, D flip-flop, toggle flip-flop.
3, clock signal commutation circuit according to claim 1 is characterized in that: above-mentioned trigger is that positive edge triggers trigger, negative edge triggers the wherein a kind of of trigger.
4, clock signal commutation circuit according to claim 1 is characterized in that: above-mentioned multiplexer is 2
nTo 1 multiplexer.
5, a kind of clock signal commutation circuit, in order to the mutual switching of k clock signal to be provided, wherein 2
N-1＜k≤2
n, k and n are all a natural number, and this clock signal commutation circuit feature is to comprise:
One clock generator, in order to produce a reference signal, wherein the cycle of this reference signal is the lowest common multiple in the cycle of this k clock signal;
N D flip-flop is the clock trigger signals respectively with g controlling signal of the system input signal as g this D flip-flop, and with above-mentioned reference signal, produces n selection signal, and wherein g is the natural number of 1～n; And
One multiplexer, according to this n the clock signal of selecting the signal export target, when wherein the clock signal of this target is switched be with switch before clock signal finish one-period synchronously.
6, clock signal commutation circuit according to claim 5 is characterized in that: above-mentioned D flip-flop is that positive edge triggers trigger, negative edge triggers the wherein a kind of of trigger.
7, clock signal commutation circuit according to claim 5 is characterized in that: above-mentioned multiplexer is 2
nTo 1 multiplexer.
8, a kind of clock signal commutation circuit, in order to the mutual switching of two clock signals to be provided, this clock signal commutation circuit comprises:
One clock generator, in order to produce a reference signal, wherein the cycle of this reference signal is the lowest common multiple in the cycle of these two clock signals;
One D flip-flop as input signal, and is the clock trigger signals with above-mentioned reference signal with the controlling signal of system, produces one and selects signal; And
One multiplexer is selected the clock signal of signal export target according to this, when wherein the clock signal of this target is switched be with switch before clock signal finish one-period synchronously.
9, clock signal commutation circuit according to claim 8 is characterized in that: above-mentioned D flip-flop is for positive edge triggers trigger, negative edge triggers the wherein a kind of of trigger.
10, clock signal commutation circuit according to claim 8 is characterized in that: above-mentioned multiplexer is 2 pairs 1 multiplexers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310101951 CN1243295C (en) | 2003-10-17 | 2003-10-17 | Clock-signal switch-over circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310101951 CN1243295C (en) | 2003-10-17 | 2003-10-17 | Clock-signal switch-over circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1529217A true CN1529217A (en) | 2004-09-15 |
| CN1243295C CN1243295C (en) | 2006-02-22 |
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ID=34304230
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200310101951 Expired - Lifetime CN1243295C (en) | 2003-10-17 | 2003-10-17 | Clock-signal switch-over circuit |
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| Country | Link |
|---|---|
| CN (1) | CN1243295C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101078944B (en) * | 2007-05-11 | 2010-05-26 | 东南大学 | Clock switching circuit |
| CN101546207B (en) * | 2008-03-28 | 2011-08-10 | 盛群半导体股份有限公司 | Clock signal switching circuit |
| CN106774632A (en) * | 2016-12-15 | 2017-05-31 | 深圳市博巨兴实业发展有限公司 | A kind of clock multi-channel control unit in microcontroller chip |
| CN110109860A (en) * | 2018-02-01 | 2019-08-09 | 纬颖科技服务股份有限公司 | Electronic system and signal switching circuit |
-
2003
- 2003-10-17 CN CN 200310101951 patent/CN1243295C/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101078944B (en) * | 2007-05-11 | 2010-05-26 | 东南大学 | Clock switching circuit |
| CN101546207B (en) * | 2008-03-28 | 2011-08-10 | 盛群半导体股份有限公司 | Clock signal switching circuit |
| CN106774632A (en) * | 2016-12-15 | 2017-05-31 | 深圳市博巨兴实业发展有限公司 | A kind of clock multi-channel control unit in microcontroller chip |
| CN110109860A (en) * | 2018-02-01 | 2019-08-09 | 纬颖科技服务股份有限公司 | Electronic system and signal switching circuit |
| CN110109860B (en) * | 2018-02-01 | 2023-03-31 | 纬颖科技服务股份有限公司 | Electronic system and signal switching circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1243295C (en) | 2006-02-22 |
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Granted publication date: 20060222 |