CN1527387A

CN1527387A - High voltage device structure for plasma plate display driving chip and its prepn

Info

Publication number: CN1527387A
Application number: CNA03158280XA
Authority: CN
Inventors: 孙伟锋; 易扬波; 孙智林; 时龙兴
Original assignee: Southeast University
Current assignee: Nantong Donghai Machine Tools Co., Ltd.; Southeast University
Priority date: 2003-09-22
Filing date: 2003-09-22
Publication date: 2004-09-08
Anticipated expiration: 2023-09-22
Also published as: CN1270382C

Abstract

The high voltage device structure for horizontal scanning driving chip in plate display contains P-type substrate, transverse high-voltage PMOS transistor, longitudinal transistor, P-type isolating ring in between. The longitudinal transistor contains buried N-type re-doped layer, N-type epitaxial layer, field oxide layer, P-type well with N-type source and P-type contact layer inside, N-type connection layer N-type drain, polysilicon grid, grid oxide layer, field oxide layer and contact layer between the polysilicon grid and the epitaxial layer, and oxide layer on the polysilicon grid. The preparation process includes preparing buried N-type layer; growing N-type epitaxial layer; making isolating ring and connection layer; making P drift of P-type transisor, P-well of N-type transistor, P-type field limiting ring, N-well of P-type transistor and P-type buffering layer on the epitaxial layer; growing field oxide layer; making thick grid oxide layer of P-type transistor and thin grid oxide layer of N-type transistor; etc.

Description

High-voltage device structure that drive chip of plasma flat-panel display is used and preparation method thereof

One, technical field

The present invention relates to high-voltage device structure that a kind of plasma flat-panel display (PDP) chip for driving uses and preparation method thereof, especially high-voltage device structure of using of plasma flat-panel display line scanning chip for driving and preparation method thereof.

Two, background technology

Drive chip of plasma flat-panel display is to realize high pressure output by low voltage logic control.Along with improving constantly of display screen technology, high pressure requirement to column selection location chip for driving drops to 100V, 80V even lower (50V) by initial 150V, 120V, operating current is about 40mA, and line driving chip is dropped to about 150V by initial 250V, and operating current is about 400mA.The core of drive chip of plasma flat-panel display is a high voltage transistor, and the quality of its design will directly influence the quality of chip performance.High-voltage CMOS (CMOS (Complementary Metal Oxide Semiconductor)) is a kind of comparatively ideal high tension apparatus, and it has advantages such as switching characteristic is good, power consumption is little, so it is applicable to high frequency, low-power consumption product, and this structure can satisfy the requirement of PDP chip for driving.Column selection location chip for driving is because operating voltage and electric current all compare less, so can adopt the preparation of body silicon materials, but the line scanning chip for driving since operating voltage and electric current all than higher, so it must adopt the epitaxial material preparation, consider big current work, as all adopting its chip area of transversary to increase greatly, generally a kind of high-voltage tube wherein can be adopted vertical structure.

Three, technology contents

Technical problem: the invention provides a kind of drive chip of plasma flat-panel display that is applicable to and use, but be particularly suited for the high-voltage device structure used as plasma flat-panel display line scanning chip for driving and the preparation method of compatibility standard low pressure extension CMOS technology thereof.

Technical scheme: high-voltage device structure of the present invention adopts following technical scheme to realize:

The high-voltage device structure that a kind of drive chip of plasma flat-panel display is used, at least comprise 1 chip unit, this chip unit comprises P type substrate, on P type substrate, be provided with high-voltage P type transverse metal-oxide-semiconductor and vertical MOS pipe, between high-voltage P type transverse metal-oxide-semiconductor and high-pressure type vertical MOS pipe, be provided with dark P type shading ring, high-pressure N-shaped vertical MOS pipe comprises the N type heavy doping buried regions that is located on the P type substrate, on N type heavily doped layer, be provided with N type epitaxial loayer, outer active device region field surface at N type epitaxial loayer is provided with field oxide, active device region field surface outside the N type is provided with P type trap, in P type trap, be provided with N type source and P type contact layer, on N type heavy doping buried regions, be provided with dark N type articulamentum, being provided with the N type above dark N type articulamentum leaks, leakage of N type and P type contact layer lay respectively at the both sides of field oxide, above the active device area beyond N type source on the N type epitaxial loayer and the P type contact layer, be provided with polysilicon gate, be provided with gate oxide between outside polysilicon gate and N type, above field oxide, the top of P type contact layer and the top of polysilicon gate are provided with oxide layer.

The following technical scheme of the preparation method of high-voltage device structure of the present invention realizes:

A kind of preparation method who is used for the high-voltage device structure that plasma flat-panel display line scanning chip for driving uses, the first step: get P type substrate, it is carried out prerinse; Preparation N type heavy doping buried regions on P type substrate; The N type of growing then epitaxial loayer; The dark N type of dark P type shading ring of preparation and high-pressure N-shaped vertical MOS pipe leaks articulamentum on epitaxial loayer; The P type drift region of preparation high-voltage P-type MOS prepares the N type trap and the P type resilient coating of P type trap, P type field limiting ring and the high-voltage P-type MOS of high-pressure N-shaped metal-oxide-semiconductor then on the epitaxial loayer on the n type buried layer, and wherein P type field limiting ring is positioned at the field oxide below; Again at the non-active device of epi-layer surface place growth field oxide; Prepare the thick grating oxide layer of high-voltage P-type MOS and the thin gate oxide of high-pressure N-shaped MOS then; Adjust channel threshold voltage then, prepare the field plate of polysilicon gate and high-voltage P-type MOS in oxide layer.Second step: preparation source region, drain region and contact hole, deposited oxide layer, evaporation of aluminum, last, anti-carve aluminium, Passivation Treatment.

Technique effect: compared with prior art, the present invention has following advantage:

1. the present invention adopts high-voltage P-type MOS transverse pipe and high-pressure N-shaped vertical MOS pipe to be combined to form the high-voltage device structure of chip for driving, this structure is owing to adopt longitudinal high-pressure N type metal-oxide-semiconductor, make the present invention can on identical chip area, improve the operating current of chip, the high tension apparatus of its especially line scanning chip for driving of chip for driving that is suitable as plasma display is used.In addition, but high-voltage device structure of the present invention makes its compatibility standard low pressure locate CMOS technology outward.The field plate of floating of float field limiting ring and the high-voltage P-type MOS transistor introducing of introducing in the 2. high-pressure N-shaped metal-oxide-semiconductor will improve the work compression resistance of two high-pressure MOSs, and their introducing needn't increase any processing step.3. the N type trap of high-voltage P-type MOS transistor introducing has improved its punch through voltage, and P type resilient coating has then improved the electric field in drain region, has improved puncture voltage.4. there is certain distance on the etching border of the thick grating oxide layer of high-voltage P-type MOS transistor and the border of field oxide, can avoid step too high and bring disconnected aluminium phenomenon like this, have improved the reliability of device.5. the present invention forms the high voltage CMOS device structure with high-voltage P type transverse metal-oxide-semiconductor and high-pressure N-shaped vertical MOS pipe, adopt CMOS (CMOS (Complementary Metal Oxide Semiconductor)) process to make, and prepare the peculiar structure of high-voltage section branch earlier, and then preparation low pressure and low pressure and the total structure of high-pressure section, in view of low-voltage device partly prepare after, the preparation of high tension apparatus part formerly, so can not exert an influence to the low pressure metal-oxide-semiconductor, so, the manufacturing process that the preparation method of high-voltage device structure of the present invention can compatibility standard low pressure extension CMOS and the high advantage of reliability is arranged.

Four, description of drawings

Fig. 1 is a structural front view of the present invention.

Fig. 2 is a structure vertical view of the present invention.

Fig. 3 is the embodiments of the invention structural front view.

Fig. 4 is an embodiments of the invention structure vertical view.

Five, specific embodiments

The high-voltage device structure that 1 one kinds of drive chip of plasma flat-panel display of embodiment are used, at least comprise 1 chip unit, this chip unit comprises P type substrate 1, on P type substrate 1, be provided with high-voltage P type transverse metal-oxide-semiconductor 2 and vertical MOS pipe 3, between high-voltage P type transverse metal-oxide-semiconductor 2 and high-pressure type vertical MOS pipe 3, be provided with dark P type shading ring 4, high-pressure N-shaped vertical MOS pipe 3 comprises the N type heavy doping buried regions 31 that is located on the P type substrate 1, on N type heavily doped layer 31, be provided with N type epitaxial loayer 32, outer active device region field surface at N type epitaxial loayer 32 is provided with

field oxide

33,32 active device region field surface is provided with P type trap 341 outside the N type, in P type trap 341, be provided with N type source 3411 and P type contact layer 3412, on N type heavy doping buried regions 31, be provided with dark N type articulamentum 35, above dark N type articulamentum 35, be provided with the N type and leak 351, leakage 351 of N type and P type contact layer 3412 lay respectively at the both sides of field oxide 33, above the active device area beyond N type source on the N type epitaxial loayer 32 and the P type contact layer, be provided with polysilicon gate 37, outside polysilicon gate 37 and N type, be provided with thin gate oxide 36 between 32, above field oxide 33, the top of P type contact layer 3412 and the top of polysilicon gate 37 are provided with oxide layer 38, high-voltage P type transverse pipe 2 comprises the N type heavy doping buried regions 21 that is located on the P type substrate 1, on N type heavy doping buried regions 21, be provided with N type epitaxial loayer 22, non-active device area on N type epitaxial loayer 22 is provided with field oxide 23, active device area on N type epitaxial loayer 22 is provided with N type trap 24, the P type leaks 251, in N type trap 24, be provided with P type source 241 and N type contact layer 242, below reaching adjacent with it field oxide, P type leakage 251 is provided with P type drift region 25, above the active device area of the N type epitaxial loayer 22 between N type trap and P type drift region 25 and the field oxide in the P type drift region 25, be provided with thick grating oxide layer 26, above thick grating oxide layer 26, be provided with polysilicon gate 27, at field oxide, P type source, the P type leaks and the top of polysilicon gate is provided with oxide layer 28, P type in P type drift region 25 is provided with resilient coating 252 below leaking 251, be provided with the field plate 261 of floating above the thick grating oxide layer 26 and below oxide layer 28, above-mentioned resilient coating 252 is one deck P type doped layers, the above-mentioned field plate of floating does not connect any voltage by the preparation of polycrystalline grid.

The high-voltage device structure that 2 one kinds of drive chip of plasma flat-panel display of embodiment are used, at least comprise 1 chip unit, this chip unit comprises P type substrate 1, on P type substrate 1, be provided with high-voltage P type transverse metal-oxide-semiconductor 2 and vertical MOS pipe 3, between high-voltage P type transverse metal-oxide-semiconductor 2 and high-pressure type vertical MOS pipe 3, be provided with dark P type shading ring 4, high-pressure N-shaped vertical MOS pipe 3 comprises the N type heavy doping buried regions 31 that is located on the P type substrate 1, on N type heavily doped layer 31, be provided with N type epitaxial loayer 32, outer active device region field surface at N type epitaxial loayer 32 is provided with

field oxide

33,32 active device region field surface is provided with P type trap 341 outside the N type, in P type trap 341, be provided with N type source 3411 and P type contact layer 3412, on N type heavy doping buried regions 31, be provided with dark N type articulamentum 35, above dark N type articulamentum 35, be provided with the N type and leak 351, leakage 351 of N type and P type contact layer 3412 lay respectively at the both sides of field oxide 33, above the active device area beyond N type source on the N type epitaxial loayer 32 and the P type contact layer, be provided with polysilicon gate 37, outside polysilicon gate 37 and N type, be provided with thin gate oxide 36 between 32, above field oxide 33, the top of P type contact layer 3412 and the top of polysilicon gate 37 are provided with oxide layer 38, the shape of polysilicon 37 can be a triangle, square, circular, abnormity or other shapes, high-voltage P type transverse pipe 2 comprises the N type heavy doping buried regions 21 that is located on the P type substrate 1, on N type heavy doping buried regions 21, be provided with N type epitaxial loayer 22, non-active device area on N type epitaxial loayer 22 is provided with field oxide 23, active device area on N type epitaxial loayer 22 is provided with N type trap 24, the P type leaks 251, in N type trap 24, be provided with P type source 241 and N type contact layer 242, below reaching adjacent with it field oxide, P type leakage 251 is provided with P type drift region 25, above the active device area of the N type epitaxial loayer 22 between N type trap and P type drift region 25 and the field oxide in the P type drift region 25, be provided with thick grating oxide layer 26, above thick grating oxide layer 26, be provided with polysilicon gate 27, at field oxide, P type source, the P type leaks and the top of polysilicon gate is provided with oxide layer 28, in the present embodiment, P type trap in the active device area on N type epitaxial loayer 32 has a plurality of, wherein, the P type trap 341 that is provided with P type contact layer 3412 and N type source 3411 is set at and field oxide 33 position adjacent, in the non-adjacent locational P type trap 342 of field oxide 33, be provided with 2

N type sources

3421 and 3423, between two

N type sources

3421 and 3423, be provided with P type contact layer 3422, in the non-active device area on N type epitaxial loayer 32 and be positioned at field oxide 33 below be provided with the field limiting ring 331 of floating, this field limiting ring of floating is one deck P type doped layer, does not connect any voltage.

3 one kinds of embodiment are used for the preparation method of the high-voltage device structure that plasma flat-panel display line scanning chip for driving uses, and it is characterized in that the first step: get P type substrate, it is carried out prerinse; Preparation N type heavy doping buried regions on P type substrate; The N type of growing then epitaxial loayer; The dark N type of dark P type shading ring of preparation and high-pressure N-shaped vertical MOS pipe leaks articulamentum on epitaxial loayer; The P type drift region of preparation high-voltage P-type MOS prepares the N type trap and the P type resilient coating of P type trap, P type field limiting ring and the high-voltage P-type MOS of high-pressure N-shaped metal-oxide-semiconductor then on the epitaxial loayer on the n type buried layer, and wherein P type field limiting ring is positioned at the field oxide below; Again at the non-active device of epi-layer surface place growth field oxide; Prepare the thick grating oxide layer of high-voltage P-type MOS and the thin gate oxide of high-pressure N-shaped MOS then; Adjust channel threshold voltage then, prepare the field plate of polysilicon gate and high-voltage P-type MOS in oxide layer.Second step: preparation source region, drain region and contact hole, deposited oxide layer, evaporation of aluminum, last, anti-carve aluminium, Passivation Treatment.

Claims

1, the high-voltage device structure that a kind of drive chip of plasma flat-panel display is used, at least comprise 1 chip unit, this chip unit comprises P type substrate (1), it is characterized in that on P type substrate (1), being provided with high-voltage P type transverse metal-oxide-semiconductor (2) and vertical MOS pipe (3), between high-voltage P type transverse metal-oxide-semiconductor (2) and high-pressure type vertical MOS pipe (3), be provided with dark P type shading ring (4), high-pressure N-shaped vertical MOS pipe (3) comprises the N type heavy doping buried regions (31) that is located on the P type substrate (1), on N type heavily doped layer (31), be provided with (32) outside the N type, outer active device region field surface at N type epitaxial loayer (32) is provided with field oxide (33), the active device region field surface of (32) is provided with P type trap (341) outside the N type, in P type trap (341), be provided with N type source (3411) and P type contact layer (3412), on N type heavy doping buried regions (31), be provided with dark N type articulamentum (35), be provided with the N type in dark N type articulamentum (35) top and leak (351), N type leakage (351) and P type contact layer (3412) lay respectively at the both sides of field oxide (33), active device area top beyond N type source on N type epitaxial loayer (32) and the P type contact layer is provided with polysilicon gate (37), outside polysilicon gate (37) and N type, be provided with thin gate oxide (36), top between (32) in field oxide (33), the top of the top of P type contact layer (3412) and polysilicon gate (37) is provided with oxide layer (38).

2, the high-voltage device structure that drive chip of plasma flat-panel display according to claim 1 is used, it is characterized in that high-voltage P type transverse pipe (2) comprises the N type heavy doping buried regions (21) that is located on the P type substrate (1), on N type heavy doping buried regions (21), be provided with N type epitaxial loayer (22), non-active device area on N type epitaxial loayer (22) is provided with field oxide (23), active device area on N type epitaxial loayer (22) is provided with N type trap (24), the P type leaks (251), in N type trap (24), be provided with P type source (241) and N type contact layer (242), be provided with P type drift region (25) in P type leakage (251) and adjacent with it field oxide below, field oxide top in active device area that is positioned at the N type epitaxial loayer (22) between N type trap and the P type drift region (25) and P type drift region (25) is provided with thick grating oxide layer (26), be provided with polysilicon gate (27) in the top of thick grating oxide layer (26), at field oxide, P type source, the P type leaks and the top of polysilicon gate is provided with oxide layer (28).

3, the high-voltage device structure used of drive chip of plasma flat-panel display according to claim 1 is characterized in that P type in P type drift region (25) leaks (251) below and is provided with resilient coating (252).

4, the high-voltage device structure used of drive chip of plasma flat-panel display according to claim 1 is characterized in that being provided with the field plate of floating (261) in thick grating oxide layer (26) top and in oxide layer (28) below.

5, the high-voltage device structure used of drive chip of plasma flat-panel display according to claim 1, it is characterized in that the P type trap in the active device area on N type epitaxial loayer (32) has a plurality of, wherein, the P type trap (341) that is provided with P type contact layer (3412) and N type source (3411) is set at and field oxide (33) position adjacent, in the non-adjacent locational P type trap (342) of field oxide (33), be provided with 2 N type sources (3421 and 3423), between two N type sources (3421 and 3423), be provided with P type contact layer (3422).

6, the high-voltage device structure of using according to the more or less described drive chip of plasma flat-panel display of claim 1,2 is characterized in that in the non-active device area on N type epitaxial loayer (32) and the below that is positioned at field oxide (33) is provided with the field limiting ring of floating (331).

7, a kind of preparation method who is used to prepare the described high-voltage device structure of claim 1 is characterized in that the first step: get P type substrate, it is carried out prerinse; Preparation N type heavy doping buried regions on P type substrate; The N type of growing then epitaxial loayer; The dark N type of dark P type shading ring of preparation and high-pressure N-shaped vertical MOS pipe leaks articulamentum on epitaxial loayer; The P type drift region of preparation high-voltage P-type MOS prepares the N type trap and the P type resilient coating of P type trap, P type field limiting ring and the high-voltage P-type MOS of high-pressure N-shaped metal-oxide-semiconductor then on the epitaxial loayer on the n type buried layer, and wherein P type field limiting ring is positioned at the field oxide below; Again at the non-active device of epi-layer surface place growth field oxide; Prepare the thick grating oxide layer of high-voltage P-type MOS and the thin gate oxide of high-pressure N-shaped MOS then; Adjust channel threshold voltage then, prepare the field plate of polysilicon gate and high-voltage P-type MOS in oxide layer.Second step: preparation source region, drain region and contact hole, deposited oxide layer, evaporation of aluminum, last, anti-carve aluminium, Passivation Treatment.