CN1525326A - Management system for defective memory - Google Patents

Abstract

The invention discloses a defect management system, admitting using the memory device contain many defect memory unit cells. It is especially applied to store serial media data. It can largely reduce the cost of product, which stores quite a large number of data in the solid memory, like MP3 player or MPEG-4 dynamic video player. An inerasable memory stores the corresponding relationship of defect in a memory device, where the memory device tests by the built-in self-testing (BIST) program. It can be configured in a mode of soft or hard body. It can be used in different memories, such as DRAM, flash memory, FeRAM and MRAM.

Description

The management system of defect memory

Technical field

The present invention relates to the management system of a kind of memory management, particularly a kind of defect memory.

Background technology

Highdensity semiconductor memory system comprises millions of each other data storing memory cells.One purpose of manufacturing course makes each memory cell all can use, and can use reliable mode storage data for making this device.Because the restriction of manufacturing technology, the storer of a certain ratio has the memory cell of one or more tool defective, and storage data reliably.This makes this storage arrangement to sell with the goods of standard.

In this " partly available " of major part (partial) or in " low-quality " storer (downgrade), most memory cell all reliably mode move.The price of these storage arrangements also is lower than all good storage arrangement of each memory cell.Its discount rate is far above the memory cell that can't use.So suitable cost under these assemblies of use can be saved in needing the terminal applies of data storing.Developed and multiple different technology, in some specific application, to use.

Multiple different technology can have been used this part memory assembly in considerable application.These technology also are applied in DRAM and the flash memory device.Especially owing to be widely used among the PC.Moreover, the industry that is fabricated to high competition of DRAM, and during entering highdensity manufacturing installation, before reaching optimization, will produce a large amount of part storage availability apparatuses in manufacturing technology.

Other memory bit of DRAM and some is using the built-in redundancy technology.The some that is fabricated to chip design of row that these are extra and row.If in several steps of test, must find out each defective of installing corresponds to this wafer with row and row with redundancy in the electronics mode defect area.This crystal grain can not erasing type storage or melt silk (fuse) and allow one when knowing the position of any defective, the just zone of these redundant memories of mapping suitably.But,, still have the essential maintenance of considerable storage arrangement even when this technology of use.Why like this, mainly contain two reasons.At first, the use of the resource of restriction redundancy in this crystal grain.General redundant row and row are not to be universe, promptly can't mapping any part in this wafer.Regularly (TIMING) and layout (LAYOUT) limit its elasticity.Therefore some defective pattern can't carry out maintenance activity, and this is because these patterns surpass the redundant degree in some zone in this zone.Secondly, give the grained region of redundant resource and may use essential compromise between the ratio of assembly of these resources " reconstructions " in distribution.If there are too many redundant column or row, the then redundant importance that surpasses the advantage of the device ratio that can rebuild for the influence of crystallite dimension.Therefore, still exist the part memory assembly of suitable ratio can't use in general application.But generally these assemblies are when selling, and the information of the characteristic of the defective that is provided and quality aspect still seldom.Therefore must set up these information by test backward.

Many part available memories with low level of defective can directly use in the low order pin expense device and toy of some type.For example, the part storage availability apparatus (being called the audio communication storer) with low number of defects successfully uses in the numerical digit answering machine.These devices store digital audio with compressed format not.Defective in storer has only the impact that the quality of sound is produced transient state, though impact in essence can't identification for these, and can be to the function generation significant effects of this device.But this simple technology can't be used in the device of high image quality, or under the conversion compressed of data.The effect of compression is further strengthened the impact of single bit defect, makes to produce how inevitable impact.And, there are many available part memory assemblies, its number of defects is far above can received scope existing in the application of answer phone or toy.

A kind of being used for is called the bit-planes classification in the technology of the available DRAM device of pC answer part.One of this technology of design example among Fig. 1.Indicate and show 4 storage arrangements that separate in 10.Each storage arrangement can read or write 4 bits simultaneously.Most its width of shared storage type is at least 8 bits and is generally 16 or 32 bits.In the separate blocks of the data storing of each bit in storer 102.Generally, the data that are used for different output bits can be more approaching in fact, but its logical address space still separates.Indicate the defective of 103 designs in the bit-planes of first memory device.Indivedual memory cells that this single defective effect is a large amount of.Indicate 104 and show bit-planes row, it comprises the defective row in the storer.Indicating 105 is that a bit-planes that comprises defective row is arranged.If comprise defective, bit-planes technology reject one whole plane simply then.Indicate 106 and show that the data pin position on a defective data plane is not connected to an external system.The data bit that is provided by storer is denoted as 107.As shown in the figure, in fact has only the bit that uses on the complete good memory cell plane that is connected to data-carrier store.Therefore must use extra storage arrangement so that needed data access width to be provided.The advantage of this technology is simple to operate, but have some shortcoming, even when at first this data redundancy only comprises minority defective memory cell, whole data redundancy all can't use.Secondly, essential adaptive other storage arrangement is to reach needed data width.Therefore occupying PCB goes up more zone and consumes more electric power.If the write capability of bit group is institute's requirement in the accumulator system, then need more assembly, this is because single assembly can't be opened processing with the dibit component that contains the data character.The 3rd, when the average of defective rises to a certain quantity, will make these storage arrangements can't use this technical finesse.But, in fact might be in this storage arrangement suitable the lacking of actual number of defective memory cell.

A kind of more complicated technology is presented among Fig. 2.The storage arrangement of wherein a plurality of tool defectives is to indicate 201 expressions.Each device is connected among the ASIC202 of a special mapping.The inside of this device comprises some a steering logic unit 203 and a memory array 204.It is outside redundant that this storer forms, the data isolation that it makes defective and the outside transmission of the accumulator system on the outside bus-bar 206 in the storage arrangement out of the ordinary.The enantiomorphic relationship of all defect on storage arrangement out of the ordinary is stored in the nonerasable memory device 205.As long as when the steering logic unit detected the action of desiring access one defective addresses, this switched to this operation the appropriate area of redundant memory array.According to this mode, have only the memory cell of tool defective must carry out the redundancy storage, can appropriate this storage arrangement of use.But also there is multinomial shortcoming in this technology.First point, ASIC202 must be in the data routing between the remainder of storer and this system.For system at a high speed, this technology can reach the impact of a suitable timing performance.The second, manufacturing course is quite complicated.Each part storage availability apparatus of essential test, and the enantiomorphic relationship of storage defective is with in being recorded in a defective mapping storer 205 backward.So essential other assembly of following the trail of in whole goods program.Test these assemblies and obtain fully and accurately the degree of defective enantiomorphic relationship to a memory cell be a very complicated challenge.Especially ought require to keep low testing cost and do not influence under original situation of using the advantage of storage availability apparatus partly, this technology is not more had efficient.

Summary of the invention

The management system that the purpose of this invention is to provide a kind of defect memory, this fault management system can the operation of tandem media formats to carry out the storage of audio communication and video signal.These data archivals generally comprise the audio communication and/or the video signal data of compression.The data of this type have a plurality of important characteristics, and make it be suitable for using in the environment of this type.

Designing these data archivals transmits to stride consume property networking medium.Therefore some data envelope will wear away, and causes playback quality to produce temporary destruction.But, comprise suitable inside data in synchronization form and will allow after being destroyed, still can normally play continuously.Therefore, if all sealing all do not comprise critical information, all the other positions of played data are invalid with not causing.The example of this form such as MPEG-3, audio communication signal (MP3) and the MPEG-2 video signal of Layer3.

The present invention proposes a kind of fault management system, and this system comprises: at least one storage arrangement, this device comprise a plurality of defective storing memory structure cells; One nonerasable memory, this storer has a plurality of storage block, is stored in the storage block with the position with above-mentioned defective; Wherein this fault management system is tested this defect memory device, and dispose the form of this nonerasable memory, position with indication defect area in each storage arrangement, and in system between the operating period, detect new defective, and with the defective enantiomorphic relationship in the new defective adding nonerasable memory that is detected.

By the present invention is described in detail with instantiation below in conjunction with accompanying drawing, can further understand feature of the present invention and advantage thereof.

Description of drawings

Fig. 1 has shown the bit-planes system of conventional art, so that with the storage arrangement with a plurality of defective memory cells position;

Fig. 2 has shown the system of more complicated known techniques, with display defect storer position again, wherein uses one to have the outside ASIC of internal storage resource with the defective of corrigendum in a plurality of storage arrangements out of the ordinary;

Fig. 3 has shown the form of data frame in the media data, states bright defect management technique so that use, and these data suitably are stored in this device;

Fig. 4 has shown the framework of the goods that use in the fault management system of above-mentioned explanation;

Fig. 5 has shown the whole framework of fault management system of the present invention, wherein configurations shown in software or hardware to carry out the actual storage square and the control die set of defect management;

Fig. 6 has shown an example with memory array of a plurality of defectives, wherein shows a square blemish square, is denoted as the impact that the square that can not use is scolded bright this defective with application;

Fig. 7 has shown the memory array identical with Fig. 6, and both comprise identical defective, and display application nonerasable memory device stores these defectives in this example.

Fig. 8 has shown the memory array identical with Fig. 6, and wherein this memory array comprises identical defective.Show among the figure that a level is to the mapping square that extends, to show the impact of mapping square shape on the sum that must be denoted as memory cell in the bad mapping square;

Fig. 9 has shown the memory array identical with Fig. 6, and wherein this memory array comprises identical defective, shows one among the figure vertically to the mapping square that extends, to show the impact of mapping square shape on the sum that must be denoted as memory cell in the bad mapping square;

Figure 10 is a process flow diagram, and with the screening storage arrangement, wherein this storage arrangement uses and has in the goods of fault management system of the present invention via this program.

Figure 11 is in part defect memory system, and the example that catalogue data stores is used for the integrality of the majority rule system of reading of data with data in this example;

Figure 12 has shown the inner structure of several mapping squares, has a sum total to check in each mapping square;

What Figure 13 had shown the defective mapping gets mechanism soon;

Figure 14 has shown the impact of internal wafer address topology in several mapping squares, and wherein this mapping square is labeled as and can not uses, and shows among the figure that a simple mechanism produces reverse action with the negative impact for the address topology.

Description of reference numerals: 301 indicate; 302,305 data frame; 303 lattice pivots are synchronous; 304 gauge outfits; 401 storage arrangements; 402 addresses and control signal; 403 data bus-bars; 404 Memory Controllers; 405 defective mapping storeies; 501 input data; 502 data writing controllers; 503 entire controller; 504 catalogue writing controllers; 505 indicate; 506 defective mapping storeies; 507 catalogue Read Controllers; 508 data reading controllers; 510 defective memory cache controllers; 509 output channels; 511 new defective controller modules; 512 built-in self testing (BIST) unit; 513 signals; 514 system architectures indicate; 601,604 indicate; 602 mapping squares; 603 defectives; 605 row defectives; 606 bad memory cells; 607 row defectives; 608 fault management systems; 701 memory arrays indicate; 702 defective mapping storeies; 703,704 indicate; 801,901,902 zones; 1001,1002 steps; The commit point of 1003 screenings; 1005 flow processs by assembly; The flow process of 1007 invalid assemblies; The flow process of 1008 invalid goods; 1009 programs; 1101 storage arrangements; 1102 each other bit group; The 1103 bit groups that wrecked from right value; 1104 controllers; Other mapping square in 1201 memory arrays; 1203 arrows indicate; 1204 show with final value in this square; The memory cell of 1205 tool defectives; 1206 sum total check the values; The content of the enantiomorphic relationship of the 1301 defective mapping storeies that determined by the defective pattern; 1302 defective patterns are presented in the main memory array; 1303 copy to a plurality of part storage availability apparatuses; 1304 keep the part storage availability apparatus of caching data; 1305 majority rule controllers indicate; 1306 feed-ins as a result; New defective in 1307 storeies; 1308 highly show reading of this sum total inspection; 1309 defects detection squares; The defective of 1401 storage arrangements; 1402 single capable defectives; 1403,1406 squares; 1404 memory arrays; 1405 row defectives.

Embodiment

Fig. 3 has shown embodiments of the invention.Wherein data tandem district shows to indicate 301.This data tandem district comprises each other data frame 302.In these data frame 302,, and make each data frame have identical length or different length according to employed form.

First data frame is with synchronous 303 beginnings of a lattice pivot.This permission in addition when data transmission when sealing consume or destroy taking place, still can determine the place that begins of each data frame.The gauge outfit 304 of one data frame provides the information relevant with the data frame content.Need to illustrate the content that comprises medium in the data payload of data frame 305 at last.

Archives with this characteristic especially are suitable for using the storage body of the fault management system of this type.Though when beginning test jobs with find out in the storer defective locations, between the operating period of this storer, still may have a spot of defective.Need these defectives not have fatefulue impact for the performance of this device.When using data tandem medium shelves, suitable little of the impact of a defective makes only to produce temporary transient effect for the quality of playing.In many examples, the user at all can't this defective of identification.

Defect management technique especially is suitable for using in some device, and wherein the data storing of these devices is in memory cache, to play in a device subsequently.The data of this storage will can not be sent to another Storage Media from this device.One of these goods example is portable MP3 audio communication or MPEG-4 video signal player.The downloads of media shelves are playing back then to be stored in this device from a PC.

Essential understanding, defect management technique of the present invention especially is suitable for the storage of tandem media formats data, but also can store the data of extended formatting.If it is also more a lot of than the result who is denoted as good mapping square to test the scope that is contained during built-in self testing, then these medium can be considered as the reliable Storage Media of the data of any pattern.

The actual framework that shows a system that uses this fault management system among Fig. 4.This system has a plurality of storage arrangements 401.The number of employed storage arrangement and be not used in and need system of the present invention among the figure, shown person is a minimum number in the required storer number among the figure.The storage arrangement of any number is even and regular in the present invention.These storeies may comprise the memory cell of a plurality of tool defectives.Though need the number of restriction defective to have some memory span to guarantee whole goods, the number of defective does not limit basically in a given device.

By address and control signal 402 control store apparatuses.According to the framework of storer, this address and control signal can be to point to the incoherent signal in address of each storage arrangement, or can be shared common control and address signals, except the selection of each device.

Use data bus-bar 403 to write data in these storeies, or from storer reading of data.Illustrate once again that according to memory architecture for each storer, these signals can be signals separately, or the common signal that uses.Basically use a plurality of storage arrangements that are arranged in parallel in this memory architecture, to provide than any each wideer data access width of other storer.But this can use a shared data sink stream framed bent structure, to reduce pin number actual in Memory Controller in the unessential system of memory width.

Memory Controller 404.Basically this controller is a microprocessor, and access action that can the control store system.This Memory Controller is connected to a defective mapping storer 405.This is a nonerasable memory, and its volume ratio main memory array is little a lot, and is used to be stored in the enantiomorphic relationship of tool defect area in the memory array.When needing access memory array when avoiding the memory cell of tool defective, relevant zone in this Memory Controller access defective mapping table.When detecting new defective, this Memory Controller also can upgrade the defective enantiomorphic relationship during use.

The framework that shows total system among Fig. 5.The data tandem that is used for the media data of the system of being stored in is represented to indicate 501.Actual low level form can not be subjected to the influence of fault management system mode of operation in these data, therefore can be considered as a black-box system in the goods design.Address in the data writing controller 502 decision primary memorys.Wherein this primary memory is for storing and write outside the input data.For example, might import data 501 from the PC interface, it writes MP3 audio communication data to be stored in the goods.

Whether entire controller 503 decision fault management systems store or reading of data person at any spatial point place.Therefore also there are all the other interfaces that partly are connected with goods in this square, and whole application can be instructed the behavior of fault management system.

One catalogue writes goods 504 and writing controller close-coupled.The stored information of this catalog control device is as beginning and the end address in specific medium shelves or archives block 2 storeies.This allows the desirable immediately data that get.This catalogue information writes predetermined zone in the primary memory.

Wherein heart place in the drawings, display-memory array position shows that to indicate 505 this can comprise several part storage availability apparatuses out of the ordinary.The address decoder mode of using a standard is with according to the address selection that is presented other device.Memory Controller from data write and the catalogue writing controller receive data and address.By data read and the catalogue Read Controller project in can access memory.Because employed memory device is changed to partly available person,, and therefore can't be stored in reliably in the data bit so the memory cell in any space may have defective in memory array.

In defective mapping storer, keep the enantiomorphic relationship 506 of defective in the memory array.This is a nonerasable memory, and the capacity of this storer is essentially a certain ratio in the main memory array.The enantiomorphic relationship of this memory storage position of defective square in main memory array.

Catalogue Read Controller 507 can be obtained to be stored in and begin and finish information in the storer by the catalogue writing controller.Therefore can determine beginning and the address of end data of data in the specific medium shelves.

Data reading controller 508 reads the data from storer, and transmits these data in output channel 509.If necessary, this controller can be connected to all the other positions of this system so that needed function to be provided.For example, can be connected to a MP3 decoding device system, to play the data that before had been stored in the device from a PC interface.

Defective memory cache controller indicates with 510.The function of this controller is for when writing archives, and what store the defective enantiomorphic relationship relevant with specific medium archives gets version soon.This gets defective enantiomorphic relationship itself soon and can be stored in the primary memory, and this pattern of getting soon is illustrated in the state of this defective when writing media defect.

Show a new defective controller module 511 among the figure.During using these goods, this module will detect new defective and add in this defect memory.

One built-in self testing (BIST) unit 512 is arranged at last, and the function of this element is carried out a series of test jobs for listing at memory array, and mends and catch the defective group to write in the defective mapping storer 506.General when starting these goods during only in this goods starting or when the test clip (test jig) of use one appointment during the manufacturing course, just carry out this a series of test procedure.Wherein signal 513 indicates and when carries out the BIST test.

Memory cell in storage arrangement is divided into the square of a plurality of mappings once more.Each mapping square is included in a plurality of memory cells in the storage arrangement.Each mapping square is represented and can be denoted as good or bad I execution area for fault management system.If when a mapping square comprises any defective memory cell, then this mapping square is denoted as bad mapping square.If when a mapping square is denoted as good mapping square, then in this square all memory cell when its memory cell is carried out recall tests, must be all storage data reliably.Essential understanding is in use backward, and under some environment, these memory cells are storage data reliably, in the case, this mapping square transfers sign to defective mode, otherwise bad mapping square can not be transferred to indicates good mapping square.

Relation in the mapping square between the size of the number of memory cell decision main memory array and needed defective mapping storer.In a defective mapping storer, only need single bit can represent a mapping square.This shows that simply a mapping square is good or bad.For example, if each mapping square comprises 1024 memory cells, then the size of this memory array is 64MB, and then this defective mapping storer must be 64KB.This fault management system allows can adjust the size of mapping square with the needs in the realistic application.Bigger mapping square makes the needs of defective mapping storer reach minimum, but its shortcoming is the more good memory cell of waste in memory array, even in memory array, only comprise the bad memory cell of minority, then whole mapping square must be labeled as bad memory cell, and the memory cell in this mapping square does not all use.

Show the memory array that comprises a plurality of defective memory cells among Fig. 6, to indicate 601 expressions.This storer comprises each other mapping square 602.This memory array comprises a large amount of defective 603, the adjacent memory cell that its influence is a large amount of.The mapping square that comprises the memory cell of any tool defective must be denoted as bad memory cell.These memory cells cover with hacures in the drawings.Sign 604 indicates the zone of the bad corresponding square that is caused by defective 603.

Memory array also comprises capable defective 605.To make that row and Lieque fall into very common owing to the actual framework of lower floor in storer, and memory array is actually the track that connects indivedual memory cell levels and vertical interlaced (to comprise character line and bit line) in whole memory arrays.If the short circuit or destroy these and link in some mode then will produce the row or column of a tool defective.Go defective and be denoted as bad memory cell in the drawings with 606 signs.

Memory array also comprises delegation's defective 607.The person marks with 608 in the drawings owing to defective is labeled as the fault management system.

Generally, at the number of the number of the expert memory cell of a mapping square and row memory cell be 2 power.This allows the correct address of the bad flag in defective mapping storer directly to obtain from main memory address.Can use simple displacement and additive operation to calculate this address, this with the microprocessor of low usefulness, handles this management system in the software mode to just, is even more important.

Be presented among Fig. 7 main memory array defective and correspondence defective mapping storer between relation.Memory array with defective is denoted as 701.This defective mapping storer is for indicating 702.Single bit in storer corresponds to the mapping square in the memory array.In the present example, if this mapping square is bad person, then the content with the defective mapping is labeled as 1, if this mapping square is good person, then is denoted as 0, and vice versa.Indicate 703 and be presented at mapping square in the primary memory and the relation between the bit in defective mapping storer.

When just from this memory array, writing or during reading of data, then checking the defective enantiomorphic relationship.Access data from the equivalent locations a specific mapping square.When reaching the terminal point of a mapping square, this address increases, and points to next good mapping square starting point.According to this mode, in storer, write or reading of data during, will skip the mapping square of tool defective.Among the figure to indicate 704 numbers that are presented at the mapping square in each good mapping square.These numbers represent to have in the accessible memory array 47 good mapping squares.

The shape of mapping square has direct influence for the number of mapping square, according to the actual framework of its defective this mapping square is labeled as bad mapping square.The memory array that Fig. 8 displayed map 6 is identical and the configuration of defective.But, in this example, in shape, the mapping square upwards is offset in level.That is, its row segmentation comes longly than capable segmentation in memory array.The mapping square is total identical among the essential sum of understanding memory cell in each mapping square and Fig. 6, and the size of defective mapping storer that therefore must use is also identical.Zone 801 shows the mapping square with circular flaw.In this figure, there are 8 mapping squares to be labeled as bad mapping square, and have 9 among Fig. 6.Therefore difference between the two is little.Show in these zones 802 that these mapping squares are denoted as bad mapping square owing to the relation of row defective.Always have 8 mapping squares and be labeled as bad mapping square, and have 4 among Fig. 6.In the mapping, relatively more following with square mapping square so be expert at, level is more inefficent to skew mapping square.In an extreme example, a mapping square can comprise row all in the memory array, but has only single row in height.Indicate 803 zone, show because the relation that Lieque falls into, these mapping squares are to have 2 to be considered as badly altogether, and are 4 among Fig. 6, so in the row mapping, level is handled Lieque and fallen into more efficient to the square of skew mapping.

Show the memory array identical and the configuration of defective among Fig. 9 with Fig. 6.Only in the present example, be vertical shift at mapping square in shape.Promptly from memory array, the capable section proportional band segment length of these mapping squares.The sum that must understand memory cell in each mapping square is same as Fig. 6 person, and therefore the size of needed defective mapping storer is also identical.Zone 901 is presented at the mapping square that is denoted as the tool defective in the circular flaw.Always have 8 mapping squares and be denoted as bad mapping square, then be 9 among Fig. 6.Therefore, difference between the two is little.Zone 902 shows owing to the row defective is denoted as bad mapping square.Have only two to be denoted as bad person, and have 4 among Fig. 6.Relatively more following with square mapping square, vertical shift mapping square is more efficient.Zone 903 demonstrations are denoted as bad mapping square owing to Lieque falls into.Always have 8 mapping squares in this zone and be denoted as bad person, then have 4 among Fig. 6.When the processing Lieque fell into, the mapping square of vertical shift was more inefficent.In extreme example, the mapping square can comprise row all in the memory array, but the width of each row has only delegation.But the data that obtain a different rows than in same row when the access time that obtains new row from a storer are also grown when a lot, and then the method then seems uneconomical on efficient and performance.Also the power than the different rows in same row is also many for the power that access row out of the ordinary are consumed.

Therefore the size of the mapping square of a general configuration and shape reach the general distribution of the defective of being found in storage arrangement with the size that meets primary memory and spendable defective mapping storer.If on Lieque falls into, have strong skew, the mapping square of usage level skew then.There is strong skew on the defective if be expert at, then uses the mapping square of vertical shift.

The purpose of built-in self testing (BIST) is for test part available memory device, to produce a defective enantiomorphic relationship figure.If can obtain sufficient defective covering scope, then can find out defective locations most in this device, then deposit in the defective mapping storer.Can avoid storage data in the defect area of this part available memory then.Between the operating period of these goods, have only a spot of additional defects to be found.

BIST uses identical microcontroller or other hardware mechanism to test this storer, as using between the error-free running period of this fault management system.Therefore, can cause other extra goods costs hardly, this is because carry out the event of BIST.In any case must comprise this function.Relatively more following with some prior art, this further reduces the cost that uses part storage availability apparatus.Because one is integrated into carries out this test in the goods on last goods when storage arrangement, in whole manufacturing course, can not follow the trail of the defective mapping relevant again with specific actual device.And, can avoid on the device receptacle of tester because bad conductance the defective of deriving that is produced.With the employed environment of end product to extremely identical environment under this storage availability apparatus partly of test.

Usually, during the goods program, when goods are energized for the first time, carry out BIST.In addition, can begin this BIST program by one group of signal, and can between the normal operating period of goods, not carry out this program by outside input system.Because the program of test does not need the resource of expensive storage device tester, so the BIST test gets time extension.

During BIST carried out, the environmental baseline of voltage or temperature etc. can be fitted and be needed and different with normal situation.This allows can increase the scope that test is contained during BIST, and therefore can reduce the additional defects number at goods between the operating period.

When beginning BIST handles, clear up defective mapping storer earlier, so that all zones are good zone in the part storer.When defective during test period detects it, then this mapping square is denoted as bad person.In fact, the corresponding format manipulation of BIST to be determining bad zone, and this operation is more as the format of magnetic data Storage Media.

BIST can comprise any test configurations group.But in general, comprise the test pattern of a plurality of couplings, it changes pattern along data, increases or reduce the direction of address, and the addressing storer.Design these and test the mistake of determining in the storer to find out (promptly a memory cell stores into 1 or 0 with reliable mode only), and be coupling in the mistake between the adjacent memory cell in this memory array.For DRAM, must be updated periodically its content, so in some test, will surpass maximum update time, have the weak memory cell of high leak rate with detection, and so storage data reliably.

After finishing all test jobs, must check operation, to determine that good capacity left in the storer is greater than a predetermined minimum value.As being, then look this device and lost efficacy.This BIST also comprises iteration tests (iterative test), and this test is for continuing this storer of test, till no longer detecting any new defective.This allows for the defective number many or unsettled device must more test on this device in some way.

When using part storage availability apparatus in goods, these devices must connect to a screening sequence.Therefore the number foot that can determine memory cell in goods applies use, and can not violate the maximized principle of parameter.For example, cannot surpass maximum standby current.Usually partly the storage availability apparatus is for all good devices, and it has relatively poor performance parameters.

Figure 10 is the process flow diagram of screening sequence of the present invention.In step 1001, begin to carry out this program with non-classified part storage availability apparatus.In step 1002, carry out screening sequence.In this program, carry out multiple different test jobs.Wherein comprise functional memory test and parameter testing.These tests are not carried out completely, but are provided at defective memory cell number indication in the specific device simply.A kind of possibility has the suitable commercial memory tester of sealing processor for using.But general design of these testers upward is at all good storage arrangements of test, and generally can't calculate the number of defective memory cell in the storage arrangement, and the test philosophy of (pass/fail) is passed through/fails in these test uses one.For the DRAM element, another is chosen as uses a tester based on PC (PC).Storage arrangement is written into the carrier of zero insertion force socket, and inserts in the second memory module of a PC.One known good memory module is inserted this first module slot in order to carry out operating system and application.One memory test formula is checked operation for the module under the test, the counting defective, and indicate those parts in greatest drawback memory cell counting.The environment that the third selectable mode is goods in the end is these assemblies of test down.Can use goods for these memory assemblies with Zero plug-in force socket.Can carry out the BIST of standard then, to screen these assemblies.Produce to feedback from goods and move, it shows those elements by test, and those assemblies are not by test.

During screening sequence, can change the validity of environmental parameter with retrofit testing.For example, allow these assemblies under the situation that temperature is up adjusted, can on these assemblies, test, go back strict than last application for the needed access time of these elements.Generally set boundary belt to reduce the probability of assembly mistake by filter criteria for all test parameters.

Indicate 1003 commit points for screening.Operation defective memory cell number can allow the assembly (if or test b IST mechanism for testing, the mapping square number of defective) of number less than a maximum, and the requirement by this parameter screening.The flow process of invalid assembly indicates with 1004.With these invalid assembly rejects, or use under the situation of some low order.Flow process by assembly is represented to indicate 1005.Use fault management system that these assemblies that pass through are used to assemble goods then.

The BIST that program 1006 expressions are carried out by these goods.This is when the complete situation of assembling and energizing for the first time with part storage availability apparatus of these goods.This defective enantiomorphic relationship writes can not wipe in the defective mapping storer, so as long as all available under the condition that this device is energized subsequently.

After finishing the BIST test, indicating person shown in 1007, on these goods, carry out a verification of passing through.This test jobs system is based on during the BIST program, behind the discovery defective square, at the operable a certain minimized memory capacity of these goods.In the part applicable components of screening test period will be had a suitable boundary belt.The number of failing in this stage is with suitable lacking.Indicate the flow process of the invalid goods of 1008 expressions.These goods will be divested, and the memory assembly that will have a greatest drawback number replaces.Show that in sign 1009 last situation will stay the good goods that are suitable for loading.

In the storage except media data, the catalogue information also must be stored in this device.This must maintain in the identical part storage availability apparatus as media data.Considering total storage volume, size general and media data is relatively more following, and what the catalogue information was suitable lacks.This catalogue data is kept information, as beginning and end position of specific medium archives, or other relevant attributes.These catalogue datas must store in mode highly reliably, if therefore ruined words of these catalogue datas, will cause can't these medium archives of access.

Though used partly storer of BIST test, still may between the operating period of goods, produce other extra defectives.Generally, suitable big of the possibility of this situation taken place, and be enough to make the catalogue information directly to be stored in the main memory array.Must provide one extra redundant bad with determine the catalogue information all reliably mode rebuild.The mode of using a redundancy and majority rule (majority voting) is to reach this purpose.

Figure 11 shows the method, and the zone with the catalogue information in storage arrangement 1101 stores three times.This copy is stored in the in fact different storage arrangements, has influence on whole storage arrangement to prevent to produce the situation of common mode failure.But under some environment, different copies is stored in the zones of different of same storage arrangement.

Indicate with 1102 from each other bit group of a catalogue information.X indicates the bit group that has wrecked from right value, to indicate 1103 expressions.Generally, the ratio of destroyed bit group is quite few.

As long as reading of data from catalogue then reads each bit group from each copy.This decision by majority, controller is from indicating 1104 expressions.Be necessary from this catalogue, to read the different copies of these data, and for the correct numerical value of bit group decision.So if two bit groups of these data are all identical, then this numerical value is replied.Therefore, when mutually single bit group is destroyed, can not have influence on the integral body of storage data.The number of copies of catalogue can increase, and prevents ruined ability with improvement.

Indicate 1105 and show the example that reads.These reading operation system data-bit-group from the different bit groups of catalogue data.This correct data-bit-group is with letter " O " expression.But the second bit group is destroyed.This decision by majority controller can obtain these data and sends back to correct from two remaining correct bit groups " 0 " value, wherein to indicate 1106 expressions.

The personnel that have the knack of present technique must understanding can use other mechanism to store catalogue data to use reliable mode in present technique.For example, can use error correcting code (ECC) method to carry out the storage of catalogue data.These methods store extra wrong compound ratio spy and remake to allow original catalogue data, even still can reply these data under the situation that occurs a plurality of bit mistakes in raw data.But the shortcoming of this technology is that mathematical calculating is quite complicated, and if when being configured on the processing software of quite simple microcontroller, must expend the quite long processing time.

Design in the test of carrying out during the BIST in part storage availability apparatus, to obtain most defective.But program test can't guarantee to have finished and test out all defectives, as providing boundary belt to this test with time or environmental baseline without any mechanism.Therefore might between the operating period of these goods, detect extra defective.When playing these medium archives, will produce slight impact to the quality of this broadcast, but under the situation of major part, may not have too much influence.

As long as any defective took place between the operating period of these goods, the essential use, and indicate the mapping square of bad defective memory cell.Therefore when carrying out data storing future, do not use this mapping square.This mechanism allowed between the operating period of these goods, set the information that study and new defective allow.

The method of using a summation inspection (checksum) is to allow detecting the new defective that is produced between the operating period at this device.Show this situation among Figure 12.Wherein indicate 1201 and be presented at other mapping square in the memory array.Its memory cell square with 8 * 8 is represented.This square can be striden duplicating of plane on a plurality of datum planes of this device, for example 8 bits.Therefore, the hexadecimal value of dibit relevant with each memory cell 1202 in the drawings.The bit number relevant with each memory cell decided on the memory architecture of use.And, preferably have a bigger size at each mapping square of system of reality.Indicate person as shown in 1203 as arrow, in a mapping square in the position adjacent.

In each mapping square, store a summation check the value.In this square, show, and be denoted as 1204 with final value.This sum total check the value is illustrated in the sum total of the numerical value of every other storage in the mapping square.If data are destroyed in the mapping square, then will use this sum total check the value to detect.When reading of data, then calculate this sum total check the value at any time.Compare with stored sum total check the value then.If both differences, then in the mapping square because the relation of defective memory cell, this mapping square is destroyed.The mapping square is labeled as in defective mapping storer and is the person of being damaged then.If might a series of bit group be destroyed, then might produce identical sum total check the value, and therefore can't detect mistake.But the probability that produces this situation is quite little.Must understand fault management system of the present invention does not need knowing just establishment under the situation that contains meaning within the data-bit-group, to use this mechanism.

Use sum total inspection can't determine memory cell or memory cell group that is specific to have defective.But, and need may not be certain this condition, this is because being included in projects all in total total inspection value all drops in the identical mapping square, and therefore whole mapping square must be labeled as bad mapping square.

Indicate 1205 and show the memory cell of tool defective, and therefore can't be with reliable mode storage data.When reading the data of this mapping square, the sum total check the value 1206 that this is relevant is detected.Difference between the sum total of calculating and storage is checked will cause this mapping square to be labeled as bad mapping square, therefore will be not used in storage data to the mapping square afterwards.

Have the knack of the mechanism that the present technique personnel must understanding can use other simple sum totals to check.For example, can use Cyclic Redundancy Code (CRC) in a mapping square, to detect the situation of data corruption more reliably.But its shortcoming is for must expend more time.When configuration fault management system in microcontroller cheaply, this is to have important considering.

Use some restriction to prevent during single inferior the reading of medium archives, having too many mapping square to be labeled as the mapping square of tool defective.This is because each time when a new mapping square is labeled as defective mapping square, will make the capacity of these goods reduce.This sum total inspection body can't identification by the invalid of the sum total inspection that blemish caused or owing to data corruption caused in system other origin causes of formation.If (for example owing to outage) destroys storer for some reason, the broadcast of medium archives must not indicate all mapping squares, and therefore adjustment is as using the unfavorable condition that is caused by goods.So, the maximum number of new bad mapping square is set at a fixing parameter for these goods.One works as this restriction above reading specific medium archives, then may know any invalid situation that these other sum total is checked that suffers from.

Another configuration mode of the method is to use an error correcting code in each mapping square, but not only uses a simple sum total check the value.This must occupy the capacity of bigger ratio in the whole storage device, but its advantage is for correcting the mistake of number of different types.In the method, correct these mistakes, as the some in the fetch program, therefore on the quality that reads, descend at least.But the mapping square still is labeled as the defective square, this be because next time when data are write this square, defective may above can for ECC the quantity that can correct.This device is handled this program in the mode that can't detect, and increases can not produce any impact to quality.The data of using this program need integrate high levels are used partly, and the storage availability apparatus is stored.

When misuse mapping square and when detecting new defective, will in defective mapping storer, the mapping square be labeled as bad, if use defective mapping storer to skip that mapping square with reading of data, to cause a problem with decision.If detecting this defective for the first time, identical subsequently archives are read again, then will skip whole mapping square and therefore in the mass data that originally occurs in archives leakage be fallen, and make the quality of this media play reduce greatly.General that situation is also bigger than the influence that original defective itself is produced.

Must be stored in the memory cache so write fashionable defective enantiomorphic relationship for the first time, use this to be stored in defective mapping information in the memory cache, to determine that when reading these archives that mapping square is bad person at the medium archives.When new data are write this storer, from this memory cache of defective mapping memory updating.This defective mapping memory cache can be stored in this memory array.Must need and need reliably to store because get information soon, can use above-mentioned majority rule method for the catalogue information for this.

Show this program among Figure 13, wherein indicate 1301 contents for the enantiomorphic relationship of the defective mapping storer that determined by the defective pattern, wherein this defective pattern is presented in the main memory array, represents to indicate 1302.When data are write main memory array, the content in the defective mapping memory cache is copied in a plurality of part storage availability apparatuses, as indicates as shown in 1303.Some section of keeping the part storage availability apparatus of caching data is denoted as 1304.Generally has only the part that stores the defective mapping relevant with the data tandem that writes.This allow different medium archives independently to read and writing system in, and suitably get the renewal operation soon.

The majority rule controller is denoted as 1305.This feed-in as a result is denoted as in 1306 the Read Controller, and the function of Read Controller is given primary memory for produce the address during the fetch program, and skips the mapping square of tool defective.

Be illustrated in defective new in the storer to indicate 1307 in the drawings.When reading back these data, because the sum total that stores is checked the difference between numerical value and the institute's computational data, this situation will be detected.Indicate 1308 and highly show reading of this sum total inspection.Use this sum total to check by defects detection square 1309.When detecting new defective, changing bit suitable in the defective mapping storer is bad mapping square with reaction with the mapping square.Show this situation to indicate 1310 in the drawings.This suitable bit changes into 1 from 0.

In the defective mapping, the copy of getting soon of defective mapping still is maintained previous value.If when therefore reading identical medium archives once again, the mapping square that is included in this defective still is included in the reading of data of this time, and determines the defective that the mapping square is identical once again.Have only when new data to write in this memory array, and the mapping memory cache that upgrades defective just can be avoided when comprising the defective mapping square of new decision.

The distribution of defective is subjected to the externalities relevant with the practical layout of storage inside apparatus in memory array.In some example, only have influence on single storer memory structure cell.But in many examples, a single actual defects will influence the adjacent memory cell of cluster.If the taker of reading is a character line or a bit line, this will be permutation or whole row district number.

In the address space of reality the defective bit groups always be not directed to outside the device the scarce bit groups in the observable numerical digit address space.This is because many memory devices are equipped with the topology mapping (topologymapping) of an inside, and this mapping system is relevant with the actual arrangement of memory cell in this device.

This situation is presented among Figure 14, and single capable defective 1402 is distributed in the logical address space of storage arrangement.The defective of storage arrangement is to indicate 1401 expressions.This row only influences in this device every row.Therefore data store in reliable mode in row at interval.It is desirable to not to the utmost, two whole mapping squares must be denoted as bad mapping square.Shown in square 1403, use direct row addressing can obtain this defective.

The effective coverage that might reduce this defective via using changing one to one of column address space, and shown in the square 1406.This exchanges the column address bit of A3 and A0 simply, and therefore can carry out on software quite simply, even can carry out on a simple microprocessor.So far the address space of Zhuan Huan left-hand side is called actual address space and then is called logical address space to the right side person.In fact, the reverse mapping of the layout of person's internal wafer shown in this conversion and cause the distribution of the single defective shown in 1402.In the actual address space, carry out all addressing of this device, wherein before this storage arrangement of addressing, this address is converted to logical address space between fixed.The correction of defective in the display logic address space in memory array 1404.1405 of the defectives of will going now have influence on adjacent row.So have only single mapping square must be labeled as bad mapping square, and partly improve the total amount in the space that can use.

Obtain actual mapping function to logic via changing the inside topology mapping of carrying out by storage arrangement simply.It is desirable to not to the utmost, this mapping is device inside, and manufacturer can't the needed information of allodial publication.But, in fact can determine this topology with statistical via the number of part memory assembly.The suggestive replaceable different address bit of record algorithm of searching of one tool is with decision impact for defective mapping square number in these devices.The sum of bad mapping square reaches hour in the functional memory device, can obtain the good approximation of topology mapping within this device.

Claims (23)

1. fault management system, this system comprises:

At least one storage arrangement, this device comprise a plurality of defective storing memory structure cells;

One nonerasable memory, this storer has a plurality of storage block, is stored in the storage block with the position with above-mentioned defective;

Wherein this fault management system is tested this defect memory device, and dispose the form of this nonerasable memory, position with indication defect area in each storage arrangement, and in system between the operating period, detect new defective, and with in the defective enantiomorphic relationship in the new defective adding nonerasable memory that is detected.

2. fault management system as claimed in claim 1, wherein the data of this storage are delimitated with data frame, make that at goods the defective bit that is occurred only produces the interference of short time between the operating period for the quality of media play.

3. fault management system as claimed in claim 1, wherein this fault management system of configuration in the firmware of microprocessor.

4. fault management system as claimed in claim 3, wherein a firmware is a catalogue writing controller, with data archival begin and the end address is stored in the defect memory device.

5. as claim 4 ground fault management system, wherein this firmware is a catalogue Read Controller, to obtain beginning and the end address by this stored ground of catalogue writing controller data archival.

6. fault management system as claimed in claim 5, wherein this firmware is a defective memory cache controller, it keeps the copy of the defective enantiomorphic relationship relevant with a specific data segment.

7. fault management system as claimed in claim 6, wherein this defective memory cache controller stores the copy of this defective enantiomorphic relationship at least one storage arrangement.

8. fault management system as claimed in claim 1, wherein a new defective controller action is in detecting new defective in this system between the operating period, and new defective is added in the defective mapping storer.

9. fault management system as claimed in claim 1 wherein also comprises a built-in self testing mechanism, with at first, sets the state of defective mapping storer.

10. as the fault management system of claim 19, this built-in self testing mechanism of configuration in the firmware of a baried type microprocessor wherein.

11. fault management system as claim 10, wherein start this built-in self testing mechanism by one group of external input signal of importing this baried type microprocessor, between the operating period, when normal running, can't produce this test action at the goods that contain fault management system.

12. fault management system as claimed in claim 1 wherein has at least a storage mechanism to be formed by memory array, but and the defective square of this at least one storage arrangement be included in the array of memory locations of the addressing of this memory array.

13. as the fault management system of claim 12, wherein the size of this defective square is 2 power, therefore can oversimplify the conversion process of storage address to mapping square address.

14. as the fault management system of claim 12, wherein the size of this defective square can be adjusted via the distribution of shapes of the defective that storage arrangement detected.

15. fault management system as claimed in claim 3, wherein this defect memory device test output that is a screening sequence is to check in the spendable storage volume of this in-house minimum.

16. as the fault management system of claim 15, wherein this screening sequence is performed by this baried type microprocessor.

17. fault management system as claimed in claim 1 is wherein kept the catalogue information of a redundancy, to provide reliable storage for these data at least one storage arrangement.

18. as the fault management system of claim 17, wherein read this catalogue information, if the ruined words of catalogue information bit group of minority also can obtain effective information via a majority rule controller.

19. fault management system as claimed in claim 1, wherein a sum total checks that (checksum) is relevant with the data value of storage in the defective square of selecting.

20. as the fault management system of claim 19, check the data value summation that does not meet storage, then the square that this defective square of sign is the tool defective in defective mapping storer if wherein sum up.

21. as the fault management system of claim 19, wherein a section that stores this defective square with redundant fashion in primary memory is a caching data, make Read Controller can be from the defect memory square reading of data.

22. as the fault management system of claim 21, wherein the detection of new defective causes promptly upgrading this defect memory, but when new data write this main memory array, just gets the renewal of copy soon as this.

23. fault management system as claimed in claim 1 is wherein changed at least one new row in the storage arrangement and row, to reduce the average of defective mapping square.

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