CN1523830A - Decapsulate method for synchronous digital series link access procedure - Google Patents
Decapsulate method for synchronous digital series link access procedure Download PDFInfo
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Abstract
This invention discloses a method for unlinking package of synchronous digital sequence link access protocol, in which, double byte or multibyte data bus and two or more serial CRC modules in same bytes with the data bus width are applied in the frame check, mid-results can be transferred between adjacent CRC modules and every one can input data and output results. Before checking, the data is processed, if they are multibyte effective data, they should be sent to two or multiple single bytes circulation redundancy check module CRC directly, if only the single one is effective, the said byte is set in one CRC, saving an 8 bit CRC module.
Description
Technical field:
The present invention relates to a kind of de-encapsulation method of synchronous digital hierarchy Link Access Procedure, relate in particular to the extraction (extraction of LAPS payload) that synchronous digital hierarchy Link Access Procedure in a kind of de-encapsulation method of synchronous digital hierarchy Link Access Procedure is decided frame (LAPS decides frame), frame check and synchronous digital hierarchy Link Access Procedure payload.
Background technology:
The present invention has realized the decapsulation of Link Access Procedure-SDH protocol comprising X with the FPGA FPGA (Field Programmable Gate Array)
43+ 1 motor synchronizing descrambling code, abandon the rate adapted byte, detect and complain to Abort field (termination) (0x7d7e), the escape of LAPS is handled, CRC32 verification (cyclic redundancy check (CRC)) and the extraction of LAPS payload and the generation of relevant alarm.The LAPS decapsulation maximum that this method realizes can support that bandwidth is 1.6Gbit/S, and inside modules adopts double byte bus (16 bit), and highest frequency can reach 100Mhz.
Link Access Procedure-SDH protocol is a kind of emerging agreement, it very be similar to High-Level Data Link Control (HDLC), be applied to IP OVER SDH (the IP agreement on the synchronous digital hierarchy), EthernetOVER SDH (Ethernet protocol on the synchronous digital hierarchy), very succinct, efficient.Its frame structure as shown in Figure 1.
0x7e is the frame alignment identification field, 0x04,0x03, be fixing address and the control field of inserting, 0xfe01 identification data payload is mac frame (Media Access Controlled frame) (IPv4:0021, IPv6:0057), FCS field (Frame Check Sequence field) is address, control, SAPI (service access point identification) and payload user data to be done the result of calculation of CRC32.To be the China's Mainland propose aspect logical at number Link Access Procedure-SDH protocol that first is approved by ITU-T and example is the agreement of world standard.Application at home is very extensive.This method realized completely Link Access Procedure-SDH protocol decapsulation (X.86, X.85) and also with the rfc2615 protocol-compliant.
Because the restriction of FPGA (field programmable gate array) hardware itself, its operating frequency unlikely very high (present stage generally not can greater than 100M) is so will realize the width that big flow just must the increase internal data bus.But the increase of internal data bus width certainly will increase the complexity (complexity of logic can be brought the reduction of circuit speed again) of programming in logic and expend more logical resource.Make the speed of service of circuit be difficult for reaching 100M.
Summary of the invention:
Purpose of the present invention is exactly in order to overcome the above problems, a kind of de-encapsulation method of synchronous digital hierarchy Link Access Procedure is proposed, the reasonable decapsulation of having handled Link Access Procedure-SDH protocol under the double byte internal data bus of this method, the resource that expends simultaneously is considerably less, and has guaranteed the speed of service of circuit.
For achieving the above object, the present invention proposes, and a kind of de-encapsulation method of synchronous digital hierarchy Link Access Procedure comprises following process at least:
LAPS decides frame;
Frame check;
The LAPS payload extracts;
Wherein frame check process is: adopt double byte or multibyte data bus, and in described frame check process, adopt the two or more byte cyclic redundancy check (CRC) modules identical with the byte number of data-bus width, they are connected mutually, can transmit intermediate object program mutually between the adjacent byte cyclic redundancy check (CRC) module, each byte cyclic redundancy check (CRC) module can be imported data and output result; Before verification, earlier data are carried out preliminary treatment: if the multibyte valid data, then directly each byte is delivered to two or more byte cyclic redundancy check (CRC) modules respectively, if have only the byte data effective, then effective this byte is put into one of them byte cyclic redundancy check (CRC) module.
The inventive method also comprises: choose identical with the data/address bus byte number at least two or more comparators, before LAPS decides frame, the later data of unified all descrambling codes of traversal, to compare through the high and low byte of the data of descrambling code with above-mentioned comparator, if frame delimited identifier, escape character (ESC), rate adapted byte, then with position, respective identification position, and write down its byte location simultaneously.
Described sign position is kept in the trigger, removes and new logo position index signal more with next input byte useful signal.
The inventive method also comprises: the extracting method of described LAPS payload is to introduce multistage byte displacement pipeline and metadata cache device, and extracts as follows: 1) frame head abandons; 2) pipe shifted: the valid data at frame head rear portion are deposited in the displacement pipeline, the input data are several bytes, the displacement pipeline is just to the several bytes of a side shifting, being positioned at the ducted valid data of displacement overflows, 3) data assembling:, assemble after extracting the data in described displacement pipeline and the metadata cache device according to current state; 4) postamble abandons.
Owing to adopted above scheme, the CRC32 method of calibration has only been used the CRC module of two 8 bits, has saved one 8 bit CRC module, and the number of bits of finishing in a clock cycle reduces, spent a resource shrinkage, and this method can satisfy the requirement of speed.
Travel through all data later on earlier at descrambling code, identify 0x7e, 0x7d, 0xdd, 0x5d, 0x5e and their position, and give subordinate's module these signs, be used for deciding frame and escape and handle the problem of difficult treatment in the time of can conveniently solving the double byte data bus structures and decide frame, introduce the displacement pipeline when extracting LAPS frame payload and solved the problem that byte is exported and postamble abandons.Use the design, economize on resources very much, whole module only needs 350 logical blocks (le), and speed is very fast, can easily reach the clock frequency of 100M on general FPGA.
Description of drawings:
Fig. 1 is a prior art LAPS frame structure;
Fig. 2 is the de-encapsulation method process flow block diagram of prior art synchronous digital hierarchy Link Access Procedure;
The X of the de-encapsulation method of Fig. 3 prior art synchronous digital hierarchy Link Access Procedure
43+ 1 scrambling code decoding circuit figure;
CRC check method flow diagram in the de-encapsulation method of Fig. 4 prior art synchronous digital hierarchy Link Access Procedure;
CRC check method flow diagram in the de-encapsulation method of Fig. 5 synchronous digital hierarchy Link Access Procedure of the present invention;
The LAPS payload of the de-encapsulation method of Fig. 6 synchronous digital hierarchy Link Access Procedure of the present invention extracts flow chart.
Embodiment:
Also the present invention is described in further detail in conjunction with the accompanying drawings below by specific embodiment.
The decapsulation of LAPS need be finished following function:
1:X
43+ 1 motor synchronizing descrambling code
2:LAPS decides frame
3: abandon the rate adapted field
4: abandon and detect the Abort field
The 5:LAPS escape is handled
The detection of 6:LAPS address, control, SAPI field
7:CRC32 calculates
8: abandon the extraction of LAPS frame head, LAPS information payload and abandon postamble
Double byte internal data bus structure makes step 2～step 8 handle more complicated.Be logic LAPS de-encapsulation method process flow block diagram as shown shown in 2.
The function of input interface is: receive data according to input data effective index signal, data-bus width can be that 16 bits, 32 compare top grade.Because the particularity of front-end module might data not come continuously, the input of data just might be desultory, and this requirement has also increased difficulty for the module of back;
Descrambling code process: do the X43+1 descrambling code.The circuit of realizing this part function with FPGA is comparative maturity.This programme also is to adopt conventional method for designing to do, and the specific implementation circuit as shown in Figure 3.
LAPS decides frame process: LAPS and decides the identification that frame comprises LAPS frame head and postamble, and according to the LAPS frame structure, LAPS frame head and postamble are all discerned by frame delimited identifier (0x7e).Double byte internal data bus structure is also given and has been brought trouble here.Our following DS, after the descrambling code:
0x5555、0x557e、0x7e7e、0x5555、0x7e55、0x5555..........
The position of frame delimited identifier (0x7e) is very flexible, and different positions and different word preface combinations all might be represented the different meanings, and 0x7e has 5 kinds of explanations in LAPS:
1:0x7e, 0x55 .... 0x7e represents the LAPS frame head here;
2:0x55,0x7e, 0x7e, 0x55...... first 0x7e here represent the LAPS postamble, represent frame head for second;
On behalf of the LAPS frame head, 3:0x55,0x7e, 0x55...... 0x7e here promptly represent postamble again;
4:0x55,0x7e, 0x7e, 0x7e, 0x55...... first 0x7e here represent postamble, and second is the padding sequence of LAPS interframe, should directly abandon, and the 3rd identifies another
The LAPS frame head arrives.
5:0x55,0x7d, 0x7e...... 0x7e after 0x7d and the abort sequence of 0x7d composition LAPS are interpreted as LAPS postamble and LAPS payload mistake jointly.
For escape character (ESC) (0x7d), also be same, it is in different positions, and the combination of different word prefaces, has different explanations:
1:0x7d, 0x5d ... .. identifies 0x7d
2:0x7d, 0x5e ... .. identifies 0x7e
3:0x7d, 0x7e ... .. sign abort sequence, the postamble of sign LAPS, simultaneously
Identify this frame in the mistake of making a start.
4:0x7d, 0xdd ... the rate adapted byte should directly abandon
5:0x7d, other non-top four kinds of bytes, expression LAPS frame itself is wrong.
The explanation of 0x7d and 0x7e is the core that Link Access Procedure-SDH protocol is handled, and as mentioned above, their intractability has 4 kinds:
1: a variety of explanations are all arranged
2: explaining all has relation with position and the combination of word preface
3: for the double byte data bus structures, their position is very flexible, may appear at optional position (high byte or low byte).
4: data may be come in intermittently, and we must have a good mechanism to remember current state.
For logical design, address the above problem with resource seldom, require design can reach simultaneously than higher speed (100MHz), be difficult really.The solution that we choose is: 1) choose identical with the data/address bus byte number at least two or more comparators, before LAPS decides frame, the later data of unified all descrambling codes of traversal, to compare with above-mentioned comparator that (all there is the hardware comparator module general FPGA inside through the high and low byte of the data of descrambling code, speed is very fast), if frame delimited identifier, escape character (ESC), rate adapted byte, then with respective identification position one, and write down its byte location (being high byte or low byte) simultaneously; A byte has 3 bit-identifies, identify 0x7d, 0x7e, 0xdd respectively,, can search out frame and other spcial characters etc. according to the value and the relative position of these 3 comparative results, such as the abort sequence be exactly the analog value of 0x7d and 0xdd be 1, and the 0x7d position is in front.Sign position is kept in the trigger, removes and new logo position index signal more with next input byte useful signal.Can solve the desultory situation of input data so very easily, the explanation of 0x7e, 0x7d, 0xdd, 0x5d, 0x5e simultaneously only has relation with the byte of adjacent (or front or rear), so after the input of back one beat of data, the state of its last bat just can have been removed.
The data that descrambling code is later after said process, are exported its state and positional information.We are according to the state and the positional information of data, can a step succinct handle LAPS decide frame, escape processing, the rate adapted byte abandons and the function relevant with 0x7d and 0x7e such as fault alarm.Be exactly according to state in fact, use case statement and handle various situations.Program structure is very succinct like this, and the efficient of program is also high.
LAPS decides after frame, escape processing, rate adapted are handled, the abort byte is finished dealing with, and we just can begin the FCS verification of LAPS.Double byte or multibyte data bus structure have also been brought trouble here, for example descend sequence:
0x7e55、0x7d5d、XXXX、0x557d、0x5e55、0x557e..........
Escape after handling is:
0x55XX、0x7dXX、0x55XX、0x7e55、0x55..........
(XX identifies this position does not have data.)
No matter be LAPS frame head, payload or postamble, all might there be the situation of byte, for the FPGA design, the Frame Check Sequence of byte (FCS) calculates and Frame Check Sequence (FCS) calculating of double byte can not shared same module.So as shown in Figure 4, prior art, select two CRC modules (being called for short CRC) for use: one is the CRC32 module (it is finished 8 bit CRC a clock cycle and calculates) of 8 bits, one is the CRC32 module (it is finished 16 bit CRC a clock cycle and calculates) of 16 bits, transmits results of intermediate calculations simultaneously between these two modules mutually.
The CRC32 verification realizes that with FPGA the number of bits of finishing is many more in a clock cycle, spent resource is just many more, and the speed that the while circuit can reach is also just low more.
As shown in Figure 5, the present invention has adopted a reasonable method to come achieve frame verification (CRC32 verification): adopt double byte or multibyte data bus, and in described frame check process, adopt the two or more byte cyclic redundancy check (CRC) modules identical (being called for short the CRC module) with the byte number of data-bus width, they are connected mutually, can transmit intermediate object program mutually between the adjacent byte cyclic redundancy check (CRC) module, each byte cyclic redundancy check (CRC) module can be imported data and output result; Before verification, earlier data are carried out preliminary treatment:,, then effective this byte is put into one of them CRC module if having only the byte data effective if the multibyte valid data are then directly delivered to two or more CRC modules to high and low byte respectively.
For above-mentioned scheme, when being applied to data-bus width is double byte, promptly during the data of 16 bits, described CRC module is two 8 bit CRC modules, and be divided into high byte and low byte CRC module, for the valid data of double byte, send into respectively in high byte and the low byte CRC module, and, be sent in the CRC module of high byte for the valid data of byte.
This method has been opened an openning in the centre of the CRC of 16 bits computing module in fact exactly, and it is divided into two 8 computing module, can import data (low 8 Bit datas of input) and output result from the openning of opening.Can save the computational resource of a CRC8 so completely.The a resource shrinkage of being FPGA like this is a lot, and speed also can reach the requirement of 100MHz.
The process that the LAPS payload extracts is: peel off LAPS frame head (address, control, SAPI field) and LAPS postamble (value of the FCS of 4 bytes).Can run into the problem of byte for double byte internal data bus structure.In order to reduce the time-delay of data, be that LAPS expense limit is peeled off toward next stage module dateout in receipts data limit, limit in inside modules.If not the postamble of payload, do not allow in addition to next stage module output byte.And require to peel off four bytes in front of frame head and 4 bytes in back of postamble for Link Access Procedure-SDH protocol.
The present invention as shown in Figure 6, adopt following LAPS payload leaching process: introduce multistage byte displacement pipeline and metadata cache device, described displacement pipeline progression is at least the frame head byte number and adds one, data assemblings data from displacement pipeline and metadata cache device, and extract as follows: 1) frame head abandons; 2) pipe shifted: the valid data at frame head rear portion are deposited in the displacement pipeline, the input data are several bytes, the displacement pipeline is just to the several bytes of a side shifting, being positioned at the ducted valid data of displacement overflows, 3) data assembling:, assemble after extracting the data in described displacement pipeline and the metadata cache device according to current state; 4) postamble abandons.
Wherein the data in step 3) assemblings can be adopted following method: whether have in the judgment data buffer memory data, displacement pipeline whether displacement, displacement pipe shifted are arranged several bytes, entrance whether detect postamble; If in the buffer and in the displacement pipeline valid data are arranged, then the valid data in the shift stages of valid data in the buffer and displacement pipeline are together taken out, assemble; If no valid data in the buffer and the valid data of non-byte are arranged in the pipeline that is shifted then take out the ducted valid data of displacement to assemble;
Wherein the process of step 4) is: when entrance detected postamble, the ducted postamble byte that then will be shifted abandoned, and directly the remaining valid data of assembling displacement pipeline, if there are data metadata cache the inside, then took out in the lump.If remain a byte at last, then take out this byte.
With data-bus width is that the LAPS payload of 16 bits is extracted as example, introduce 5 grades of byte displacement pipelines and be respectively the first order, the second level, the third level, the fourth stage and level V displacement pipeline and a data buffer storage, data assemblings data from the fourth stage and level V displacement pipeline and buffer, detailed process is as follows:
Frame head abandons: introduce a counter, begin byte count from the LAPS frame head, the later byte of nybble is put into pipeline.Counter zero setting in the LAPS postamble begins counting at the LAPS frame head.
Pipe shifted: when input data when being two effective bytes, pipeline two bytes that move right.When input when input data when being an effective byte, the pipeline byte that moves right.
Metadata cache:, these byte data are deposited in the buffer if when the valid data that displacement can only be overflowed in the pipeline are a byte;
Data assemblings: as shown in Figure 6, the data assembling be that data 4 and the level V ducted data that are shifted are data 5 data from buffer, the fourth stage ducted data that are shifted.When fetching data, judge current state, promptly metadata cache the inside whether have data, displacement pipeline whether displacement, displacement pipe shifted are arranged several bytes, entrance whether detect postamble, confirm whether fetch data and get that local data.Specifically following situation is arranged:
(1): but there is not the shift motion entrance to detect postamble as pipeline, and the data of buffer the inside will be assembled output together with ducted the 5th byte so.
(2): but there is not the shift motion entrance not detect postamble as pipeline, so at this time continue to wait for and can not assemble.
(3): do not have data as buffer, but at this time pipe shifted a byte, data temporarily arrive buffer so.
(4): as buffer data are arranged, but at this time pipe shifted a byte, buffer data and ducted the 5th byte assemble output together so.
If current in a word have only a byte to export, so just temporarily be put in buffer, wait for and raised together 2 directly assembling outputs later on.If current have two directly can export, so just directly output.
Postamble (LAPS FCS field) abandons: when entrance detected the LAPS postamble, the first order ducted data that are shifted were that data 1 to the fourth stage ducted data that are shifted are that data 4 are four FCS fields certainly so, promptly should abandon; So be the level V ducted data that are shifted data 5 directly, the data of buffer the inside are exported in the lump if there are data current cache device the inside.
Adopt above-mentioned LAPS payload leaching process, solved the byte problem very easily and the LAPS postamble abandons problem.The resource that is consumed is also fewer, and speed is also fast.The present invention still can be useful for 24bit, and 32bit even wideer internal bus have very strong autgmentability, can satisfy different SDH speed very easily.
Claims (10)
1. the de-encapsulation method of a synchronous digital hierarchy Link Access Procedure comprises following process at least:
LAPS decides frame;
Frame check;
The LAPS payload extracts;
It is characterized in that:
Adopt double byte or multibyte data bus, and in described frame check process, adopt the two or more byte cyclic redundancy check (CRC) modules identical with the byte number of data-bus width, they are connected mutually, can transmit intermediate object program mutually between the adjacent byte cyclic redundancy check (CRC) module, each byte cyclic redundancy check (CRC) module can be imported data and output result; Before verification, earlier data are carried out preliminary treatment: if the multibyte valid data, then directly each byte is delivered to two or more byte cyclic redundancy check (CRC) modules respectively, if have only the byte data effective, then effective this byte is put into one of them byte cyclic redundancy check (CRC) module.
2, the de-encapsulation method of synchronous digital hierarchy Link Access Procedure as claimed in claim 1, it is characterized in that: described data-bus width is a double byte, i.e. 16 bits, described CRC module is two 8 bit CRC modules, be divided into high byte and low byte CRC module,, send into respectively in high byte and the low byte CRC module for the valid data of double byte, for the valid data of byte, be sent in the CRC module of high byte.
3, the de-encapsulation method of synchronous digital hierarchy Link Access Procedure as claimed in claim 1, it is characterized in that: choose identical with the data/address bus byte number at least two or more comparators, before LAPS decides frame, the later data of unified all descrambling codes of traversal, to compare through the high and low byte of the data of descrambling code with above-mentioned comparator, if frame delimited identifier, escape character (ESC), rate adapted byte,, and write down its byte location simultaneously then with position, respective identification position.
4, the de-encapsulation method of synchronous digital hierarchy Link Access Procedure as claimed in claim 3 is characterized in that: described sign position is kept in the trigger, removes and new logo position index signal more with next input byte useful signal.
5, as the de-encapsulation method of the described synchronous digital hierarchy Link Access Procedure of any one claim in the claim 1 to 4, it is characterized in that: the extracting method of described LAPS payload is to introduce multistage byte displacement pipeline and metadata cache device, and extracts as follows: 1) frame head abandons; 2) pipe shifted: the valid data at frame head rear portion are deposited in the displacement pipeline, the input data are several bytes, the displacement pipeline is just to the several bytes of a side shifting, being positioned at the ducted valid data of displacement overflows, 3) data assembling:, assemble after extracting the data in described displacement pipeline and the metadata cache device according to current state; 4) postamble abandons.
6, the de-encapsulation method of synchronous digital hierarchy Link Access Procedure as claimed in claim 5 is characterized in that: described displacement pipeline progression is at least the postamble byte number and adds one.
7, the de-encapsulation method of synchronous digital hierarchy Link Access Procedure as claimed in claim 5 is characterized in that: when the valid data that overflow in the displacement pipeline are a byte, these byte data are deposited in the buffer.
8, the de-encapsulation method of synchronous digital hierarchy Link Access Procedure as claimed in claim 5 is characterized in that: wherein the state of step 3) data assemblings time institute's basis comprises: whether have in the metadata cache data, displacement pipeline whether displacement, displacement pipe shifted are arranged several bytes, entrance whether detect postamble; If in the buffer and in the displacement pipeline valid data are arranged, then the valid data in the shift stages of valid data in the buffer and displacement pipeline are together taken out, assemble; If no valid data in the buffer and the valid data of non-byte are arranged in the pipeline that is shifted then take out the ducted valid data of displacement and assemble.
9, the de-encapsulation method of synchronous digital hierarchy Link Access Procedure as claimed in claim 5, it is characterized in that: the step 1) frame head abandons also and comprises: introduce a counter, begin byte count from frame head, the later byte of frame head is put into pipeline, and counter is zero setting in postamble.
10, the de-encapsulation method of synchronous digital hierarchy Link Access Procedure as claimed in claim 5, it is characterized in that: wherein the process that abandons of step 4) postamble is: when entrance detects postamble, the ducted postamble byte that then will be shifted abandons, and the valid data in assembling displacement remaining valid data of pipeline and/or the buffer.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1750411B (en) * | 2004-09-13 | 2012-02-22 | 安华高科技杰纳勒尔Ip（新加坡）私人有限公司 | Method and system for detecting cyclic redundency code calculation |
| CN101374035B (en) * | 2008-09-19 | 2012-09-05 | 中兴通讯股份有限公司 | Decoding method and system for GBIT passive optical network and framing method |
| CN104158650A (en) * | 2014-07-15 | 2014-11-19 | 南京航空航天大学 | AES encryption/decryption circuit based on data redundancy error detection mechanism |
| CN106899371A (en) * | 2015-12-18 | 2017-06-27 | 中兴通讯股份有限公司 | Method for synchronizing time and device |
| CN110109615A (en) * | 2019-03-28 | 2019-08-09 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Byte stream escape character hardware processing method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1138391C (en) * | 1999-07-14 | 2004-02-11 | 邮电部武汉邮电科学研究院 | Frame encapsulation of adaptation method for making internet be compatible with synchronous digital system |
| CN1250294A (en) * | 1999-07-27 | 2000-04-12 | 邮电部武汉邮电科学研究院 | Adaption method for fusion of Ethernet with synchronizing digital system or synchronizing optical network |
| US6732318B2 (en) * | 2001-04-03 | 2004-05-04 | Sun Microsystems, Inc. | Variable width parallel cyclical redundancy check |
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2003
- 2003-02-20 CN CNB031040640A patent/CN1319342C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1750411B (en) * | 2004-09-13 | 2012-02-22 | 安华高科技杰纳勒尔Ip（新加坡）私人有限公司 | Method and system for detecting cyclic redundency code calculation |
| CN101374035B (en) * | 2008-09-19 | 2012-09-05 | 中兴通讯股份有限公司 | Decoding method and system for GBIT passive optical network and framing method |
| CN104158650A (en) * | 2014-07-15 | 2014-11-19 | 南京航空航天大学 | AES encryption/decryption circuit based on data redundancy error detection mechanism |
| CN104158650B (en) * | 2014-07-15 | 2017-05-10 | 南京航空航天大学 | AES encryption/decryption circuit based on data redundancy error detection mechanism |
| CN106899371A (en) * | 2015-12-18 | 2017-06-27 | 中兴通讯股份有限公司 | Method for synchronizing time and device |
| CN106899371B (en) * | 2015-12-18 | 2020-12-11 | 中兴通讯股份有限公司 | Time synchronization method and device |
| CN110109615A (en) * | 2019-03-28 | 2019-08-09 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Byte stream escape character hardware processing method |
| CN110109615B (en) * | 2019-03-28 | 2022-08-30 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Hardware processing method for escape character of byte stream |
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| CN1319342C (en) | 2007-05-30 |
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