CN1523510A

CN1523510A - Method and apparatus for repeated data downloading to in situ programmable gate array

Info

Publication number: CN1523510A
Application number: CNA031044964A
Authority: CN
Inventors: 刘芳斌; 杨武翰
Original assignee: BenQ Corp
Current assignee: BenQ Corp
Priority date: 2003-02-18
Filing date: 2003-02-18
Publication date: 2004-08-25
Anticipated expiration: 2023-02-18
Also published as: CN1266621C

Abstract

The invention provides a method for downloading data to a field programmable gate array (FPGA) repeatedly, the character lies in, it uses a complex program logic device (CPLD) to configure and write into a nonvolatile random access memory (NVRAM) and write into a field programmable gate array, and matches with a connector which contains a testing circuit, which is used to judge if the invention uses the connector to connect according to the test state by input the testing circuit to FPGA control function CPLD element, if the state is logic low, then executes and read the data in NVRAM and writes into FPGA.

Description

But the repeated downloads data are to the method and the device of field programmable gate array

Technical field

The present invention is relevant for programmable element (programmable devices), but especially a kind of repeated downloads data to a field programmable gate array (Field Programmable Gate Array, abbreviation FPGA) method and device, it is easy to revise (easily re-configure) this field programmable gate array, to increase research and development (R﹠amp; And then save the cost of product development and the speed of upgrading D) and the convenience of upgrading when (upgrade).

Background technology

In integrated circuit (IC) design field, because field programmable gate array element (FPGA devices) can offer the chance of IC design simulation and test mistake, therefore be widely used in recent years in the IC designs in fields such as multimedia, workstation, electronic communication and network.

The structure of field programmable gate array element (FPGA device) mainly adopts static RAM basis (SRAM Base) and two kinds of Design Modes of anti-fuse (Anti-fuse), wherein, above-mentioned application generally adopts the pattern of static RAM basic schema as the IC design.

Yet, though but the static RAM basic schema has overprogram (reprogrammable), power consumption is low and can form advantages such as (in-circuit configurable) on line, but must carry out data by the outside in its operation and download (data download), therefore, its operation usefulness will be decided on the download circuit of cooperation.

Fig. 1 is the schematic internal view of a typical field programmable gate array element download circuit product.As shown in fig. 1, be that field programmable gate array element (FPGA device) is downloaded in institute's development product at present on the market, majority is to utilize nonvolatile memory (Non-Volatile Random Access Memory is called for short NVRAM) to deposit the required numeric data code of design circuit in the FPGA element.Yet such application must possess the circuit control access circuit 16 of two kinds of functions; Circuit control access circuit 16 first functions are to accept outside down loading updating numeric data code between nonvolatile memory 14, circuit control access circuit 16 another part functions then in order to the numeric data code in the reading non-volatile storage 14 to FPGA element 12.Above-mentioned these circuit can be incorporated on the same printed panel 10 mostly, and so, the circuit that the user designs in development can be very easily to FPGA makes an amendment.When product enters volume production, also can be under the situation of not revising board circuit direct data download sign indicating number.But, after in case product is released, the general function that just no longer needs to write the numeric data code of NVRAM, and this part circuit 16 has comprised the data download sign indicating number to 14 function between nonvolatile memory 14 and reading non-volatile storage, can produce the problem of cost of idleness like this.In addition entering batch process during the stage, some product can be with above-mentioned two parts separately, only keeps the required operational code (operating code) of NVRAM 14 to FPGA 12.At this moment, element 16 among Fig. 1 no longer is present in this circuit board 10, carrying out data if necessary downloads when revising FPGA and include, then need NVRAM is taken out, write with existing CD writer or alternate manner, though solved cost waste problem like this, but the not convenient property can cause research and development time the and increase the product of user's end the degree of difficulty when if version updating or function upgrading are arranged.

Summary of the invention

Therefore, a purpose of the present invention is for providing a kind of data to of repeated downloads effectively field programmable gate array (Field Programmable Gate Array, abbreviation FPGA) method, it is easy to revise (easily re-configure) this field programmable gate array and includes, to increase research and development (R﹠amp; D) convenience the time, and then save the cost of product development.

The invention provides a kind of method of the data to of repeated downloads effectively field programmable gate array, it has downloads the ability of (repeatedly on-board download) data to FPGA on the repeat plate, convenience in the time of can increasing upgrading (upgrade), and then the speed of quickening product up-gradation.This method comprises the following step: use complicated programmable logic element (Complex Programmable Logic Device, be called for short CPLD) dispose and write to a nonvolatile RAM (Non-Volatile RandomAccess Memory, be called for short NVRAM) and write to a field programmable gate array (FieldProgrammable Gate Array, abbreviation FPGA) control function, and the collocation use comprises a testing circuit at interior connector (connector) for one group, decide complicated programmable logic element whether to utilize this group connector to be connected in order to export a detected state (detection state) to according to this testing circuit with the CPLD element that writes the FPGA control function, if this detected state is a logic low, then carry out the action that data write NVRAM, if this detected state is a logic high, then carries out and read the NVRAM internal data to write the action among the FPGA.So, just (on-borad) repeated downloads data have facility and efficient (re-configuration convenience andperformance) in the modification to FPGA onboard.

Description of drawings

For allow above-mentioned and other purpose of the present invention, feature, can be more apparent with advantage, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail as follows:

Fig. 1 shows the inside calcspar of a typical field programmable gate array (Field Programmable Gate Array is called for short FPGA) download circuit;

Fig. 2 shows a field programmable gate array of the present invention (Field Programmable Gate Array is called for short FPGA) download system calcspar;

The road embodiment of live once that Fig. 2 structure is constituted according to the present invention of Fig. 3 system; And

Fig. 4 show one according to the present invention the inside enlarged drawing of Fig. 3 connector.

Symbol description

1: data bus;

2: control signal wire;

10: circuit board;

14: nonvolatile memory;

16: circuit control access circuit;

21: main frame;

23: interface;

24,25: field programmable gate array;

201,202: download circuit;

203,212: the control square;

205,217: connector;

204,209,213-215,219: pin;

218: bidirectional bus;

303,304: testing circuit;

VCC: operating voltage;

Embodiment

Fig. 2 shows a field programmable gate array of the present invention (Field Programmable Gate Array is called for short FPGA) download system calcspar.In Fig. 2, native system mainly comprises: a main frame 21, so that the data (data) that are downloaded to field programmable gate array source to be provided; One first download circuit 201, in order to transmission information, this information is the Data Update usefulness of download end, and provides control signal control to download; One second download circuit 202, in order to receive information from first download circuit, write to a nonvolatile RAM (Non-Volatile Random Access Memory is called for short NVRAM), this nonvolatile RAM can be a flash memory (not shown); After the data from the outside write nonvolatile RAM, after finishing the renewal of numeric data code, just can read in to a main field programmable gate array 24 (master FPGA) and use this moment, wherein, this main field programmable gate array 24 can convert the information (from main frame) that is received to the form that a less important field programmable gate array 25 (slave FPGA) can receive and use.

As shown in Figure 2, suppose that desired data has been downloaded and when being stored in the NVRAM storer, by control signal wire 2, the data in the NVRAM storer can be sent to element 202 through data bus 1 simultaneously.Then, when the execution data write to the action of FPGA, data can be imported the form (format) that element 24 can receive and use into by element 202 earlier, if be connected in series a less important FPGA element 25 in addition behind the element 24, then write in the FPGA element 25 by element 24 again.If revise or during design circuit data that testing element 24 or element 25 include, can connect second connector 217 and control can be transferred to element 201 from element 202 by control signal wire 2, the first connectors 205.At this moment, one external signal Erase can be by pin 209 inputs, assign the required pin done that controls signal to element 201 to remove the legacy data in (erase) NVRAM storer by interface 23, then, main frame 21 via pin Din, pc-clk and connector 205,217, directly writes new data in the NVRAM storer again.Now with the operation instructions of 201,202 of download circuit in after.

The road embodiment of live once that Fig. 2 structure is constituted according to the present invention of Fig. 3 system.In Fig. 3, element 201 comprises one first control square and this first connector 205, and element 202 comprises this second connector 217, a NVRAM storer 211 and one second control square 212.Wherein,

element

201 and 202 is two unit independently, utilizes built-in separately

connector

205 and 217 to connect (communication) mutually.

As shown in Figure 3, the present invention adds a testing circuit (aftermentioned), and the FPGA download circuit is divided into writes NVRAM (first) download circuit 201 and write FPGA (second) download circuit 202 two parts, to reach the purpose of effectively controlling cost and taking into account convenience.Wherein, the function of controlling

square

203 and 212 is to realize with complicated programmable logic element (Complex Programmable Logic Device is called for short CPLD), and configuration square 203 needs the capacity of usefulness greater than square 212.In addition, two parts 201,202 utilize the connector 205 of a pair of n+13 of having root pin, 217 are connected, wherein, n representative writes the figure place of the address bus 207 required usefulness of NVRAM storer 211, and 13 pins then are that 8 bit data bus 208 add that 4 control signals (are the pin (clock signal pin) 204 of pin (detectionstate signal pin 215)+clock signal of detected state signal 206 of pin (write enable signal pin)+testing circuit of pin (output enable signal pin)+the write enable signal of pin (chip enables ignal pin)+output enable signal oe of chip enable signal ce.Again, circuit 201,202 utilize CPLD to download pin 214 comes the activation download action, download cable (downloadcable) is transmitted from main frame 21 (Fig. 2) will write the numeric data code of NVRAM storer 211 to circuit 201, the numeric data code that maybe will be stored in the NVRAM storer 211 is sent among the FPGA 24 and 25 (Fig. 2) in serial transmission (serial transmission) mode via initialized square 212, the execution of wherein, initialization (initialization) is to send initializing signal init (through pin 213) by element 24 to finish to square 212 and element 25.For the action of each chip synchronously, be to send the clock signal pin 204,210 of main clock signal C CLK (Fig. 2) to each chip in this example by element 24 again.Each control signal that is sent to element 202 by element 24 can be passed through a control signal pin 219, and element 212 can be moved to the processing that element 211 reads or writes.The action of reading or write NVRAM storer 211 is to carry out via bidirectional bus 218.Under the situation that aforementioned connector was opened in 205,217 minutes, can independently carry out the action that data are read NVRAM storer 211.But when writing NVRAM storer 211, just must tell all data of element 212 suspension joints (floating) and signal pin to become high impedance (high impedance) by the detected state signal pin 215 of testing circuit.The testing circuit that then will be built in the connector is illustrated in down.

Fig. 4 show one according to the present invention the inside enlarged drawing of Fig. 3 connector.In Fig. 4, connector of the present invention also comprises a testing circuit 303,304 except the electrical connection function (electrically connecting function) of the signals such as clock signal C CLK, data-signal Data, address signal Addr and control signal Ctrl that have Fig. 3 and address.

As shown in Figure 4, mainly be that configuration one detects resistor R (about about 10K ohm) at connector 205 ends (side) (daughter board) configurations one ground short circuit pins (grounded shorted-circuit pin) 303 and between the pin 215 of connector 217 ends (motherboard) and operating voltage VCC at testing circuit.So, when two connectors 205,217 did not connect, pin 215 was in (open circuit) state that opens circuit, so the voltage logical value is 1 (noble potential).On the other hand, after two connectors 205,217 connected, pin 215 became path (pathway) state, caused the voltage logical value to become 0 (electronegative potential).In view of the above, just can determine that present data are to flow into or outflow element 211, just, sense data if pin 215 output electronegative potentials are then represented certainly writes data in the element 211 in element 24 in element 211 if pin 215 output noble potentials are then represented.

Though the present invention with a preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under situation without departing from the spirit or scope of the invention; can change and modification, so protection scope of the present invention is as the criterion with the claim restricted portion that is proposed.

Claims

1. but the method for repeated downloads data to a field programmable gate array (FPGA), it is characterized in that, use complicated programmable logic element (CPLD) to control to write numeric data code to a nonvolatile RAM (NVRAM) and read this numeric data code and write to the control function of a field programmable gate array (FPGA) from this nonvolatile RAM, and the collocation use comprises a testing circuit at interior connector for one group, decide complicated programmable logic element whether by this group connector data download in order to export this detected state to according to this testing circuit with the CPLD element that writes the FPGA control function, if this detected state is one first logic level, then carry out the action that these data write NVRAM, if this detected state is one second logic level, then carries out and read the NVRAM internal data to write the action among the FPGA.

2. but the method for repeated downloads data to a field programmable gate array as claimed in claim 1, wherein, this capacity with the CPLD element that writes the NVRAM control function has the capacity of the CPLD element that writes the FPGA control function greater than this.

3. but the method for repeated downloads data to a field programmable gate array as claimed in claim 1, wherein, the part of this testing circuit disposes a resistor between a peripheral operation voltage and a detection signal pin, in order to export through this detection signal pin in the CPLD element that this detected state to this tool writes the FPGA control function, its another part disposes a ground short circuit circuit, open circuit and have noble potential when two connectors separate, to form, make this detected state be output as this first logic level, and when two connectors join, form path and have electronegative potential, make this detected state be output as this second logic level.

4. but the method for repeated downloads data to a field programmable gate array as claimed in claim 3, wherein, this short circuit current uses a lead.

5. but the device of repeated downloads data to a field programmable gate array (FPGA) comprising:

One nonvolatile RAM;

One first control square has one first complicated programmable logic element (CPLD), and configuration receives and write the control function of a renewal numeric data code to this nonvolatile RAM (NVRAM) in it;

One first connector, this first connector include one first testing circuit and are connected to this first control square, to receive this renewal numeric data code that this first control square transmits;

One second control square, have one second complicated programmable logic element (CPLD), configuration is read this renewal numeric data code in this nonvolatile RAM and will be upgraded the control function that numeric data code writes to a field programmable gate array (FPGA) in it; And

One second connector, connect this second control square, this second connector has one second testing circuit, and this second testing circuit transmits a detected state signal to this second control square, and this second connector is in order to optionally to be connected with this first connector and to separate;

Wherein when this first connector separates with this second connector, when this detected state signal presents one first current potential, make this second control square read in this renewal numeric data code of this nonvolatile RAM inside and write in the field programmable gate array, when this first connector is connected with this second connector, this second testing circuit connects this first testing circuit, make this detected state signal present one second current potential, this first control square transmits this renewal numeric data code and writes this nonvolatile RAM.

6. but the device of repeated downloads data to a field programmable gate array as claimed in claim 5, wherein, this first control square receives an outside control signal, this control signal comprises that a chip enable signal writes enable signal with the output, one of enable data and signal and writes to action, and the detected state signal of a testing circuit of this nonvolatile RAM element with enable data to start above-mentioned each element, an output enable signal, with transmit and according to this determination data this NVRAM element write or reads action.

7. but the device of repeated downloads data to a field programmable gate array as claimed in claim 5, wherein, this second control square receives the clock signal from this FPGA element, with synchronous each related elements.

8. but the device of repeated downloads data to a field programmable gate array as claimed in claim 5, wherein this first testing circuit is made of an earth lead, this second testing circuit comprises a resistor, one first end of this resistor connects an external voltage, one second end transmits this detected state signal to this second control square, when this first connector was connected with this second connector, this second end was electrically connected on this earth lead.

9. but the device of repeated downloads data to a field programmable gate array as claimed in claim 7, wherein each related elements comprises this nonvolatile RAM, this first control square and this second control square.

But 10. the device of repeated downloads data to a field programmable gate array as claimed in claim 5, this first current potential is a noble potential, this second current potential is an electronegative potential.