CN1521837A - Process of making mask ROM and arrangement thereof - Google Patents
Process of making mask ROM and arrangement thereof Download PDFInfo
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- CN1521837A CN1521837A CNA031026907A CN03102690A CN1521837A CN 1521837 A CN1521837 A CN 1521837A CN A031026907 A CNA031026907 A CN A031026907A CN 03102690 A CN03102690 A CN 03102690A CN 1521837 A CN1521837 A CN 1521837A
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Abstract
A method for making mask ROM comprises the steps of, forming in sequence a grid dielectric layer and a plurality of strip-shaped conductor layer on a substrate, and forming a dielectric layer on the substrate and the first conductor layer, then patterning the dielectric layer to form a plurality of coding openings, wherein each of the coding opening exposes the first conductor layer, and forming a plurality of well regions in the first conductor layer on the bottom of the coding opening, then and forming a plurality of strip-shaped second conductor layers on the dielectric layer and in the coding opening, electrically connecting them to the well regions so as to form a diode memory element array, which can be stacked into a plurality of layers to increase the degree of integrity of the elements.
Description
Technical field
The invention relates to a kind of read-only memory (Read Only Memory, manufacture method ROM), and particularly relevant for the manufacture method of a kind of mask-type ROM (Mask ROM).
Background technology
Because read-only memory has non-volatile (Non-Volatile) characteristic of not losing wherein stored data because of power interruptions, therefore all must possess this type of internal memory in many electric equipment products, the normal running when starting shooting to keep electric equipment products.In the read-only memory the most the basis a kind of promptly be mask-type ROM, general mask-type ROM commonly used utilizes channel transistor to be used as memory cell, and in sequencing (Program) stage optionally implanting ions to the channel appointed zone, by changing the purpose that start voltage (Threshold Voltage) reaches control store unit conducting in read operation (On) or closes (Off).
As mentioned above, the memory cell arrays of mask-type ROM normally is made of transistorized kenel, yet this kind has following problem with the mask-type ROM that transistor constitutes memory cell arrays:
Because transistor is higher for the quality requirements of the silicon base below it, grid oxic horizon etc., therefore its manufacture craft condition is comparatively harsh, and, because this factor, make memory cell arrays that this kind constitutes with transistor and being not easy upwards more than storehouse one deck.
And the memory cell arrays of transistor version can be because factors such as leakage currents, makes its decoding nargin of 0/1 less and clear inadequately (clear), and therefore the situation of decoding error takes place quite easily.
And, form because its bit line of memory cell arrays of transistor version is used in the mode of implanting admixture in the substrate usually, however its connect face and can shoal along with dwindling of element, thereby cause the rising of bit line resistance, influence the operation usefulness of element.
Summary of the invention
Therefore, purpose of the present invention is exactly in manufacture method that a kind of mask-type ROM is provided and structure, can dwindle size of component and improve the integrated level of element.
A further object of the present invention is exactly in manufacture method that a kind of mask-type ROM is provided and structure, comparatively clear and definite decoding ability can be provided and improve the nargin of decoding.
Another purpose of the present invention is exactly in manufacture method that a kind of mask-type ROM is provided and structure, service speed that can lift elements.
Another object of the present invention is exactly in manufacture method that a kind of mask-type ROM is provided and structure, and its manufacture craft that forms mask-type ROM is comparatively simple.
The present invention proposes a kind of manufacture method of mask-type ROM, the method forms plural number first conductor layer of gate dielectric and strip in regular turn in a substrate, the structure of this first conductor layer is compound crystal silicon/metal silicide/compound crystal silicon, forms first dielectric layer again on the substrate and first conductor layer.Then, patterning first dielectric layer is to form the first coding opening of plural number, and wherein each first coding open bottom exposes first conductor layer, forms first well region of plural number again in first conductor layer of the first coding open bottom.Then, form plural number second conductor layer of strip on first dielectric layer with in the first coding opening, wherein second conductor layer electrically connects first well region.To form one first memory cell arrays.
And, in above-mentioned manufacture method, after forming first memory cell arrays, more can on first dielectric layer and second conductor layer, form second dielectric layer, on second dielectric layer, form plural number the 3rd conductor layer of strip again, on second dielectric layer and the 3rd conductor layer, form the 3rd dielectric layer then, patterning the 3rd dielectric layer is to form the second coding opening of plural number again, wherein each second coding opening exposes the 3rd conductor layer bottom, then in the 3rd conductor layer of the second coding open bottom, form second well region of plural number, on the 3rd dielectric layer with in the second coding opening, form plural number the 4th conductor layer of strip again, wherein the 4th conductor layer electrically connects second well region, to form one second memory cell arrays.
The present invention proposes a kind of structure of mask-type ROM, comprises plural number first conductor layer, one first dielectric layer, a plurality of first well region of a substrate, gate dielectric, strip at least, plural number second conductor layer of strip.Wherein gate dielectric is configured in the substrate, first conductor layer is configured on the gate dielectric, first dielectric layer is disposed on the substrate and first conductor layer, wherein first dielectric layer has a plurality of first coding openings, and the first coding opening exposes the first conductor layer surface, the first well region individual configuration in first conductor layer of the first coding open bottom, and second conductor layer be configured on first dielectric layer with the first coding opening in, wherein second conductor layer electrically connects first well region.And gate dielectric, first conductor layer, first dielectric layer, first well region, the second conductor series of strata constitute one first memory cell arrays.
In said structure, more comprise one second dielectric layer, plural number the 3rd conductor layer of strip, one the 3rd dielectric layer, a plurality of second well region, plural number the 4th conductor layer of strip.Wherein second dielectric layer is configured on first dielectric layer and second conductor layer, the 3rd conductor layer is configured on second dielectric layer, the 3rd dielectric layer is disposed on second dielectric layer and the 3rd conductor layer, wherein the 3rd dielectric layer has a plurality of second coding openings, and the second coding opening exposes the 3rd conductor layer surface, the second well region individual configuration is in the 3rd conductor layer of the second coding open bottom, and the 4th conductor layer be configured on the 3rd dielectric layer with the second coding opening in, wherein the 4th conductor layer electrically connects second well region.And second dielectric layer, the 3rd conductor layer, the 3rd dielectric layer, second well region, the 4th conductor layer constitute one second memory cell arrays.
In addition, in the manufacture method and structure of above-mentioned mask-type ROM, all right storehouse forms second memory cell arrays of plural layer on second memory cell arrays.
Moreover in the manufacture method and structure of above-mentioned mask-type ROM, the material of second conductor layer and the 4th conductor layer comprises metal materials such as aluminium, tungsten, copper.
The present invention proposes a kind of interpretation method of mask-type ROM, this mask-type ROM comprises plurality of word lines at least, be configured in the well region of the plural number on the character line, wherein the dopant profile of character line (N+type) is different from the dopant profile (P+type) of well region, and a plurality of bit lines, its neutrality line is arranged at differing heights perpendicular to character line and with those character lines, and the part confluce of bit line and character line is electrically connected to well region individually, this interpretation method comprises that deciphering the pairing bit line in position to one applies one first voltage, apply one second voltage for other bit line outside this bit line, wherein first voltage is greater than second voltage, the pairing character line of paginal translation code position applies tertiary voltage simultaneously, apply the 4th voltage for other character line outside this character line, wherein the 4th voltage is greater than tertiary voltage.
The memory cell arrays of mask-type ROM of the present invention is owing to be made of diode, make memory cell arrays to make progress storehouse and form the structure of a three-dimensional, therefore, the size of memory cell can be dwindled and the integrated level of memory element can upwards promote.
And, because mask-type ROM of the present invention is judged to be " 1 " in the decoding district (that is being diode) that implants well region, and be judged to be zero in the zone system that does not implant, so its decoding of 0/1 is more clear than the memory cell of transistor version, and the nargin of its decoding is also bigger.
And in mask-type ROM of the present invention, because its bit line can adopt metal material to form, compared to being known in the formed bit line that mixes in the substrate, the formed bit line resistance of the present invention is less, and speed that can the lift elements operation.
In addition, therefore lower because the present invention need not form transistor to the requirement of manufacture craft condition, so the more known manufacture craft of the manufacture craft of manufacturing mask-type ROM of the present invention is simple.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborate.
Description of drawings
Figure 1A to Fig. 1 F is the generalized section according to the manufacturing process of the mask-type ROM of preferred embodiment of the present invention.
Fig. 2 is the schematic diagram of deciphering according to the mask-type ROM of preferred embodiment of the present invention.
Indicate explanation:
100: substrate 102: gate dielectric
104,106,114,118,126: conductor layer 108,116,120: dielectric layer
110,122: coding opening 112,124: well region
202,204,206,208,210,212,214: character line
252,254,256,258: bit line 270: diode
Embodiment
Figure 1A to Fig. 1 F illustrate is the manufacturing process profile of a kind of mask-type ROM of preferred embodiment of the present invention.
At first, please refer to Figure 1A, a substrate 100 is provided, this substrate 100 for example is the semiconductor silicon substrate.And formed the plural conductor layer 104/106 of gate dielectric 102 and strip in substrate 100.Wherein the material of gate dielectric 102 for example is a silica, and the material of conductor layer 104 is doped polycrystalline silicon/metal silicides of N+type, and the material of conductor layer 106 is doped polycrystalline silicon of N+type.The method that forms the conductor layer 104/106 of gate dielectric 102 and strip for example is to form layer of oxide layer (not illustrating) with thermal oxidation method in substrate, in the mode of the dopant ion of coming personally, utilize chemical vapour deposition technique in substrate 100, to form one deck doped polysilicon layer/metal silicide/doped polycrystalline silicon (not illustrating) again.Then, utilize the lithography manufacture craft, this doped polysilicon layer of patterning is to form the plural conductor layer 104/106 of strip.
Then, please refer to Figure 1B, form one dielectric layer 108 on substrate 100 and conductor layer 106, wherein the material of this dielectric layer 108 for example is a silicon dioxide, and the method that forms this dielectric layer 108 for example is to utilize chemical vapour deposition technique to form one deck silicon oxide layer in substrate 100.
Please continue with reference to Figure 1B, in dielectric layer 108, form coding opening 110 to expose predetermined position of deciphering, the method that wherein forms coding opening 110 for example is to utilize coding light shield (not illustrating), on dielectric layer 108, form patterned light blockage layer (not illustrating) to define coding site, then carry out etching process and remove the dielectric layer 108 of part and form coding opening 110, and expose the conductor layer 106 of opening 110 bottoms of encoding.
Then, please refer to Fig. 1 C, form well region 112 on the conductor layer 106 in coding opening 110, the mode that wherein forms this well region 112 for example be continuous be the cover curtain with the patterned light blockage layer, carry out an ion and implant manufacture craft, in conductor layer 106, to form doped region, then, remove patterned light blockage layer, carry out a tempering manufacture craft again and form well region 112, wherein well region 112 has second dopant profile different with first dopant profile (P type dopant profile).
Please continue the C with reference to Fig. 1, the plural conductor layer 114 that forms strip on dielectric layer 108 is with as bit line, and the wherein trend of moving towards vertical conductor layer 106 of conductor layer 114, and conductor layer 114 is inserted in the coding opening 110 and electrically connected with well region 112.The material of this conductor layer 114 for example is metal materials such as aluminium, tungsten, copper.The method that forms this conductor layer 114 for example is to cover the conductor material layer that one deck fills up opening with physical vaporous deposition or chemical vapour deposition technique on dielectric layer 108, and the step of process lithography is to form the plural conductor layer 114 of strip on dielectric layer 108 again.
Through the described step of above-mentioned Figure 1A to Fig. 1 C, can in substrate 100, form the memory cell arrays that one deck is made of diode (finger-type becomes the memory cell of well region 112), then, please continue F, the memory cell arrays that constitutes by diode with another layer of storehouse on memory cell arrays with reference to Fig. 1 D to Fig. 1.
Please refer to Fig. 1 D, on dielectric layer 100 and conductor layer 114, form one dielectric layer 116, wherein this dielectric layer 116 is in order to isolate two-layer different memory cell arrays, its material for example is a silicon dioxide, and the method that forms this dielectric layer 116 for example is to utilize chemical vapour deposition technique to form one deck silicon oxide layer on dielectric layer 100 and conductor layer 114.
Please continue D with reference to Fig. 1, on dielectric layer 116, form the conductor layer 118 of strip, wherein the material of conductor layer 118 for example is the doped polycrystalline silicon of doped polycrystalline silicon/metal silicide/N+type, the method of its formation for example is the mode with the dopant ion of coming personally, utilize chemical vapour deposition technique on dielectric layer 116, to form one deck doped polysilicon layer (not illustrating), utilize the lithography manufacture craft again, this doped polysilicon layer of patterning is to form the plural conductor layer 118 of strip on dielectric layer.
Then, please refer to Fig. 1 E, on dielectric layer 116 and conductor layer 118, form one dielectric layer 120, wherein the material of this dielectric layer 120 for example is a silicon dioxide, and the method that forms this dielectric layer 120 for example is to utilize chemical vapour deposition technique to form one deck silicon oxide layer on dielectric layer 116 and conductor layer 118.
Please continue E with reference to Fig. 1, in dielectric layer 120, form coding opening 122 to expose predetermined position of deciphering, the method that wherein forms coding opening 122 for example is to utilize coding light shield (not illustrating), on dielectric layer 120, form patterned light blockage layer (not illustrating) to define coding site, then carry out etching process and remove the dielectric layer 120 of part and form coding opening 122, and expose the conductor layer 118 of opening 122 bottoms of encoding.
Then, please refer to Fig. 1 F, form well region 124 on the conductor layer 118 in coding opening 122, the mode that wherein forms this well region 124 for example be continuous be the cover curtain with the patterned light blockage layer, carry out an ion and implant manufacture craft, in conductor layer 118, to form doped region, then, remove patterned light blockage layer, carry out a tempering manufacture craft again and form well region 124, wherein well region 124 has and different second dopant profile (P type dopant profile) of compound crystal silicon dopant profile on the conductor layer 124.
Please continue the F with reference to Fig. 1, the plural conductor layer 126 that forms strip on dielectric layer 122 is with as bit line, and wherein the trend of conductor layer 126 is perpendicular to the trend of conductor layer 118, and conductor layer 126 is inserted in the coding opening 122 and electrically connected with well region 124.The material of this conductor layer 126 for example is metal materials such as aluminium, tungsten, copper.The method that forms this conductor layer 126 for example is to cover the conductor material layer that one deck fills up coding opening 122 with physical vaporous deposition or chemical vapour deposition technique on dielectric layer 120, and the step of process lithography is to form the plural conductor layer 126 of strip on dielectric layer 120 again.
Through after the step of above-mentioned Figure 1A to Fig. 1 F, can form and have the two-layer mask-type ROM that constitutes memory cell arrays with diode.Because the follow-up step of finishing the cover screen type internal memory is known by being familiar with this operator, so does not repeat them here.
Please continue with reference to Fig. 1 F so that the structure of cover curtain internal memory of the present invention to be described.Structure with the individual layer memory cell arrays is an example, and mask-type ROM of the present invention is made of the plural conductor layer 114 of the well region 112 of the plural stack layer of substrate 100, gate dielectric 102, strip, plural number, dielectric layer 108, strip.
Gate dielectric 102 is disposed in the substrate 100.And the plural stack layer individual configuration of strip is in gate dielectric 102, wherein each stack layer by conductor layer 104 and conductor layer 106 in regular turn storehouse form, in order to character line as memory element, and conductor layer 106 to have first dopant profile for example be N type dopant profile.
Dielectric layer 108 is disposed on substrate 100 and the stack layer, and wherein dielectric layer 108 has a plurality of coding openings 110, and goes out the surface of conductor layer 106 in the bottom-exposed of coding opening 110.
The well region 112 of plural number is configured in the conductor layer 106 of coding opening 110 bottoms, and wherein well region 112 has second dopant profile different with first dopant profile, for example is P type dopant profile.
The plural conductor layer 114 of strip be disposed on the dielectric layer 108 with coding opening 110 in, in order to bit line as memory element, wherein the trend of conductor layer 114 is perpendicular to the trend of stack layer, and conductor layer 114 electrically connects with well region 112, so that well region 112 confluces that have of conductor layer (character line) 106 and conductor layer (bit line) 114 form a diode memory cell.
The structure of above-mentioned mask-type ROM is the structure of individual layer memory cell arrays, and if the structure of double-deck memory cell arrays, mask-type ROM then of the present invention more comprises well region 124, the dielectric layer 120 of plural conductor layer 118, the plural number of dielectric layer 116, strip, the plural conductor layer 126 of strip.
Wherein dielectric layer 116 is disposed on dielectric layer 108 and the conductor layer 114, in order to isolate two-layer different memory cell arrays.
Plural conductor layer 118 individual configuration of strip on dielectric layer 116, in order to character line as memory element, and conductor layer 118 to have first dopant profile for example be N type dopant profile.
Dielectric layer 120 is disposed on dielectric layer 116 and the conductor layer 118, and wherein dielectric layer 120 has a plurality of coding openings 122, and goes out the surface of conductor layer 118 in the bottom-exposed of coding opening 122.
The well region 124 of plural number is configured in the conductor layer 118 of coding opening 122 bottoms, and wherein well region 124 has second dopant profile (P type dopant profile) different with first dopant profile (N type dopant profile).
The plural conductor layer 126 of strip be disposed on the dielectric layer 120 with coding opening 122 in, in order to bit line as memory element, wherein the trend of conductor layer 126 is perpendicular to the trend of conductor layer 118, and conductor layer 126 electrically connects with well region 124, so that the confluce with well region 124 of conductor layer (character line) 118 and conductor layer (bit line) 126 forms a diode memory cell.Therefore, can access the mask-type ROM that forms by two layer diode memory cell arrays storehouses shown in Fig. 1 F.
Then, please refer to Fig. 2 so that the interpretation method of mask-type ROM of the present invention to be described.In Fig. 2,202 to 214 representatives be character line, 252 to 258 representatives be bit line.Its neutrality line and character line are arranged at differing heights, and on the character line of the part confluce of character line and bit line, be formed with well region (not illustrating) in the position that the implantation deciphered is arranged, and bit line (N+type) and well region (P+type) electrically connect forming a diode, and then character line and bit line do not electrically connect in other confluce of undecoded implantation.With Fig. 2 is example, in the time will deciphering to position 270, paginal translation code position 270 pairing bit lines 254 apply high voltage, 252,256,258 of other bit lines apply low-voltage, simultaneously, position 270 pairing character lines 208 are applied low-voltage, and other character line 202,204,206,210,212,214 applies high voltage.Through this kind decoded mode, then can guarantee when decoding electric current be according to Fig. 2 in route shown by arrows flow, and can not open by mistake the diode that opens position 270 peripheries and cause decoding error.
In above-mentioned preferred embodiment, wherein form the manufacture craft of conductor layer 104 (polycide), form periphery circuit region when making the present invention can be applicable to known mask-type ROM manufacture craft and be provided with, under the situation of not considering periphery circuit region, the present invention can not form conductor layer 104, and directly with the character line of conductor layer 106 (N+doped polysilicon) as memory cell arrays.
And, last preferable stating among the embodiment, forming double-deck memory cell arrays explaining, yet the present invention is not limited thereto, the present invention can also be according to the needs of reality, and then the storehouse number of plies of adjusting its memory cell arrays is to form the memory cell arrays more than two layers.It for example is the step of repetition Fig. 1 D to Fig. 1 F, with on the memory cell arrays of the second layer again storehouse form the memory cell arrays of plural layer.
In sum, because the memory cell arrays of mask-type ROM of the present invention is made of diode, make that the memory cell arrays storehouse one deck that can make progress is above and form the structure of a three-dimensional, therefore, the size of memory cell can be dwindled and the integrated level of memory element can upwards promote.
And, because mask-type ROM of the present invention is judged to be " 1 " in the decoding district (that is being diode) that implants well region, and be zero at the regional determination of not implanting, so its decoding of 0/1 is more clear than the memory cell of transistor version, and the nargin of its decoding is also bigger.
And in mask-type ROM of the present invention, because its bit line can adopt metal material to form, compared to being known in the formed bit line that mixes in the substrate, the formed bit line resistance of the present invention is less, and speed that can the lift elements operation.
In addition, therefore lower because the present invention need not form transistor to the requirement of manufacture craft condition, so the more known manufacture craft of the manufacture craft of manufacturing mask-type ROM of the present invention is simple.
Though the present invention with a preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (25)
1, a kind of manufacture method of mask-type ROM is characterized in that: comprise the following steps:
In a substrate, form plural number first conductor layer of gate dielectric and strip in regular turn;
On this substrate and those first conductor layers, form one first dielectric layer;
This first dielectric layer of patterning is to form the first coding opening of plural number, and wherein each those first coding open bottom exposes those first conductor layers;
In those first conductor layers of those first coding open bottom, form first well region of plural number; And
Form plural number second conductor layer of strip on this first dielectric layer with in those first coding openings, wherein those second conductor layers electrically connect those first well regions, to form one first memory cell arrays.
2, the manufacture method of mask-type ROM as claimed in claim 1 is characterized in that: the material of those first conductor layers comprises doped polycrystalline silicon.
3, the manufacture method of mask-type ROM as claimed in claim 1 is characterized in that: the dopant profile of those first conductor layers is different from the dopant profile of those first well regions.
4, the manufacture method of mask-type ROM as claimed in claim 1 is characterized in that: the material of those second conductor layers comprise be selected from group that aluminium, tungsten and copper organizes one of them.
5, the manufacture method of mask-type ROM as claimed in claim 1 is characterized in that: the trend of those first conductor layers is perpendicular to the trend of those second conductor layers.
6, the manufacture method of mask-type ROM as claimed in claim 1 is characterized in that: also be included in and form a character line between each those grid oxic horizon and each those first conductor layer.
7, the manufacture method of mask-type ROM as claimed in claim 1 is characterized in that: form after the step of those second conductor layers of strip on this first dielectric layer with in those first coding openings, also comprise:
(a) on this first dielectric layer and those second conductor layers, form one second dielectric layer;
(b) plural number the 3rd conductor layer of formation strip on this second dielectric layer;
(c) on this second dielectric layer and those the 3rd conductor layers, form one the 3rd dielectric layer;
(d) patterning the 3rd dielectric layer is to form the second coding opening of plural number, and wherein each those second coding opening exposes those the 3rd conductor layer bottoms;
(e) in those the 3rd conductor layers of those second coding open bottom, form the second plural well region; And
(f) form plural number the 4th conductor layer of strip on the 3rd dielectric layer with in those second coding openings, wherein those the 4th conductor layers electrically connect those second well regions, to form one second memory cell arrays.
8, the manufacture method of mask-type ROM as claimed in claim 7 is characterized in that: the material of those the 3rd conductor layers comprises doped polycrystalline silicon.
9, the manufacture method of mask-type ROM as claimed in claim 7 is characterized in that: the dopant profile of those the 3rd conductor layers is different from the dopant profile of those second well regions.
10, the manufacture method of mask-type ROM as claimed in claim 7 is characterized in that: the material of those the 4th conductor layers comprise be selected from group that aluminium, tungsten and copper organizes one of them.
11, the manufacture method of mask-type ROM as claimed in claim 7 is characterized in that: the trend of those the 3rd conductor layers is perpendicular to the trend of those the 4th conductor layers.
12, the manufacture method of mask-type ROM as claimed in claim 7 is characterized in that: also comprise the step of repetition (a)～(f), more to form plural layer second memory cell arrays on this second memory cell arrays.
13, a kind of structure of mask-type ROM is characterized in that: comprising:
One substrate;
Gate dielectric is configured in this substrate;
Plural number first conductor layer of strip is configured on those gate dielectrics;
One first dielectric layer is disposed on this substrate and those first conductor layers, and wherein this first dielectric layer has a plurality of first coding openings, and those first coding openings expose those first conductor layer surfaces;
A plurality of first well regions, individual configuration is in those first conductor layers of those first coding open bottom; And
Plural number second conductor layer of strip, be configured on this first dielectric layer with those first coding openings in, wherein those second conductor layers electrically connect those first well regions, and those gate dielectrics, those first conductor layers, this first dielectric layer, those first well regions, those second conductor layers constitute one first memory cell arrays.
14, the structure of mask-type ROM as claimed in claim 13 is characterized in that: the material of those first conductor layers comprises doped polycrystalline silicon/metal silicide/N+type doped polycrystalline silicon.
15, the structure of mask-type ROM as claimed in claim 13 is characterized in that: the dopant profile of those first conductor layers is different from the dopant profile of those first well regions.
16, the structure of mask-type ROM as claimed in claim 13 is characterized in that: the material of those second conductor layers comprise be selected from group that aluminium, tungsten and copper organizes one of them.
17, the structure of mask-type ROM as claimed in claim 13 is characterized in that: the trend of those first conductor layers is perpendicular to the trend of those second conductor layers.
18, the structure of mask-type ROM as claimed in claim 13 is characterized in that: have more a character line, be disposed between each those grid oxic horizon and each those first conductor layer.
19, the structure of mask-type ROM as claimed in claim 13 is characterized in that: have more:
One second dielectric layer is configured on this first dielectric layer and those second conductor layers;
Plural number the 3rd conductor layer of strip is configured on this second dielectric layer;
One the 3rd dielectric layer is disposed on this second dielectric layer and those the 3rd conductor layers, and wherein the 3rd dielectric layer has a plurality of second coding openings, and those second coding openings expose those the 3rd conductor layer surfaces;
A plurality of second well regions, individual configuration is in those the 3rd conductor layers of those second coding open bottom; And
Plural number the 4th conductor layer of strip, be configured on the 3rd dielectric layer with those second coding openings in, wherein those the 4th conductor layers electrically connect those second well regions, and this second dielectric layer, those the 3rd conductor layers, the 3rd dielectric layer, those second well regions, those the 4th conductor layers constitute one second memory cell arrays.
20, the structure of mask-type ROM as claimed in claim 19 is characterized in that: the material of those the 3rd conductor layers comprises doped polycrystalline silicon.
21, the structure of mask-type ROM as claimed in claim 19 is characterized in that: the dopant profile of those the 3rd conductor layers is different from the dopant profile of those second well regions.
22, the structure of mask-type ROM as claimed in claim 19 is characterized in that: the material of those the 4th conductor layers comprise be selected from group that aluminium, tungsten and copper organizes one of them.
23, the structure of mask-type ROM as claimed in claim 19 is characterized in that: the trend of those the 3rd conductor layers is perpendicular to the trend of those the 4th conductor layers.
24, the structure of mask-type ROM as claimed in claim 19 is characterized in that: also have plural layer second memory cell arrays, be stacked in regular turn on this second memory cell arrays.
25, a kind of interpretation method of mask-type ROM, this mask-type ROM comprises plurality of word lines at least, is configured in the well region of the plural number on those character lines, wherein the dopant profile of those character lines (N+type) is different from the dopant profile (P+type) of those well regions, and a plurality of bit lines, wherein those bit lines are arranged at differing heights perpendicular to those character lines and with those character lines, and the part confluce of those bit lines and those character lines is electrically connected to those well regions individually, it is characterized in that: this interpretation method comprises:
The pairing bit line in one decoding position is applied one first voltage, apply one second voltage for other those bit lines outside this bit line, wherein this first voltage is greater than this second voltage, simultaneously the pairing character line in this decoding position is applied a tertiary voltage, apply one the 4th voltage for other those character lines outside this character line, wherein the 4th voltage is greater than this tertiary voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031026907A CN100437983C (en) | 2003-02-14 | 2003-02-14 | Process of making mask ROM and arrangement thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031026907A CN100437983C (en) | 2003-02-14 | 2003-02-14 | Process of making mask ROM and arrangement thereof |
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| CN1521837A true CN1521837A (en) | 2004-08-18 |
| CN100437983C CN100437983C (en) | 2008-11-26 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101685827B (en) * | 2008-07-22 | 2011-07-20 | 旺宏电子股份有限公司 | Memory device and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5311039A (en) * | 1990-04-24 | 1994-05-10 | Seiko Epson Corporation | PROM and ROM memory cells |
| US5441907A (en) * | 1994-06-27 | 1995-08-15 | Taiwan Semiconductor Manufacturing Company | Process for manufacturing a plug-diode mask ROM |
| TW312851B (en) * | 1997-02-03 | 1997-08-11 | United Microelectronics Corp | Manufacturing method of read only memory by silicon on insulator process |
| TW329042B (en) * | 1997-02-17 | 1998-04-01 | United Microelectronics Corp | Binary ROM and its manufacturing method |
| NO308149B1 (en) * | 1998-06-02 | 2000-07-31 | Thin Film Electronics Asa | Scalable, integrated data processing device |
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| CN101685827B (en) * | 2008-07-22 | 2011-07-20 | 旺宏电子股份有限公司 | Memory device and its manufacturing method |
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| CN100437983C (en) | 2008-11-26 |
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